2 comedi/drivers/rtd520.c
3 Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2001 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: Real Time Devices PCI4520/DM7520
26 Devices: [Real Time Devices] DM7520HR-1 (rtd520), DM7520HR-8,
28 Status: Works. Only tested on DM7520-8. Not SMP safe.
30 Configuration options:
31 [0] - PCI bus of device (optional)
32 If bus / slot is not specified, the first available PCI
34 [1] - PCI slot of device (optional)
37 Created by Dan Christian, NASA Ames Research Center.
39 The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
41 8/16 12 bit ADC with FIFO and channel gain table
42 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
43 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
44 2 12 bit DACs with FIFOs
48 timers: ADC sample, pacer, burst, about, delay, DA1, DA2
50 3 user timer/counters (8254)
53 The DM7520 has slightly fewer features (fewer gain steps).
55 These boards can support external multiplexors and multi-board
56 synchronization, but this driver doesn't support that.
58 Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
59 Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
60 Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
61 Call them and ask for the register level manual.
62 PCI chip: http://www.plxtech.com/products/io/pci9080
65 This board is memory mapped. There is some IO stuff, but it isn't needed.
67 I use a pretty loose naming style within the driver (rtd_blah).
68 All externally visible names should be rtd520_blah.
69 I use camelCase for structures (and inside them).
70 I may also use upper CamelCase for function names (old habit).
72 This board is somewhat related to the RTD PCI4400 board.
74 I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
75 das1800, since they have the best documented code. Driver
76 cb_pcidas64.c uses the same DMA controller.
78 As far as I can tell, the About interrupt doesn't work if Sample is
79 also enabled. It turns out that About really isn't needed, since
80 we always count down samples read.
82 There was some timer/counter code, but it didn't follow the right API.
89 Analog-In supports instruction and command mode.
91 With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
92 (single channel, 64K read buffer). I get random system lockups when
93 using DMA with ALI-15xx based systems. I haven't been able to test
94 any other chipsets. The lockups happen soon after the start of an
95 acquistion, not in the middle of a long run.
97 Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
98 (with a 256K read buffer).
100 Digital-IO and Analog-Out only support instruction mode.
104 #include <linux/interrupt.h>
105 #include <linux/delay.h>
107 #include "../comedidev.h"
109 #define DRV_NAME "rtd520"
111 /*======================================================================
112 Driver specific stuff (tunable)
113 ======================================================================*/
114 /* Enable this to test the new DMA support. You may get hard lock ups */
117 /* We really only need 2 buffers. More than that means being much
118 smarter about knowing which ones are full. */
119 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
121 /* Target period for periodic transfers. This sets the user read latency. */
122 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
123 /* If this is too low, efficiency is poor */
124 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
126 /* Set a practical limit on how long a list to support (affects memory use) */
127 /* The board support a channel list up to the FIFO length (1K or 8K) */
128 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
130 /* tuning for ai/ao instruction done polling */
132 #define WAIT_QUIETLY /* as nothing, spin on done bit */
133 #define RTD_ADC_TIMEOUT 66000 /* 2 msec at 33mhz bus rate */
134 #define RTD_DAC_TIMEOUT 66000
135 #define RTD_DMA_TIMEOUT 33000 /* 1 msec */
137 /* by delaying, power and electrical noise are reduced somewhat */
138 #define WAIT_QUIETLY udelay(1)
139 #define RTD_ADC_TIMEOUT 2000 /* in usec */
140 #define RTD_DAC_TIMEOUT 2000 /* in usec */
141 #define RTD_DMA_TIMEOUT 1000 /* in usec */
144 /*======================================================================
146 ======================================================================*/
149 #define PCI_VENDOR_ID_RTD 0x1435
151 The board has three memory windows: las0, las1, and lcfg (the PCI chip)
152 Las1 has the data and can be burst DMAed 32bits at a time.
154 #define LCFG_PCIINDEX 0
155 /* PCI region 1 is a 256 byte IO space mapping. Use??? */
156 #define LAS0_PCIINDEX 2 /* PCI memory resources */
157 #define LAS1_PCIINDEX 3
158 #define LCFG_PCISIZE 0x100
159 #define LAS0_PCISIZE 0x200
160 #define LAS1_PCISIZE 0x10
162 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
163 #define RTD_CLOCK_BASE 125 /* clock period in ns */
165 /* Note: these speed are slower than the spec, but fit the counter resolution*/
166 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
167 /* max speed if we don't have to wait for settling */
168 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
170 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
171 /* min speed when only 1 channel (no burst counter) */
172 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
177 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
178 #define DMA_MODE_BITS (\
179 PLX_LOCAL_BUS_16_WIDE_BITS \
180 | PLX_DMA_EN_READYIN_BIT \
181 | PLX_DMA_LOCAL_BURST_EN_BIT \
183 | PLX_DMA_INTR_PCI_BIT \
184 | PLX_LOCAL_ADDR_CONST_BIT \
185 | PLX_DEMAND_MODE_BIT)
187 #define DMA_TRANSFER_BITS (\
188 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
189 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
190 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
192 /*======================================================================
193 Comedi specific stuff
194 ======================================================================*/
197 The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
199 static const struct comedi_lrange rtd_ai_7520_range = { 18, {
200 /* +-5V input range gain steps */
209 /* +-10V input range gain steps */
221 /* +10V input range gain steps */
237 /* PCI4520 has two more gains (6 more entries) */
238 static const struct comedi_lrange rtd_ai_4520_range = { 24, {
239 /* +-5V input range gain steps */
252 /* +-10V input range gain steps */
268 /* +10V input range gain steps */
287 /* Table order matches range values */
288 static const struct comedi_lrange rtd_ao_range = { 4, {
300 const char *name; /* must be first */
305 int range10Start; /* start of +-10V range */
306 int rangeUniStart; /* start of +10V range */
309 static const struct rtdBoard rtd520Boards[] = {
331 * Useful for shorthand access to the particular board structure
333 #define thisboard ((const struct rtdBoard *)dev->board_ptr)
336 This structure is for data unique to this hardware driver.
337 This is also unique for each board in the system.
340 /* memory mapped board structures */
345 unsigned long intCount; /* interrupt count */
346 long aiCount; /* total transfer size (samples) */
347 int transCount; /* # to transfer data. 0->1/2FIFO */
348 int flags; /* flag event modes */
350 /* PCI device info */
351 struct pci_dev *pci_dev;
352 int got_regions; /* non-zero if PCI regions owned */
354 /* channel list info */
355 /* chanBipolar tracks whether a channel is bipolar (and needs +2048) */
356 unsigned char chanBipolar[RTD_MAX_CHANLIST / 8]; /* bit array */
359 unsigned int aoValue[2]; /* Used for AO read back */
361 /* timer gate (when enabled) */
362 u8 utcGate[4]; /* 1 extra allows simple range check */
364 /* shadow registers affect other registers, but can't be read back */
365 /* The macros below update these on writes */
366 u16 intMask; /* interrupt mask */
367 u16 intClearMask; /* interrupt clear mask */
368 u8 utcCtrl[4]; /* crtl mode for 3 utc + read back */
369 u8 dioStatus; /* could be read back (dio0Ctrl) */
372 * Always DMA 1/2 FIFO. Buffer (dmaBuff?) is (at least) twice that
373 * size. After transferring, interrupt processes 1/2 FIFO and
376 s16 dma0Offset; /* current processing offset (0, 1/2) */
377 uint16_t *dma0Buff[DMA_CHAIN_COUNT]; /* DMA buffers (for ADC) */
378 dma_addr_t dma0BuffPhysAddr[DMA_CHAIN_COUNT]; /* physical addresses */
379 struct plx_dma_desc *dma0Chain; /* DMA descriptor ring for dmaBuff */
380 dma_addr_t dma0ChainPhysAddr; /* physical addresses */
381 /* shadow registers */
388 /* bit defines for "flags" */
389 #define SEND_EOS 0x01 /* send End Of Scan events */
390 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
391 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
393 /* Macros for accessing channel list bit array */
394 #define CHAN_ARRAY_TEST(array, index) \
395 (((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
396 #define CHAN_ARRAY_SET(array, index) \
397 (((array)[(index)/8] |= 1 << ((index) & 0x7)))
398 #define CHAN_ARRAY_CLEAR(array, index) \
399 (((array)[(index)/8] &= ~(1 << ((index) & 0x7))))
402 * most drivers define the following macro to make it easy to
403 * access the private structure.
405 #define devpriv ((struct rtdPrivate *)dev->private)
407 /* Macros to access registers */
409 /* pacer start/stop read=start, write=stop*/
410 #define RtdPacerStart(dev) \
411 readl(devpriv->las0+LAS0_PACER)
412 #define RtdPacerStop(dev) \
413 writel(0, devpriv->las0+LAS0_PACER)
415 /* Interrupt status */
416 #define RtdInterruptStatus(dev) \
417 readw(devpriv->las0+LAS0_IT)
420 #define RtdInterruptMask(dev, v) \
421 writew((devpriv->intMask = (v)), devpriv->las0+LAS0_IT)
423 /* Interrupt status clear (only bits set in mask) */
424 #define RtdInterruptClear(dev) \
425 readw(devpriv->las0+LAS0_CLEAR)
427 /* Interrupt clear mask */
428 #define RtdInterruptClearMask(dev, v) \
429 writew((devpriv->intClearMask = (v)), devpriv->las0+LAS0_CLEAR)
431 /* Interrupt overrun status */
432 #define RtdInterruptOverrunStatus(dev) \
433 readl(devpriv->las0+LAS0_OVERRUN)
435 /* Interrupt overrun clear */
436 #define RtdInterruptOverrunClear(dev) \
437 writel(0, devpriv->las0+LAS0_OVERRUN)
439 /* Pacer counter, 24bit */
440 #define RtdPacerCount(dev) \
441 readl(devpriv->las0+LAS0_PCLK)
442 #define RtdPacerCounter(dev, v) \
443 writel((v) & 0xffffff, devpriv->las0+LAS0_PCLK)
445 /* Burst counter, 10bit */
446 #define RtdBurstCount(dev) \
447 readl(devpriv->las0+LAS0_BCLK)
448 #define RtdBurstCounter(dev, v) \
449 writel((v) & 0x3ff, devpriv->las0+LAS0_BCLK)
451 /* Delay counter, 16bit */
452 #define RtdDelayCount(dev) \
453 readl(devpriv->las0+LAS0_DCLK)
454 #define RtdDelayCounter(dev, v) \
455 writel((v) & 0xffff, devpriv->las0+LAS0_DCLK)
457 /* About counter, 16bit */
458 #define RtdAboutCount(dev) \
459 readl(devpriv->las0+LAS0_ACNT)
460 #define RtdAboutCounter(dev, v) \
461 writel((v) & 0xffff, devpriv->las0+LAS0_ACNT)
463 /* ADC sample counter, 10bit */
464 #define RtdAdcSampleCount(dev) \
465 readl(devpriv->las0+LAS0_ADC_SCNT)
466 #define RtdAdcSampleCounter(dev, v) \
467 writel((v) & 0x3ff, devpriv->las0+LAS0_ADC_SCNT)
469 /* User Timer/Counter (8254) */
470 #define RtdUtcCounterGet(dev, n) \
471 readb(devpriv->las0 \
472 + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
474 #define RtdUtcCounterPut(dev, n, v) \
475 writeb((v) & 0xff, devpriv->las0 \
476 + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
478 /* Set UTC (8254) control byte */
479 #define RtdUtcCtrlPut(dev, n, v) \
480 writeb(devpriv->utcCtrl[(n) & 3] = (((n) & 3) << 6) | ((v) & 0x3f), \
481 devpriv->las0 + LAS0_UTC_CTRL)
483 /* Set UTCn clock source (write only) */
484 #define RtdUtcClockSource(dev, n, v) \
485 writew(v, devpriv->las0 \
486 + ((n <= 0) ? LAS0_UTC0_CLOCK : \
487 ((1 == n) ? LAS0_UTC1_CLOCK : LAS0_UTC2_CLOCK)))
489 /* Set UTCn gate source (write only) */
490 #define RtdUtcGateSource(dev, n, v) \
491 writew(v, devpriv->las0 \
492 + ((n <= 0) ? LAS0_UTC0_GATE : \
493 ((1 == n) ? LAS0_UTC1_GATE : LAS0_UTC2_GATE)))
495 /* User output N source select (write only) */
496 #define RtdUsrOutSource(dev, n, v) \
497 writel(v, devpriv->las0+((n <= 0) ? LAS0_UOUT0_SELECT : \
501 #define RtdDio0Read(dev) \
502 (readw(devpriv->las0+LAS0_DIO0) & 0xff)
503 #define RtdDio0Write(dev, v) \
504 writew((v) & 0xff, devpriv->las0+LAS0_DIO0)
506 #define RtdDio1Read(dev) \
507 (readw(devpriv->las0+LAS0_DIO1) & 0xff)
508 #define RtdDio1Write(dev, v) \
509 writew((v) & 0xff, devpriv->las0+LAS0_DIO1)
511 #define RtdDioStatusRead(dev) \
512 (readw(devpriv->las0+LAS0_DIO_STATUS) & 0xff)
513 #define RtdDioStatusWrite(dev, v) \
514 writew((devpriv->dioStatus = (v)), devpriv->las0+LAS0_DIO_STATUS)
516 #define RtdDio0CtrlRead(dev) \
517 (readw(devpriv->las0+LAS0_DIO0_CTRL) & 0xff)
518 #define RtdDio0CtrlWrite(dev, v) \
519 writew((v) & 0xff, devpriv->las0+LAS0_DIO0_CTRL)
521 /* Digital to Analog converter */
522 /* Write one data value (sign + 12bit + marker bits) */
523 /* Note: matches what DMA would put. Actual value << 3 */
524 #define RtdDacFifoPut(dev, n, v) \
525 writew((v), devpriv->las1 + (((n) == 0) ? LAS1_DAC1_FIFO : \
528 /* Start single DAC conversion */
529 #define RtdDacUpdate(dev, n) \
530 writew(0, devpriv->las0 + (((n) == 0) ? LAS0_DAC1 : LAS0_DAC2))
532 /* Start single DAC conversion on both DACs */
533 #define RtdDacBothUpdate(dev) \
534 writew(0, devpriv->las0+LAS0_DAC)
536 /* Set DAC output type and range */
537 #define RtdDacRange(dev, n, v) \
538 writew((v) & 7, devpriv->las0 \
539 +(((n) == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL))
542 #define RtdDacClearFifo(dev, n) \
543 writel(0, devpriv->las0+(((n) == 0) ? LAS0_DAC1_RESET : \
546 /* Set source for DMA 0 (write only, shadow?) */
547 #define RtdDma0Source(dev, n) \
548 writel((n) & 0xf, devpriv->las0+LAS0_DMA0_SRC)
550 /* Set source for DMA 1 (write only, shadow?) */
551 #define RtdDma1Source(dev, n) \
552 writel((n) & 0xf, devpriv->las0+LAS0_DMA1_SRC)
554 /* Reset board state for DMA 0 */
555 #define RtdDma0Reset(dev) \
556 writel(0, devpriv->las0+LAS0_DMA0_RESET)
558 /* Reset board state for DMA 1 */
559 #define RtdDma1Reset(dev) \
560 writel(0, devpriv->las0+LAS0_DMA1_SRC)
562 /* PLX9080 interrupt mask and status */
563 #define RtdPlxInterruptRead(dev) \
564 readl(devpriv->lcfg+LCFG_ITCSR)
565 #define RtdPlxInterruptWrite(dev, v) \
566 writel(v, devpriv->lcfg+LCFG_ITCSR)
568 /* Set mode for DMA 0 */
569 #define RtdDma0Mode(dev, m) \
570 writel((m), devpriv->lcfg+LCFG_DMAMODE0)
572 /* Set PCI address for DMA 0 */
573 #define RtdDma0PciAddr(dev, a) \
574 writel((a), devpriv->lcfg+LCFG_DMAPADR0)
576 /* Set local address for DMA 0 */
577 #define RtdDma0LocalAddr(dev, a) \
578 writel((a), devpriv->lcfg+LCFG_DMALADR0)
580 /* Set byte count for DMA 0 */
581 #define RtdDma0Count(dev, c) \
582 writel((c), devpriv->lcfg+LCFG_DMASIZ0)
584 /* Set next descriptor for DMA 0 */
585 #define RtdDma0Next(dev, a) \
586 writel((a), devpriv->lcfg+LCFG_DMADPR0)
588 /* Set mode for DMA 1 */
589 #define RtdDma1Mode(dev, m) \
590 writel((m), devpriv->lcfg+LCFG_DMAMODE1)
592 /* Set PCI address for DMA 1 */
593 #define RtdDma1PciAddr(dev, a) \
594 writel((a), devpriv->lcfg+LCFG_DMAADR1)
596 /* Set local address for DMA 1 */
597 #define RtdDma1LocalAddr(dev, a) \
598 writel((a), devpriv->lcfg+LCFG_DMALADR1)
600 /* Set byte count for DMA 1 */
601 #define RtdDma1Count(dev, c) \
602 writel((c), devpriv->lcfg+LCFG_DMASIZ1)
604 /* Set next descriptor for DMA 1 */
605 #define RtdDma1Next(dev, a) \
606 writel((a), devpriv->lcfg+LCFG_DMADPR1)
608 /* Set control for DMA 0 (write only, shadow?) */
609 #define RtdDma0Control(dev, n) \
610 writeb(devpriv->dma0Control = (n), devpriv->lcfg+LCFG_DMACSR0)
612 /* Get status for DMA 0 */
613 #define RtdDma0Status(dev) \
614 readb(devpriv->lcfg+LCFG_DMACSR0)
616 /* Set control for DMA 1 (write only, shadow?) */
617 #define RtdDma1Control(dev, n) \
618 writeb(devpriv->dma1Control = (n), devpriv->lcfg+LCFG_DMACSR1)
620 /* Get status for DMA 1 */
621 #define RtdDma1Status(dev) \
622 readb(devpriv->lcfg+LCFG_DMACSR1)
625 Given a desired period and the clock period (both in ns),
626 return the proper counter value (divider-1).
627 Sets the original period to be the true value.
628 Note: you have to check if the value is larger than the counter range!
630 static int rtd_ns_to_timer_base(unsigned int *nanosec, /* desired period (in ns) */
631 int round_mode, int base)
632 { /* clock period (in ns) */
635 switch (round_mode) {
636 case TRIG_ROUND_NEAREST:
638 divider = (*nanosec + base / 2) / base;
640 case TRIG_ROUND_DOWN:
641 divider = (*nanosec) / base;
644 divider = (*nanosec + base - 1) / base;
648 divider = 2; /* min is divide by 2 */
650 /* Note: we don't check for max, because different timers
651 have different ranges */
653 *nanosec = base * divider;
654 return divider - 1; /* countdown is divisor+1 */
658 Given a desired period (in ns),
659 return the proper counter value (divider-1) for the internal clock.
660 Sets the original period to be the true value.
662 static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
664 return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
668 Convert a single comedi channel-gain entry to a RTD520 table entry
670 static unsigned short rtdConvertChanGain(struct comedi_device *dev,
671 unsigned int comediChan, int chanIndex)
672 { /* index in channel list */
673 unsigned int chan, range, aref;
674 unsigned short r = 0;
676 chan = CR_CHAN(comediChan);
677 range = CR_RANGE(comediChan);
678 aref = CR_AREF(comediChan);
682 /* Note: we also setup the channel list bipolar flag array */
683 if (range < thisboard->range10Start) { /* first batch are +-5 */
684 r |= 0x000; /* +-5 range */
685 r |= (range & 0x7) << 4; /* gain */
686 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
687 } else if (range < thisboard->rangeUniStart) { /* second batch are +-10 */
688 r |= 0x100; /* +-10 range */
690 r |= ((range - thisboard->range10Start) & 0x7) << 4;
691 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
692 } else { /* last batch is +10 */
693 r |= 0x200; /* +10 range */
695 r |= ((range - thisboard->rangeUniStart) & 0x7) << 4;
696 CHAN_ARRAY_CLEAR(devpriv->chanBipolar, chanIndex);
700 case AREF_GROUND: /* on-board ground */
704 r |= 0x80; /* ref external analog common */
708 r |= 0x400; /* differential inputs */
711 case AREF_OTHER: /* ??? */
714 /*printk ("chan=%d r=%d a=%d -> 0x%x\n",
715 chan, range, aref, r); */
720 Setup the channel-gain table from a comedi list
722 static void rtd_load_channelgain_list(struct comedi_device *dev,
723 unsigned int n_chan, unsigned int *list)
725 if (n_chan > 1) { /* setup channel gain table */
728 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
729 writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
730 for (ii = 0; ii < n_chan; ii++) {
731 writel(rtdConvertChanGain(dev, list[ii], ii),
732 devpriv->las0 + LAS0_CGT_WRITE);
734 } else { /* just use the channel gain latch */
735 writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
736 writel(rtdConvertChanGain(dev, list[0], 0),
737 devpriv->las0 + LAS0_CGL_WRITE);
741 /* determine fifo size by doing adc conversions until the fifo half
742 empty status flag clears */
743 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
745 unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
747 static const unsigned limit = 0x2000;
748 unsigned fifo_size = 0;
750 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
751 rtd_load_channelgain_list(dev, 1, &chanspec);
752 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
753 /* convert samples */
754 for (i = 0; i < limit; ++i) {
755 unsigned fifo_status;
756 /* trigger conversion */
757 writew(0, devpriv->las0 + LAS0_ADC);
759 fifo_status = readl(devpriv->las0 + LAS0_ADC);
760 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
766 printk(KERN_INFO "\ncomedi: %s: failed to probe fifo size.\n",
770 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
771 if (fifo_size != 0x400 && fifo_size != 0x2000) {
773 (KERN_INFO "\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n",
774 DRV_NAME, fifo_size);
781 "instructions" read/write data in "one-shot" or "software-triggered"
782 mode (simplest case).
783 This doesn't use interrupts.
785 Note, we don't do any settling delays. Use a instruction list to
786 select, delay, then read.
788 static int rtd_ai_rinsn(struct comedi_device *dev,
789 struct comedi_subdevice *s, struct comedi_insn *insn,
795 /* clear any old fifo data */
796 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
798 /* write channel to multiplexer and clear channel gain table */
799 rtd_load_channelgain_list(dev, 1, &insn->chanspec);
801 /* set conversion source */
802 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
804 /* convert n samples */
805 for (n = 0; n < insn->n; n++) {
807 /* trigger conversion */
808 writew(0, devpriv->las0 + LAS0_ADC);
810 for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
811 stat = readl(devpriv->las0 + LAS0_ADC);
812 if (stat & FS_ADC_NOT_EMPTY) /* 1 -> not empty */
816 if (ii >= RTD_ADC_TIMEOUT) {
818 ("rtd520: Error: ADC never finished! FifoStatus=0x%x\n",
824 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
825 /*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
826 d = d >> 3; /* low 3 bits are marker lines */
827 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
828 /* convert to comedi unsigned data */
834 /* return the number of samples read/written */
839 Get what we know is there.... Fast!
840 This uses 1/2 the bus cycles of read_dregs (below).
842 The manual claims that we can do a lword read, but it doesn't work here.
844 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
849 for (ii = 0; ii < count; ii++) {
853 if (0 == devpriv->aiCount) { /* done */
854 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
858 if (!(readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY)) {
859 DPRINTK("comedi: READ OOPS on %d of %d\n", ii + 1,
864 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
866 d = d >> 3; /* low 3 bits are marker lines */
867 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
868 /* convert to comedi unsigned data */
873 if (!comedi_buf_put(s->async, sample))
876 if (devpriv->aiCount > 0) /* < 0, means read forever */
883 unknown amout of data is waiting in fifo.
885 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
887 while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
889 s16 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
891 if (0 == devpriv->aiCount) { /* done */
892 continue; /* read rest */
895 d = d >> 3; /* low 3 bits are marker lines */
896 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
897 /* convert to comedi unsigned data */
902 if (!comedi_buf_put(s->async, sample))
905 if (devpriv->aiCount > 0) /* < 0, means read forever */
913 Terminate a DMA transfer and wait for everything to quiet down
915 void abort_dma(struct comedi_device *dev, unsigned int channel)
916 { /* DMA channel 0, 1 */
917 unsigned long dma_cs_addr; /* the control/status register */
920 /* unsigned long flags; */
922 dma_cs_addr = (unsigned long)devpriv->lcfg
923 + ((channel == 0) ? LCFG_DMACSR0 : LCFG_DMACSR1);
925 /* spinlock for plx dma control/status reg */
926 /* spin_lock_irqsave( &dev->spinlock, flags ); */
928 /* abort dma transfer if necessary */
929 status = readb(dma_cs_addr);
930 if ((status & PLX_DMA_EN_BIT) == 0) { /* not enabled (Error?) */
931 DPRINTK("rtd520: AbortDma on non-active channel %d (0x%x)\n",
936 /* wait to make sure done bit is zero (needed?) */
937 for (ii = 0; (status & PLX_DMA_DONE_BIT) && ii < RTD_DMA_TIMEOUT; ii++) {
939 status = readb(dma_cs_addr);
941 if (status & PLX_DMA_DONE_BIT) {
942 printk("rtd520: Timeout waiting for dma %i done clear\n",
947 /* disable channel (required) */
948 writeb(0, dma_cs_addr);
949 udelay(1); /* needed?? */
950 /* set abort bit for channel */
951 writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
953 /* wait for dma done bit to be set */
954 status = readb(dma_cs_addr);
956 (status & PLX_DMA_DONE_BIT) == 0 && ii < RTD_DMA_TIMEOUT; ii++) {
957 status = readb(dma_cs_addr);
960 if ((status & PLX_DMA_DONE_BIT) == 0) {
961 printk("rtd520: Timeout waiting for dma %i done set\n",
966 /* spin_unlock_irqrestore( &dev->spinlock, flags ); */
970 Process what is in the DMA transfer buffer and pass to comedi
971 Note: this is not re-entrant
973 static int ai_process_dma(struct comedi_device *dev, struct comedi_subdevice *s)
978 if (devpriv->aiCount == 0) /* transfer already complete */
981 dp = devpriv->dma0Buff[devpriv->dma0Offset];
982 for (ii = 0; ii < devpriv->fifoLen / 2;) { /* convert samples */
985 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
986 sample = (*dp >> 3) + 2048; /* convert to comedi unsigned data */
988 sample = *dp >> 3; /* low 3 bits are marker lines */
990 *dp++ = sample; /* put processed value back */
992 if (++s->async->cur_chan >= s->async->cmd.chanlist_len)
993 s->async->cur_chan = 0;
995 ++ii; /* number ready to transfer */
996 if (devpriv->aiCount > 0) { /* < 0, means read forever */
997 if (--devpriv->aiCount == 0) { /* done */
998 /*DPRINTK ("rtd520: Final %d samples\n", ii); */
1004 /* now pass the whole array to the comedi buffer */
1005 dp = devpriv->dma0Buff[devpriv->dma0Offset];
1006 n = comedi_buf_write_alloc(s->async, ii * sizeof(s16));
1007 if (n < (ii * sizeof(s16))) { /* any residual is an error */
1008 DPRINTK("rtd520:ai_process_dma buffer overflow %d samples!\n",
1009 ii - (n / sizeof(s16)));
1010 s->async->events |= COMEDI_CB_ERROR;
1013 comedi_buf_memcpy_to(s->async, 0, dp, n);
1014 comedi_buf_write_free(s->async, n);
1017 * always at least 1 scan -- 1/2 FIFO is larger than our max scan list
1019 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
1021 if (++devpriv->dma0Offset >= DMA_CHAIN_COUNT) { /* next buffer */
1022 devpriv->dma0Offset = 0;
1026 #endif /* USE_DMA */
1029 Handle all rtd520 interrupts.
1030 Runs atomically and is never re-entered.
1031 This is a "slow handler"; other interrupts may be active.
1032 The data conversion may someday happen in a "bottom half".
1034 static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */
1036 { /* our data *//* cpu context (ignored) */
1037 struct comedi_device *dev = d; /* must be called "dev" for devpriv */
1040 struct comedi_subdevice *s = dev->subdevices + 0; /* analog in subdevice */
1045 devpriv->intCount++; /* DEBUG statistics */
1047 fifoStatus = readl(devpriv->las0 + LAS0_ADC);
1048 /* check for FIFO full, this automatically halts the ADC! */
1049 if (!(fifoStatus & FS_ADC_NOT_FULL)) { /* 0 -> full */
1050 DPRINTK("rtd520: FIFO full! fifo_status=0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1054 if (devpriv->flags & DMA0_ACTIVE) { /* Check DMA */
1055 u32 istatus = RtdPlxInterruptRead(dev);
1057 if (istatus & ICS_DMA0_A) {
1058 if (ai_process_dma(dev, s) < 0) {
1060 ("rtd520: comedi read buffer overflow (DMA) with %ld to go!\n",
1063 (devpriv->dma0Control &
1065 | PLX_CLEAR_DMA_INTR_BIT);
1069 /*DPRINTK ("rtd520: DMA transfer: %ld to go, istatus %x\n",
1070 devpriv->aiCount, istatus); */
1073 dma0Control & ~PLX_DMA_START_BIT)
1074 | PLX_CLEAR_DMA_INTR_BIT);
1075 if (0 == devpriv->aiCount) { /* counted down */
1076 DPRINTK("rtd520: Samples Done (DMA).\n");
1079 comedi_event(dev, s);
1081 /*DPRINTK ("rtd520: No DMA ready: istatus %x\n", istatus); */
1084 /* Fall through and check for other interrupt sources */
1085 #endif /* USE_DMA */
1087 status = RtdInterruptStatus(dev);
1088 /* if interrupt was not caused by our board, or handled above */
1092 if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
1093 /* since the priority interrupt controller may have queued a sample
1094 counter interrupt, even though we have already finished,
1095 we must handle the possibility that there is no data here */
1096 if (!(fifoStatus & FS_ADC_HEMPTY)) { /* 0 -> 1/2 full */
1097 /*DPRINTK("rtd520: Sample int, reading 1/2FIFO. fifo_status 0x%x\n",
1098 (fifoStatus ^ 0x6666) & 0x7777); */
1099 if (ai_read_n(dev, s, devpriv->fifoLen / 2) < 0) {
1101 ("rtd520: comedi read buffer overflow (1/2FIFO) with %ld to go!\n",
1105 if (0 == devpriv->aiCount) { /* counted down */
1106 DPRINTK("rtd520: Samples Done (1/2). fifo_status was 0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1109 comedi_event(dev, s);
1110 } else if (devpriv->transCount > 0) { /* read often */
1111 /*DPRINTK("rtd520: Sample int, reading %d fifo_status 0x%x\n",
1112 devpriv->transCount, (fifoStatus ^ 0x6666) & 0x7777); */
1113 if (fifoStatus & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
1114 if (ai_read_n(dev, s, devpriv->transCount) < 0) {
1116 ("rtd520: comedi read buffer overflow (N) with %ld to go!\n",
1120 if (0 == devpriv->aiCount) { /* counted down */
1122 ("rtd520: Samples Done (N). fifo_status was 0x%x\n",
1123 (fifoStatus ^ 0x6666) & 0x7777);
1126 comedi_event(dev, s);
1128 } else { /* wait for 1/2 FIFO (old) */
1130 ("rtd520: Sample int. Wait for 1/2. fifo_status 0x%x\n",
1131 (fifoStatus ^ 0x6666) & 0x7777);
1134 DPRINTK("rtd520: unknown interrupt source!\n");
1137 if (0xffff & RtdInterruptOverrunStatus(dev)) { /* interrupt overrun */
1139 ("rtd520: Interrupt overrun with %ld to go! over_status=0x%x\n",
1140 devpriv->aiCount, 0xffff & RtdInterruptOverrunStatus(dev));
1144 /* clear the interrupt */
1145 RtdInterruptClearMask(dev, status);
1146 RtdInterruptClear(dev);
1150 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1151 s->async->events |= COMEDI_CB_ERROR;
1152 devpriv->aiCount = 0; /* stop and don't transfer any more */
1153 /* fall into transferDone */
1156 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1157 RtdPacerStop(dev); /* Stop PACER */
1158 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1159 RtdInterruptMask(dev, 0); /* mask out SAMPLE */
1161 if (devpriv->flags & DMA0_ACTIVE) {
1162 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1163 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1165 devpriv->flags &= ~DMA0_ACTIVE;
1166 /* if Using DMA, then we should have read everything by now */
1167 if (devpriv->aiCount > 0) {
1168 DPRINTK("rtd520: Lost DMA data! %ld remain\n",
1172 #endif /* USE_DMA */
1174 if (devpriv->aiCount > 0) { /* there shouldn't be anything left */
1175 fifoStatus = readl(devpriv->las0 + LAS0_ADC);
1176 DPRINTK("rtd520: Finishing up. %ld remain, fifoStat=%x\n", devpriv->aiCount, (fifoStatus ^ 0x6666) & 0x7777); /* should read all 0s */
1177 ai_read_dregs(dev, s); /* read anything left in FIFO */
1180 s->async->events |= COMEDI_CB_EOA; /* signal end to comedi */
1181 comedi_event(dev, s);
1183 /* clear the interrupt */
1184 status = RtdInterruptStatus(dev);
1185 RtdInterruptClearMask(dev, status);
1186 RtdInterruptClear(dev);
1188 fifoStatus = readl(devpriv->las0 + LAS0_ADC);
1190 ("rtd520: Acquisition complete. %ld ints, intStat=%x, overStat=%x\n",
1191 devpriv->intCount, status,
1192 0xffff & RtdInterruptOverrunStatus(dev));
1199 return the number of samples available
1201 static int rtd_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1203 /* TODO: This needs to mask interrupts, read_dregs, and then re-enable */
1204 /* Not sure what to do if DMA is active */
1205 return s->async->buf_write_count - s->async->buf_read_count;
1210 cmdtest tests a particular command to see if it is valid.
1211 Using the cmdtest ioctl, a user can create a valid cmd
1212 and then have it executed by the cmd ioctl (asyncronously).
1214 cmdtest returns 1,2,3,4 or 0, depending on which tests
1218 static int rtd_ai_cmdtest(struct comedi_device *dev,
1219 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1224 /* step 1: make sure trigger sources are trivially valid */
1226 tmp = cmd->start_src;
1227 cmd->start_src &= TRIG_NOW;
1228 if (!cmd->start_src || tmp != cmd->start_src)
1231 tmp = cmd->scan_begin_src;
1232 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
1233 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1237 tmp = cmd->convert_src;
1238 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1239 if (!cmd->convert_src || tmp != cmd->convert_src)
1243 tmp = cmd->scan_end_src;
1244 cmd->scan_end_src &= TRIG_COUNT;
1245 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1249 tmp = cmd->stop_src;
1250 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1251 if (!cmd->stop_src || tmp != cmd->stop_src)
1258 /* step 2: make sure trigger sources are unique
1259 and mutually compatible */
1260 /* note that mutual compatibility is not an issue here */
1261 if (cmd->scan_begin_src != TRIG_TIMER &&
1262 cmd->scan_begin_src != TRIG_EXT) {
1265 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1268 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1274 /* step 3: make sure arguments are trivially compatible */
1276 if (cmd->start_arg != 0) {
1281 if (cmd->scan_begin_src == TRIG_TIMER) {
1282 /* Note: these are time periods, not actual rates */
1283 if (1 == cmd->chanlist_len) { /* no scanning */
1284 if (cmd->scan_begin_arg < RTD_MAX_SPEED_1) {
1285 cmd->scan_begin_arg = RTD_MAX_SPEED_1;
1286 rtd_ns_to_timer(&cmd->scan_begin_arg,
1290 if (cmd->scan_begin_arg > RTD_MIN_SPEED_1) {
1291 cmd->scan_begin_arg = RTD_MIN_SPEED_1;
1292 rtd_ns_to_timer(&cmd->scan_begin_arg,
1297 if (cmd->scan_begin_arg < RTD_MAX_SPEED) {
1298 cmd->scan_begin_arg = RTD_MAX_SPEED;
1299 rtd_ns_to_timer(&cmd->scan_begin_arg,
1303 if (cmd->scan_begin_arg > RTD_MIN_SPEED) {
1304 cmd->scan_begin_arg = RTD_MIN_SPEED;
1305 rtd_ns_to_timer(&cmd->scan_begin_arg,
1311 /* external trigger */
1312 /* should be level/edge, hi/lo specification here */
1313 /* should specify multiple external triggers */
1314 if (cmd->scan_begin_arg > 9) {
1315 cmd->scan_begin_arg = 9;
1319 if (cmd->convert_src == TRIG_TIMER) {
1320 if (1 == cmd->chanlist_len) { /* no scanning */
1321 if (cmd->convert_arg < RTD_MAX_SPEED_1) {
1322 cmd->convert_arg = RTD_MAX_SPEED_1;
1323 rtd_ns_to_timer(&cmd->convert_arg,
1327 if (cmd->convert_arg > RTD_MIN_SPEED_1) {
1328 cmd->convert_arg = RTD_MIN_SPEED_1;
1329 rtd_ns_to_timer(&cmd->convert_arg,
1334 if (cmd->convert_arg < RTD_MAX_SPEED) {
1335 cmd->convert_arg = RTD_MAX_SPEED;
1336 rtd_ns_to_timer(&cmd->convert_arg,
1340 if (cmd->convert_arg > RTD_MIN_SPEED) {
1341 cmd->convert_arg = RTD_MIN_SPEED;
1342 rtd_ns_to_timer(&cmd->convert_arg,
1348 /* external trigger */
1350 if (cmd->convert_arg > 9) {
1351 cmd->convert_arg = 9;
1357 if (cmd->scan_end_arg != cmd->chanlist_len) {
1358 cmd->scan_end_arg = cmd->chanlist_len;
1362 if (cmd->stop_src == TRIG_COUNT) {
1363 /* TODO check for rounding error due to counter wrap */
1367 if (cmd->stop_arg != 0) {
1377 /* step 4: fix up any arguments */
1379 if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
1380 cmd->chanlist_len = RTD_MAX_CHANLIST;
1383 if (cmd->scan_begin_src == TRIG_TIMER) {
1384 tmp = cmd->scan_begin_arg;
1385 rtd_ns_to_timer(&cmd->scan_begin_arg,
1386 cmd->flags & TRIG_ROUND_MASK);
1387 if (tmp != cmd->scan_begin_arg)
1391 if (cmd->convert_src == TRIG_TIMER) {
1392 tmp = cmd->convert_arg;
1393 rtd_ns_to_timer(&cmd->convert_arg,
1394 cmd->flags & TRIG_ROUND_MASK);
1395 if (tmp != cmd->convert_arg)
1398 if (cmd->scan_begin_src == TRIG_TIMER
1399 && (cmd->scan_begin_arg
1400 < (cmd->convert_arg * cmd->scan_end_arg))) {
1401 cmd->scan_begin_arg =
1402 cmd->convert_arg * cmd->scan_end_arg;
1414 Execute a analog in command with many possible triggering options.
1415 The data get stored in the async structure of the subdevice.
1416 This is usually done by an interrupt handler.
1417 Userland gets to the data using read calls.
1419 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1421 struct comedi_cmd *cmd = &s->async->cmd;
1424 /* stop anything currently running */
1425 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1426 RtdPacerStop(dev); /* make sure PACER is stopped */
1427 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1428 RtdInterruptMask(dev, 0);
1430 if (devpriv->flags & DMA0_ACTIVE) { /* cancel anything running */
1431 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1432 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1434 devpriv->flags &= ~DMA0_ACTIVE;
1435 if (RtdPlxInterruptRead(dev) & ICS_DMA0_A) { /*clear pending int */
1436 RtdDma0Control(dev, PLX_CLEAR_DMA_INTR_BIT);
1439 RtdDma0Reset(dev); /* reset onboard state */
1440 #endif /* USE_DMA */
1441 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1442 RtdInterruptOverrunClear(dev);
1443 devpriv->intCount = 0;
1445 if (!dev->irq) { /* we need interrupts for this */
1446 DPRINTK("rtd520: ERROR! No interrupt available!\n");
1450 /* start configuration */
1451 /* load channel list and reset CGT */
1452 rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
1454 /* setup the common case and override if needed */
1455 if (cmd->chanlist_len > 1) {
1456 /*DPRINTK ("rtd520: Multi channel setup\n"); */
1457 writel(0, devpriv->las0 + LAS0_PACER_START);
1458 writel(1, devpriv->las0 + LAS0_BURST_START);
1459 writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
1460 } else { /* single channel */
1461 /*DPRINTK ("rtd520: single channel setup\n"); */
1462 writel(0, devpriv->las0 + LAS0_PACER_START);
1463 writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
1465 RtdAboutCounter(dev, devpriv->fifoLen / 2 - 1); /* 1/2 FIFO */
1467 if (TRIG_TIMER == cmd->scan_begin_src) {
1468 /* scan_begin_arg is in nanoseconds */
1469 /* find out how many samples to wait before transferring */
1470 if (cmd->flags & TRIG_WAKE_EOS) {
1471 /* this may generate un-sustainable interrupt rates */
1472 /* the application is responsible for doing the right thing */
1473 devpriv->transCount = cmd->chanlist_len;
1474 devpriv->flags |= SEND_EOS;
1476 /* arrange to transfer data periodically */
1479 (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
1480 cmd->scan_begin_arg;
1481 if (devpriv->transCount < cmd->chanlist_len) {
1482 /* transfer after each scan (and avoid 0) */
1483 devpriv->transCount = cmd->chanlist_len;
1484 } else { /* make a multiple of scan length */
1485 devpriv->transCount =
1486 (devpriv->transCount +
1487 cmd->chanlist_len - 1)
1488 / cmd->chanlist_len;
1489 devpriv->transCount *= cmd->chanlist_len;
1491 devpriv->flags |= SEND_EOS;
1493 if (devpriv->transCount >= (devpriv->fifoLen / 2)) {
1494 /* out of counter range, use 1/2 fifo instead */
1495 devpriv->transCount = 0;
1496 devpriv->flags &= ~SEND_EOS;
1498 /* interrupt for each transfer */
1499 RtdAboutCounter(dev, devpriv->transCount - 1);
1503 ("rtd520: scanLen=%d transferCount=%d fifoLen=%d\n scanTime(ns)=%d flags=0x%x\n",
1504 cmd->chanlist_len, devpriv->transCount, devpriv->fifoLen,
1505 cmd->scan_begin_arg, devpriv->flags);
1506 } else { /* unknown timing, just use 1/2 FIFO */
1507 devpriv->transCount = 0;
1508 devpriv->flags &= ~SEND_EOS;
1510 writel(1, devpriv->las0 + LAS0_PACER_SELECT);
1511 writel(1, devpriv->las0 + LAS0_ACNT_STOP_ENABLE);
1513 /* BUG??? these look like enumerated values, but they are bit fields */
1515 /* First, setup when to stop */
1516 switch (cmd->stop_src) {
1517 case TRIG_COUNT: /* stop after N scans */
1518 devpriv->aiCount = cmd->stop_arg * cmd->chanlist_len;
1519 if ((devpriv->transCount > 0)
1520 && (devpriv->transCount > devpriv->aiCount)) {
1521 devpriv->transCount = devpriv->aiCount;
1525 case TRIG_NONE: /* stop when cancel is called */
1526 devpriv->aiCount = -1; /* read forever */
1530 DPRINTK("rtd520: Warning! ignoring stop_src mode %d\n",
1535 switch (cmd->scan_begin_src) {
1536 case TRIG_TIMER: /* periodic scanning */
1537 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
1538 TRIG_ROUND_NEAREST);
1539 /* set PACER clock */
1540 /*DPRINTK ("rtd520: loading %d into pacer\n", timer); */
1541 RtdPacerCounter(dev, timer);
1546 writel(1, devpriv->las0 + LAS0_PACER_START);
1550 DPRINTK("rtd520: Warning! ignoring scan_begin_src mode %d\n",
1551 cmd->scan_begin_src);
1554 /* Sample timing within a scan */
1555 switch (cmd->convert_src) {
1556 case TRIG_TIMER: /* periodic */
1557 if (cmd->chanlist_len > 1) { /* only needed for multi-channel */
1558 timer = rtd_ns_to_timer(&cmd->convert_arg,
1559 TRIG_ROUND_NEAREST);
1560 /* setup BURST clock */
1561 /*DPRINTK ("rtd520: loading %d into burst\n", timer); */
1562 RtdBurstCounter(dev, timer);
1567 case TRIG_EXT: /* external */
1568 writel(2, devpriv->las0 + LAS0_BURST_START);
1572 DPRINTK("rtd520: Warning! ignoring convert_src mode %d\n",
1575 /* end configuration */
1577 /* This doesn't seem to work. There is no way to clear an interrupt
1578 that the priority controller has queued! */
1579 RtdInterruptClearMask(dev, ~0); /* clear any existing flags */
1580 RtdInterruptClear(dev);
1582 /* TODO: allow multiple interrupt sources */
1583 if (devpriv->transCount > 0) { /* transfer every N samples */
1584 RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
1585 DPRINTK("rtd520: Transferring every %d\n", devpriv->transCount);
1586 } else { /* 1/2 FIFO transfers */
1588 devpriv->flags |= DMA0_ACTIVE;
1590 /* point to first transfer in ring */
1591 devpriv->dma0Offset = 0;
1592 RtdDma0Mode(dev, DMA_MODE_BITS);
1593 RtdDma0Next(dev, /* point to first block */
1594 devpriv->dma0Chain[DMA_CHAIN_COUNT - 1].next);
1595 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL); /* set DMA trigger source */
1597 RtdPlxInterruptWrite(dev, /* enable interrupt */
1598 RtdPlxInterruptRead(dev) | ICS_DMA0_E);
1599 /* Must be 2 steps. See PLX app note about "Starting a DMA transfer" */
1600 RtdDma0Control(dev, PLX_DMA_EN_BIT); /* enable DMA (clear INTR?) */
1601 RtdDma0Control(dev, PLX_DMA_EN_BIT | PLX_DMA_START_BIT); /*start DMA */
1602 DPRINTK("rtd520: Using DMA0 transfers. plxInt %x RtdInt %x\n",
1603 RtdPlxInterruptRead(dev), devpriv->intMask);
1605 RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
1606 DPRINTK("rtd520: Transferring every 1/2 FIFO\n");
1607 #endif /* USE_DMA */
1610 /* BUG: start_src is ASSUMED to be TRIG_NOW */
1611 /* BUG? it seems like things are running before the "start" */
1612 RtdPacerStart(dev); /* Start PACER */
1617 Stop a running data acquisition.
1619 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1623 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1624 RtdPacerStop(dev); /* Stop PACER */
1625 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1626 RtdInterruptMask(dev, 0);
1627 devpriv->aiCount = 0; /* stop and don't transfer any more */
1629 if (devpriv->flags & DMA0_ACTIVE) {
1630 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1631 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1633 devpriv->flags &= ~DMA0_ACTIVE;
1635 #endif /* USE_DMA */
1636 status = RtdInterruptStatus(dev);
1638 ("rtd520: Acquisition canceled. %ld ints, intStat=%x, overStat=%x\n",
1639 devpriv->intCount, status,
1640 0xffff & RtdInterruptOverrunStatus(dev));
1645 Output one (or more) analog values to a single port as fast as possible.
1647 static int rtd_ao_winsn(struct comedi_device *dev,
1648 struct comedi_subdevice *s, struct comedi_insn *insn,
1652 int chan = CR_CHAN(insn->chanspec);
1653 int range = CR_RANGE(insn->chanspec);
1655 /* Configure the output range (table index matches the range values) */
1656 RtdDacRange(dev, chan, range);
1658 /* Writing a list of values to an AO channel is probably not
1659 * very useful, but that's how the interface is defined. */
1660 for (i = 0; i < insn->n; ++i) {
1661 int val = data[i] << 3;
1662 int stat = 0; /* initialize to avoid bogus warning */
1665 /* VERIFY: comedi range and offset conversions */
1667 if ((range > 1) /* bipolar */
1668 && (data[i] < 2048)) {
1669 /* offset and sign extend */
1670 val = (((int)data[i]) - 2048) << 3;
1671 } else { /* unipolor */
1676 ("comedi: rtd520 DAC chan=%d range=%d writing %d as 0x%x\n",
1677 chan, range, data[i], val);
1679 /* a typical programming sequence */
1680 RtdDacFifoPut(dev, chan, val); /* put the value in */
1681 RtdDacUpdate(dev, chan); /* trigger the conversion */
1683 devpriv->aoValue[chan] = data[i]; /* save for read back */
1685 for (ii = 0; ii < RTD_DAC_TIMEOUT; ++ii) {
1686 stat = readl(devpriv->las0 + LAS0_ADC);
1687 /* 1 -> not empty */
1688 if (stat & ((0 == chan) ? FS_DAC1_NOT_EMPTY :
1693 if (ii >= RTD_DAC_TIMEOUT) {
1695 ("rtd520: Error: DAC never finished! FifoStatus=0x%x\n",
1701 /* return the number of samples read/written */
1705 /* AO subdevices should have a read insn as well as a write insn.
1706 * Usually this means copying a value stored in devpriv. */
1707 static int rtd_ao_rinsn(struct comedi_device *dev,
1708 struct comedi_subdevice *s, struct comedi_insn *insn,
1712 int chan = CR_CHAN(insn->chanspec);
1714 for (i = 0; i < insn->n; i++)
1715 data[i] = devpriv->aoValue[chan];
1722 Write a masked set of bits and the read back the port.
1723 We track what the bits should be (i.e. we don't read the port first).
1725 DIO devices are slightly special. Although it is possible to
1726 * implement the insn_read/insn_write interface, it is much more
1727 * useful to applications if you implement the insn_bits interface.
1728 * This allows packed reading/writing of the DIO channels. The
1729 * comedi core can convert between insn_bits and insn_read/write
1731 static int rtd_dio_insn_bits(struct comedi_device *dev,
1732 struct comedi_subdevice *s,
1733 struct comedi_insn *insn, unsigned int *data)
1735 /* The insn data is a mask in data[0] and the new data
1736 * in data[1], each channel cooresponding to a bit. */
1738 s->state &= ~data[0];
1739 s->state |= data[0] & data[1];
1741 /* Write out the new digital output lines */
1742 RtdDio0Write(dev, s->state);
1744 /* on return, data[1] contains the value of the digital
1746 data[1] = RtdDio0Read(dev);
1748 /*DPRINTK("rtd520:port_0 wrote: 0x%x read: 0x%x\n", s->state, data[1]); */
1754 Configure one bit on a IO port as Input or Output (hence the name :-).
1756 static int rtd_dio_insn_config(struct comedi_device *dev,
1757 struct comedi_subdevice *s,
1758 struct comedi_insn *insn, unsigned int *data)
1760 int chan = CR_CHAN(insn->chanspec);
1762 /* The input or output configuration of each digital line is
1763 * configured by a special insn_config instruction. chanspec
1764 * contains the channel to be changed, and data[0] contains the
1765 * value COMEDI_INPUT or COMEDI_OUTPUT. */
1767 case INSN_CONFIG_DIO_OUTPUT:
1768 s->io_bits |= 1 << chan; /* 1 means Out */
1770 case INSN_CONFIG_DIO_INPUT:
1771 s->io_bits &= ~(1 << chan);
1773 case INSN_CONFIG_DIO_QUERY:
1775 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1782 DPRINTK("rtd520: port_0_direction=0x%x (1 means out)\n", s->io_bits);
1783 /* TODO support digital match interrupts and strobes */
1784 RtdDioStatusWrite(dev, 0x01); /* make Dio0Ctrl point to direction */
1785 RtdDio0CtrlWrite(dev, s->io_bits); /* set direction 1 means Out */
1786 RtdDioStatusWrite(dev, 0); /* make Dio0Ctrl clear interrupts */
1788 /* port1 can only be all input or all output */
1790 /* there are also 2 user input lines and 2 user output lines */
1795 static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1796 { /* board name and options flags */
1797 struct comedi_subdevice *s;
1798 struct pci_dev *pcidev;
1800 resource_size_t physLas0; /* configuration */
1801 resource_size_t physLas1; /* data area */
1802 resource_size_t physLcfg; /* PLX9080 */
1807 printk(KERN_INFO "comedi%d: rtd520 attaching.\n", dev->minor);
1809 #if defined(CONFIG_COMEDI_DEBUG) && defined(USE_DMA)
1810 /* You can set this a load time: modprobe comedi comedi_debug=1 */
1811 if (0 == comedi_debug) /* force DMA debug printks */
1816 * Allocate the private structure area. alloc_private() is a
1817 * convenient macro defined in comedidev.h.
1819 if (alloc_private(dev, sizeof(struct rtdPrivate)) < 0)
1823 * Probe the device to determine what device in the series it is.
1825 for (pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, NULL);
1827 pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, pcidev)) {
1830 if (it->options[0] || it->options[1]) {
1831 if (pcidev->bus->number != it->options[0]
1832 || PCI_SLOT(pcidev->devfn) != it->options[1]) {
1836 for (i = 0; i < ARRAY_SIZE(rtd520Boards); ++i) {
1837 if (pcidev->device == rtd520Boards[i].device_id) {
1838 dev->board_ptr = &rtd520Boards[i];
1843 break; /* found one */
1846 if (it->options[0] && it->options[1]) {
1847 printk(KERN_INFO "No RTD card at bus=%d slot=%d.\n",
1848 it->options[0], it->options[1]);
1850 printk(KERN_INFO "No RTD card found.\n");
1854 devpriv->pci_dev = pcidev;
1855 dev->board_name = thisboard->name;
1857 ret = comedi_pci_enable(pcidev, DRV_NAME);
1859 printk(KERN_INFO "Failed to enable PCI device and request regions.\n");
1862 devpriv->got_regions = 1;
1865 * Initialize base addresses
1867 /* Get the physical address from PCI config */
1868 physLas0 = pci_resource_start(devpriv->pci_dev, LAS0_PCIINDEX);
1869 physLas1 = pci_resource_start(devpriv->pci_dev, LAS1_PCIINDEX);
1870 physLcfg = pci_resource_start(devpriv->pci_dev, LCFG_PCIINDEX);
1871 /* Now have the kernel map this into memory */
1872 /* ASSUME page aligned */
1873 devpriv->las0 = ioremap_nocache(physLas0, LAS0_PCISIZE);
1874 devpriv->las1 = ioremap_nocache(physLas1, LAS1_PCISIZE);
1875 devpriv->lcfg = ioremap_nocache(physLcfg, LCFG_PCISIZE);
1877 if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
1881 DPRINTK("%s: LAS0=%llx, LAS1=%llx, CFG=%llx.\n", dev->board_name,
1882 (unsigned long long)physLas0, (unsigned long long)physLas1,
1883 (unsigned long long)physLcfg);
1884 { /* The RTD driver does this */
1885 unsigned char pci_latency;
1887 /*uint32_t epld_version; */
1889 pci_read_config_word(devpriv->pci_dev, PCI_REVISION_ID,
1891 DPRINTK("%s: PCI revision %d.\n", dev->board_name, revision);
1893 pci_read_config_byte(devpriv->pci_dev,
1894 PCI_LATENCY_TIMER, &pci_latency);
1895 if (pci_latency < 32) {
1896 printk(KERN_INFO "%s: PCI latency changed from %d to %d\n",
1897 dev->board_name, pci_latency, 32);
1898 pci_write_config_byte(devpriv->pci_dev,
1899 PCI_LATENCY_TIMER, 32);
1901 DPRINTK("rtd520: PCI latency = %d\n", pci_latency);
1905 * Undocumented EPLD version (doesn't match RTD driver results)
1907 /*DPRINTK ("rtd520: Reading epld from %p\n",
1909 epld_version = readl (devpriv->las0+0);
1910 if ((epld_version & 0xF0) >> 4 == 0x0F) {
1911 DPRINTK("rtd520: pre-v8 EPLD. (%x)\n", epld_version);
1913 DPRINTK("rtd520: EPLD version %x.\n", epld_version >> 4);
1917 /* Show board configuration */
1918 printk(KERN_INFO "%s:", dev->board_name);
1920 ret = comedi_alloc_subdevices(dev, 4);
1924 s = dev->subdevices + 0;
1925 dev->read_subdev = s;
1926 /* analog input subdevice */
1927 s->type = COMEDI_SUBD_AI;
1929 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
1930 s->n_chan = thisboard->aiChans;
1931 s->maxdata = (1 << thisboard->aiBits) - 1;
1932 if (thisboard->aiMaxGain <= 32)
1933 s->range_table = &rtd_ai_7520_range;
1935 s->range_table = &rtd_ai_4520_range;
1937 s->len_chanlist = RTD_MAX_CHANLIST; /* devpriv->fifoLen */
1938 s->insn_read = rtd_ai_rinsn;
1939 s->do_cmd = rtd_ai_cmd;
1940 s->do_cmdtest = rtd_ai_cmdtest;
1941 s->cancel = rtd_ai_cancel;
1942 /* s->poll = rtd_ai_poll; *//* not ready yet */
1944 s = dev->subdevices + 1;
1945 /* analog output subdevice */
1946 s->type = COMEDI_SUBD_AO;
1947 s->subdev_flags = SDF_WRITABLE;
1949 s->maxdata = (1 << thisboard->aiBits) - 1;
1950 s->range_table = &rtd_ao_range;
1951 s->insn_write = rtd_ao_winsn;
1952 s->insn_read = rtd_ao_rinsn;
1954 s = dev->subdevices + 2;
1955 /* digital i/o subdevice */
1956 s->type = COMEDI_SUBD_DIO;
1957 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1958 /* we only support port 0 right now. Ignoring port 1 and user IO */
1961 s->range_table = &range_digital;
1962 s->insn_bits = rtd_dio_insn_bits;
1963 s->insn_config = rtd_dio_insn_config;
1965 /* timer/counter subdevices (not currently supported) */
1966 s = dev->subdevices + 3;
1967 s->type = COMEDI_SUBD_COUNTER;
1968 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1970 s->maxdata = 0xffff;
1972 /* initialize board, per RTD spec */
1973 /* also, initialize shadow registers */
1974 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
1975 udelay(100); /* needed? */
1976 RtdPlxInterruptWrite(dev, 0);
1977 RtdInterruptMask(dev, 0); /* and sets shadow */
1978 RtdInterruptClearMask(dev, ~0); /* and sets shadow */
1979 RtdInterruptClear(dev); /* clears bits set by mask */
1980 RtdInterruptOverrunClear(dev);
1981 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
1982 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1983 RtdDacClearFifo(dev, 0);
1984 RtdDacClearFifo(dev, 1);
1985 /* clear digital IO fifo */
1986 RtdDioStatusWrite(dev, 0); /* safe state, set shadow */
1987 RtdUtcCtrlPut(dev, 0, 0x30); /* safe state, set shadow */
1988 RtdUtcCtrlPut(dev, 1, 0x30); /* safe state, set shadow */
1989 RtdUtcCtrlPut(dev, 2, 0x30); /* safe state, set shadow */
1990 RtdUtcCtrlPut(dev, 3, 0); /* safe state, set shadow */
1991 /* TODO: set user out source ??? */
1993 /* check if our interrupt is available and get it */
1994 ret = request_irq(devpriv->pci_dev->irq, rtd_interrupt,
1995 IRQF_SHARED, DRV_NAME, dev);
1998 printk("Could not get interrupt! (%u)\n",
1999 devpriv->pci_dev->irq);
2002 dev->irq = devpriv->pci_dev->irq;
2003 printk(KERN_INFO "( irq=%u )", dev->irq);
2005 ret = rtd520_probe_fifo_depth(dev);
2009 devpriv->fifoLen = ret;
2010 printk("( fifoLen=%d )", devpriv->fifoLen);
2014 printk("( DMA buff=%d )\n", DMA_CHAIN_COUNT);
2016 * The PLX9080 has 2 DMA controllers, but there could be
2017 * 4 sources: ADC, digital, DAC1, and DAC2. Since only the
2018 * ADC supports cmd mode right now, this isn't an issue (yet)
2020 devpriv->dma0Offset = 0;
2022 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2023 devpriv->dma0Buff[index] =
2024 pci_alloc_consistent(devpriv->pci_dev,
2026 devpriv->fifoLen / 2,
2028 dma0BuffPhysAddr[index]);
2029 if (devpriv->dma0Buff[index] == NULL) {
2031 goto rtd_attach_die_error;
2033 /*DPRINTK ("buff[%d] @ %p virtual, %x PCI\n",
2035 devpriv->dma0Buff[index],
2036 devpriv->dma0BuffPhysAddr[index]); */
2040 * setup DMA descriptor ring (use cpu_to_le32 for byte
2043 devpriv->dma0Chain =
2044 pci_alloc_consistent(devpriv->pci_dev,
2045 sizeof(struct plx_dma_desc) *
2047 &devpriv->dma0ChainPhysAddr);
2048 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2049 devpriv->dma0Chain[index].pci_start_addr =
2050 devpriv->dma0BuffPhysAddr[index];
2051 devpriv->dma0Chain[index].local_start_addr =
2053 devpriv->dma0Chain[index].transfer_size =
2054 sizeof(u16) * devpriv->fifoLen / 2;
2055 devpriv->dma0Chain[index].next =
2056 (devpriv->dma0ChainPhysAddr + ((index +
2059 * sizeof(devpriv->dma0Chain[0]))
2060 | DMA_TRANSFER_BITS;
2061 /*DPRINTK ("ring[%d] @%lx PCI: %x, local: %x, N: 0x%x, next: %x\n",
2063 ((long)devpriv->dma0ChainPhysAddr
2064 + (index * sizeof(devpriv->dma0Chain[0]))),
2065 devpriv->dma0Chain[index].pci_start_addr,
2066 devpriv->dma0Chain[index].local_start_addr,
2067 devpriv->dma0Chain[index].transfer_size,
2068 devpriv->dma0Chain[index].next); */
2071 if (devpriv->dma0Chain == NULL) {
2073 goto rtd_attach_die_error;
2076 RtdDma0Mode(dev, DMA_MODE_BITS);
2077 /* set DMA trigger source */
2078 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL);
2080 printk(KERN_INFO "( no IRQ->no DMA )");
2082 #endif /* USE_DMA */
2084 if (dev->irq) { /* enable plx9080 interrupts */
2085 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
2088 printk("\ncomedi%d: rtd520 driver attached.\n", dev->minor);
2093 /* hit an error, clean up memory and return ret */
2094 /* rtd_attach_die_error: */
2096 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2097 if (NULL != devpriv->dma0Buff[index]) { /* free buffer memory */
2098 pci_free_consistent(devpriv->pci_dev,
2099 sizeof(u16) * devpriv->fifoLen / 2,
2100 devpriv->dma0Buff[index],
2101 devpriv->dma0BuffPhysAddr[index]);
2102 devpriv->dma0Buff[index] = NULL;
2105 if (NULL != devpriv->dma0Chain) {
2106 pci_free_consistent(devpriv->pci_dev,
2107 sizeof(struct plx_dma_desc)
2110 devpriv->dma0ChainPhysAddr);
2111 devpriv->dma0Chain = NULL;
2113 #endif /* USE_DMA */
2114 /* subdevices and priv are freed by the core */
2116 /* disable interrupt controller */
2117 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
2118 & ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E));
2119 free_irq(dev->irq, dev);
2122 /* release all regions that were allocated */
2124 iounmap(devpriv->las0);
2127 iounmap(devpriv->las1);
2130 iounmap(devpriv->lcfg);
2132 if (devpriv->pci_dev)
2133 pci_dev_put(devpriv->pci_dev);
2139 static void rtd_detach(struct comedi_device *dev)
2146 /* Shut down any board ops by resetting it */
2148 if (devpriv->lcfg) {
2149 RtdDma0Control(dev, 0); /* disable DMA */
2150 RtdDma1Control(dev, 0); /* disable DMA */
2151 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
2153 #endif /* USE_DMA */
2154 if (devpriv->las0) {
2155 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
2156 RtdInterruptMask(dev, 0);
2157 RtdInterruptClearMask(dev, ~0);
2158 RtdInterruptClear(dev); /* clears bits set by mask */
2162 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2163 if (NULL != devpriv->dma0Buff[index]) {
2164 pci_free_consistent(devpriv->pci_dev,
2166 devpriv->fifoLen / 2,
2167 devpriv->dma0Buff[index],
2169 dma0BuffPhysAddr[index]);
2170 devpriv->dma0Buff[index] = NULL;
2173 if (NULL != devpriv->dma0Chain) {
2174 pci_free_consistent(devpriv->pci_dev,
2175 sizeof(struct plx_dma_desc) *
2176 DMA_CHAIN_COUNT, devpriv->dma0Chain,
2177 devpriv->dma0ChainPhysAddr);
2178 devpriv->dma0Chain = NULL;
2180 #endif /* USE_DMA */
2182 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
2183 & ~(ICS_PLIE | ICS_DMA0_E |
2185 free_irq(dev->irq, dev);
2188 iounmap(devpriv->las0);
2190 iounmap(devpriv->las1);
2192 iounmap(devpriv->lcfg);
2193 if (devpriv->pci_dev) {
2194 if (devpriv->got_regions)
2195 comedi_pci_disable(devpriv->pci_dev);
2196 pci_dev_put(devpriv->pci_dev);
2201 static struct comedi_driver rtd520_driver = {
2202 .driver_name = "rtd520",
2203 .module = THIS_MODULE,
2204 .attach = rtd_attach,
2205 .detach = rtd_detach,
2208 static int __devinit rtd520_pci_probe(struct pci_dev *dev,
2209 const struct pci_device_id *ent)
2211 return comedi_pci_auto_config(dev, &rtd520_driver);
2214 static void __devexit rtd520_pci_remove(struct pci_dev *dev)
2216 comedi_pci_auto_unconfig(dev);
2219 static DEFINE_PCI_DEVICE_TABLE(rtd520_pci_table) = {
2220 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x7520) },
2221 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x4520) },
2224 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
2226 static struct pci_driver rtd520_pci_driver = {
2228 .id_table = rtd520_pci_table,
2229 .probe = rtd520_pci_probe,
2230 .remove = __devexit_p(rtd520_pci_remove),
2232 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
2234 MODULE_AUTHOR("Comedi http://www.comedi.org");
2235 MODULE_DESCRIPTION("Comedi low-level driver");
2236 MODULE_LICENSE("GPL");