3 * Comedi driver for Winsystems PC-104 based 48/96-channel DIO boards.
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2006 Calin A. Culianu <calin@ajvar.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: Winsystems PC-104 based 48/96-channel DIO boards.
22 * Devices: [Winsystems] PCM-UIO48A (pcmuio48), PCM-UIO96A (pcmuio96)
23 * Author: Calin Culianu <calin@ajvar.org>
24 * Updated: Fri, 13 Jan 2006 12:01:01 -0500
27 * A driver for the relatively straightforward-to-program PCM-UIO48A and
28 * PCM-UIO96A boards from Winsystems. These boards use either one or two
29 * (in the 96-DIO version) WS16C48 ASIC HighDensity I/O Chips (HDIO). This
30 * chip is interesting in that each I/O line is individually programmable
31 * for INPUT or OUTPUT (thus comedi_dio_config can be done on a per-channel
32 * basis). Also, each chip supports edge-triggered interrupts for the first
33 * 24 I/O lines. Of course, since the 96-channel version of the board has
34 * two ASICs, it can detect polarity changes on up to 48 I/O lines. Since
35 * this is essentially an (non-PnP) ISA board, I/O Address and IRQ selection
36 * are done through jumpers on the board. You need to pass that information
37 * to this driver as the first and second comedi_config option, respectively.
38 * Note that the 48-channel version uses 16 bytes of IO memory and the 96-
39 * channel version uses 32-bytes (in case you are worried about conflicts).
40 * The 48-channel board is split into two 24-channel comedi subdevices. The
41 * 96-channel board is split into 4 24-channel DIO subdevices.
43 * Note that IRQ support has been added, but it is untested.
45 * To use edge-detection IRQ support, pass the IRQs of both ASICS (for the
46 * 96 channel version) or just 1 ASIC (for 48-channel version). Then, use
47 * comedi_commands with TRIG_NOW. Your callback will be called each time an
48 * edge is triggered, and the data values will be two sample_t's, which
49 * should be concatenated to form one 32-bit unsigned int. This value is
50 * the mask of channels that had edges detected from your channel list. Note
51 * that the bits positions in the mask correspond to positions in your
52 * chanlist when you specified the command and *not* channel id's!
54 * To set the polarity of the edge-detection interrupts pass a nonzero value
55 * for either CR_RANGE or CR_AREF for edge-up polarity, or a zero value for
56 * both CR_RANGE and CR_AREF if you want edge-down polarity.
58 * In the 48-channel version:
60 * On subdev 0, the first 24 channels channels are edge-detect channels.
62 * In the 96-channel board you have the following channels that can do edge
65 * subdev 0, channels 0-24 (first 24 channels of 1st ASIC)
66 * subdev 2, channels 0-24 (first 24 channels of 2nd ASIC)
68 * Configuration Options:
69 * [0] - I/O port base address
70 * [1] - IRQ (for first ASIC, or first 24 channels)
71 * [2] - IRQ (for second ASIC, pcmuio96 only - IRQ for chans 48-72
72 * can be the same as first irq!)
75 #include <linux/module.h>
76 #include <linux/interrupt.h>
78 #include "../comedidev.h"
80 #include "comedi_fc.h"
85 * Offset Page 0 Page 1 Page 2 Page 3
86 * ------ ----------- ----------- ----------- -----------
87 * 0x00 Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O
88 * 0x01 Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O
89 * 0x02 Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O
90 * 0x03 Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O
91 * 0x04 Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O
92 * 0x05 Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O
93 * 0x06 INT_PENDING INT_PENDING INT_PENDING INT_PENDING
94 * 0x07 Page/Lock Page/Lock Page/Lock Page/Lock
95 * 0x08 N/A POL_0 ENAB_0 INT_ID0
96 * 0x09 N/A POL_1 ENAB_1 INT_ID1
97 * 0x0a N/A POL_2 ENAB_2 INT_ID2
99 #define PCMUIO_PORT_REG(x) (0x00 + (x))
100 #define PCMUIO_INT_PENDING_REG 0x06
101 #define PCMUIO_PAGE_LOCK_REG 0x07
102 #define PCMUIO_LOCK_PORT(x) ((1 << (x)) & 0x3f)
103 #define PCMUIO_PAGE(x) (((x) & 0x3) << 6)
104 #define PCMUIO_PAGE_MASK PCMUIO_PAGE(3)
105 #define PCMUIO_PAGE_POL 1
106 #define PCMUIO_PAGE_ENAB 2
107 #define PCMUIO_PAGE_INT_ID 3
108 #define PCMUIO_PAGE_REG(x) (0x08 + (x))
110 #define PCMUIO_ASIC_IOSIZE 0x10
111 #define PCMUIO_MAX_ASICS 2
113 struct pcmuio_board {
118 static const struct pcmuio_board pcmuio_boards[] = {
129 spinlock_t pagelock; /* protects the page registers */
130 spinlock_t spinlock; /* protects member variables */
131 unsigned int enabled_mask;
132 unsigned int active:1;
135 struct pcmuio_private {
136 struct pcmuio_asic asics[PCMUIO_MAX_ASICS];
140 static inline unsigned long pcmuio_asic_iobase(struct comedi_device *dev,
143 return dev->iobase + (asic * PCMUIO_ASIC_IOSIZE);
146 static inline int pcmuio_subdevice_to_asic(struct comedi_subdevice *s)
149 * subdevice 0 and 1 are handled by the first asic
150 * subdevice 2 and 3 are handled by the second asic
155 static inline int pcmuio_subdevice_to_port(struct comedi_subdevice *s)
158 * subdevice 0 and 2 use port registers 0-2
159 * subdevice 1 and 3 use port registers 3-5
161 return (s->index % 2) ? 3 : 0;
164 static void pcmuio_write(struct comedi_device *dev, unsigned int val,
165 int asic, int page, int port)
167 struct pcmuio_private *devpriv = dev->private;
168 struct pcmuio_asic *chip = &devpriv->asics[asic];
169 unsigned long iobase = pcmuio_asic_iobase(dev, asic);
172 spin_lock_irqsave(&chip->pagelock, flags);
174 /* Port registers are valid for any page */
175 outb(val & 0xff, iobase + PCMUIO_PORT_REG(port + 0));
176 outb((val >> 8) & 0xff, iobase + PCMUIO_PORT_REG(port + 1));
177 outb((val >> 16) & 0xff, iobase + PCMUIO_PORT_REG(port + 2));
179 outb(PCMUIO_PAGE(page), iobase + PCMUIO_PAGE_LOCK_REG);
180 outb(val & 0xff, iobase + PCMUIO_PAGE_REG(0));
181 outb((val >> 8) & 0xff, iobase + PCMUIO_PAGE_REG(1));
182 outb((val >> 16) & 0xff, iobase + PCMUIO_PAGE_REG(2));
184 spin_unlock_irqrestore(&chip->pagelock, flags);
187 static unsigned int pcmuio_read(struct comedi_device *dev,
188 int asic, int page, int port)
190 struct pcmuio_private *devpriv = dev->private;
191 struct pcmuio_asic *chip = &devpriv->asics[asic];
192 unsigned long iobase = pcmuio_asic_iobase(dev, asic);
196 spin_lock_irqsave(&chip->pagelock, flags);
198 /* Port registers are valid for any page */
199 val = inb(iobase + PCMUIO_PORT_REG(port + 0));
200 val |= (inb(iobase + PCMUIO_PORT_REG(port + 1)) << 8);
201 val |= (inb(iobase + PCMUIO_PORT_REG(port + 2)) << 16);
203 outb(PCMUIO_PAGE(page), iobase + PCMUIO_PAGE_LOCK_REG);
204 val = inb(iobase + PCMUIO_PAGE_REG(0));
205 val |= (inb(iobase + PCMUIO_PAGE_REG(1)) << 8);
206 val |= (inb(iobase + PCMUIO_PAGE_REG(2)) << 16);
208 spin_unlock_irqrestore(&chip->pagelock, flags);
214 * Each channel can be individually programmed for input or output.
215 * Writing a '0' to a channel causes the corresponding output pin
216 * to go to a high-z state (pulled high by an external 10K resistor).
217 * This allows it to be used as an input. When used in the input mode,
218 * a read reflects the inverted state of the I/O pin, such that a
219 * high on the pin will read as a '0' in the register. Writing a '1'
220 * to a bit position causes the pin to sink current (up to 12mA),
221 * effectively pulling it low.
223 static int pcmuio_dio_insn_bits(struct comedi_device *dev,
224 struct comedi_subdevice *s,
225 struct comedi_insn *insn,
228 int asic = pcmuio_subdevice_to_asic(s);
229 int port = pcmuio_subdevice_to_port(s);
230 unsigned int chanmask = (1 << s->n_chan) - 1;
234 mask = comedi_dio_update_state(s, data);
237 * Outputs are inverted, invert the state and
238 * update the channels.
240 * The s->io_bits mask makes sure the input channels
241 * are '0' so that the outputs pins stay in a high
244 val = ~s->state & chanmask;
246 pcmuio_write(dev, val, asic, 0, port);
249 /* get inverted state of the channels from the port */
250 val = pcmuio_read(dev, asic, 0, port);
252 /* return the true state of the channels */
253 data[1] = ~val & chanmask;
258 static int pcmuio_dio_insn_config(struct comedi_device *dev,
259 struct comedi_subdevice *s,
260 struct comedi_insn *insn,
263 int asic = pcmuio_subdevice_to_asic(s);
264 int port = pcmuio_subdevice_to_port(s);
267 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
271 if (data[0] == INSN_CONFIG_DIO_INPUT)
272 pcmuio_write(dev, s->io_bits, asic, 0, port);
277 static void pcmuio_reset(struct comedi_device *dev)
279 const struct pcmuio_board *board = dev->board_ptr;
282 for (asic = 0; asic < board->num_asics; ++asic) {
283 /* first, clear all the DIO port bits */
284 pcmuio_write(dev, 0, asic, 0, 0);
285 pcmuio_write(dev, 0, asic, 0, 3);
287 /* Next, clear all the paged registers for each page */
288 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_POL, 0);
289 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_ENAB, 0);
290 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_INT_ID, 0);
294 /* chip->spinlock is already locked */
295 static void pcmuio_stop_intr(struct comedi_device *dev,
296 struct comedi_subdevice *s)
298 struct pcmuio_private *devpriv = dev->private;
299 int asic = pcmuio_subdevice_to_asic(s);
300 struct pcmuio_asic *chip = &devpriv->asics[asic];
302 chip->enabled_mask = 0;
304 s->async->inttrig = NULL;
306 /* disable all intrs for this subdev.. */
307 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_ENAB, 0);
310 static void pcmuio_handle_intr_subdev(struct comedi_device *dev,
311 struct comedi_subdevice *s,
314 struct pcmuio_private *devpriv = dev->private;
315 int asic = pcmuio_subdevice_to_asic(s);
316 struct pcmuio_asic *chip = &devpriv->asics[asic];
317 struct comedi_cmd *cmd = &s->async->cmd;
318 unsigned int val = 0;
322 spin_lock_irqsave(&chip->spinlock, flags);
327 if (!(triggered & chip->enabled_mask))
330 for (i = 0; i < cmd->chanlist_len; i++) {
331 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
333 if (triggered & (1 << chan))
337 comedi_buf_write_samples(s, &val, 1);
339 if (cmd->stop_src == TRIG_COUNT &&
340 s->async->scans_done >= cmd->stop_arg)
341 s->async->events |= COMEDI_CB_EOA;
344 spin_unlock_irqrestore(&chip->spinlock, flags);
346 comedi_handle_events(dev, s);
349 static int pcmuio_handle_asic_interrupt(struct comedi_device *dev, int asic)
351 /* there are could be two asics so we can't use dev->read_subdev */
352 struct comedi_subdevice *s = &dev->subdevices[asic * 2];
353 unsigned long iobase = pcmuio_asic_iobase(dev, asic);
356 /* are there any interrupts pending */
357 val = inb(iobase + PCMUIO_INT_PENDING_REG) & 0x07;
361 /* get, and clear, the pending interrupts */
362 val = pcmuio_read(dev, asic, PCMUIO_PAGE_INT_ID, 0);
363 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_INT_ID, 0);
365 /* handle the pending interrupts */
366 pcmuio_handle_intr_subdev(dev, s, val);
371 static irqreturn_t pcmuio_interrupt(int irq, void *d)
373 struct comedi_device *dev = d;
374 struct pcmuio_private *devpriv = dev->private;
378 handled += pcmuio_handle_asic_interrupt(dev, 0);
379 if (irq == devpriv->irq2)
380 handled += pcmuio_handle_asic_interrupt(dev, 1);
382 return handled ? IRQ_HANDLED : IRQ_NONE;
385 /* chip->spinlock is already locked */
386 static void pcmuio_start_intr(struct comedi_device *dev,
387 struct comedi_subdevice *s)
389 struct pcmuio_private *devpriv = dev->private;
390 int asic = pcmuio_subdevice_to_asic(s);
391 struct pcmuio_asic *chip = &devpriv->asics[asic];
392 struct comedi_cmd *cmd = &s->async->cmd;
393 unsigned int bits = 0;
394 unsigned int pol_bits = 0;
397 chip->enabled_mask = 0;
400 for (i = 0; i < cmd->chanlist_len; i++) {
401 unsigned int chanspec = cmd->chanlist[i];
402 unsigned int chan = CR_CHAN(chanspec);
403 unsigned int range = CR_RANGE(chanspec);
404 unsigned int aref = CR_AREF(chanspec);
407 pol_bits |= ((aref || range) ? 1 : 0) << chan;
410 bits &= ((1 << s->n_chan) - 1);
411 chip->enabled_mask = bits;
413 /* set pol and enab intrs for this subdev.. */
414 pcmuio_write(dev, pol_bits, asic, PCMUIO_PAGE_POL, 0);
415 pcmuio_write(dev, bits, asic, PCMUIO_PAGE_ENAB, 0);
418 static int pcmuio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
420 struct pcmuio_private *devpriv = dev->private;
421 int asic = pcmuio_subdevice_to_asic(s);
422 struct pcmuio_asic *chip = &devpriv->asics[asic];
425 spin_lock_irqsave(&chip->spinlock, flags);
427 pcmuio_stop_intr(dev, s);
428 spin_unlock_irqrestore(&chip->spinlock, flags);
433 static int pcmuio_inttrig_start_intr(struct comedi_device *dev,
434 struct comedi_subdevice *s,
435 unsigned int trig_num)
437 struct pcmuio_private *devpriv = dev->private;
438 struct comedi_cmd *cmd = &s->async->cmd;
439 int asic = pcmuio_subdevice_to_asic(s);
440 struct pcmuio_asic *chip = &devpriv->asics[asic];
443 if (trig_num != cmd->start_arg)
446 spin_lock_irqsave(&chip->spinlock, flags);
447 s->async->inttrig = NULL;
449 pcmuio_start_intr(dev, s);
451 spin_unlock_irqrestore(&chip->spinlock, flags);
457 * 'do_cmd' function for an 'INTERRUPT' subdevice.
459 static int pcmuio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
461 struct pcmuio_private *devpriv = dev->private;
462 struct comedi_cmd *cmd = &s->async->cmd;
463 int asic = pcmuio_subdevice_to_asic(s);
464 struct pcmuio_asic *chip = &devpriv->asics[asic];
467 spin_lock_irqsave(&chip->spinlock, flags);
470 /* Set up start of acquisition. */
471 if (cmd->start_src == TRIG_INT)
472 s->async->inttrig = pcmuio_inttrig_start_intr;
474 pcmuio_start_intr(dev, s);
476 spin_unlock_irqrestore(&chip->spinlock, flags);
481 static int pcmuio_cmdtest(struct comedi_device *dev,
482 struct comedi_subdevice *s,
483 struct comedi_cmd *cmd)
487 /* Step 1 : check if triggers are trivially valid */
489 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
490 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
491 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
492 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
493 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
498 /* Step 2a : make sure trigger sources are unique */
500 err |= cfc_check_trigger_is_unique(cmd->start_src);
501 err |= cfc_check_trigger_is_unique(cmd->stop_src);
503 /* Step 2b : and mutually compatible */
508 /* Step 3: check if arguments are trivially valid */
510 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
511 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
512 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
513 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
515 if (cmd->stop_src == TRIG_COUNT)
516 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
518 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
523 /* step 4: fix up any arguments */
525 /* if (err) return 4; */
530 static int pcmuio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
532 const struct pcmuio_board *board = dev->board_ptr;
533 struct comedi_subdevice *s;
534 struct pcmuio_private *devpriv;
538 ret = comedi_request_region(dev, it->options[0],
539 board->num_asics * PCMUIO_ASIC_IOSIZE);
543 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
547 for (i = 0; i < PCMUIO_MAX_ASICS; ++i) {
548 struct pcmuio_asic *chip = &devpriv->asics[i];
550 spin_lock_init(&chip->pagelock);
551 spin_lock_init(&chip->spinlock);
556 if (it->options[1]) {
557 /* request the irq for the 1st asic */
558 ret = request_irq(it->options[1], pcmuio_interrupt, 0,
559 dev->board_name, dev);
561 dev->irq = it->options[1];
564 if (board->num_asics == 2) {
565 if (it->options[2] == dev->irq) {
566 /* the same irq (or none) is used by both asics */
567 devpriv->irq2 = it->options[2];
568 } else if (it->options[2]) {
569 /* request the irq for the 2nd asic */
570 ret = request_irq(it->options[2], pcmuio_interrupt, 0,
571 dev->board_name, dev);
573 devpriv->irq2 = it->options[2];
577 ret = comedi_alloc_subdevices(dev, board->num_asics * 2);
581 for (i = 0; i < dev->n_subdevices; ++i) {
582 s = &dev->subdevices[i];
583 s->type = COMEDI_SUBD_DIO;
584 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
587 s->range_table = &range_digital;
588 s->insn_bits = pcmuio_dio_insn_bits;
589 s->insn_config = pcmuio_dio_insn_config;
591 /* subdevices 0 and 2 can suppport interrupts */
592 if ((i == 0 && dev->irq) || (i == 2 && devpriv->irq2)) {
593 /* setup the interrupt subdevice */
594 dev->read_subdev = s;
595 s->subdev_flags |= SDF_CMD_READ | SDF_LSAMPL |
597 s->len_chanlist = s->n_chan;
598 s->cancel = pcmuio_cancel;
599 s->do_cmd = pcmuio_cmd;
600 s->do_cmdtest = pcmuio_cmdtest;
607 static void pcmuio_detach(struct comedi_device *dev)
609 struct pcmuio_private *devpriv = dev->private;
614 /* free the 2nd irq if used, the core will free the 1st one */
615 if (devpriv->irq2 && devpriv->irq2 != dev->irq)
616 free_irq(devpriv->irq2, dev);
618 comedi_legacy_detach(dev);
621 static struct comedi_driver pcmuio_driver = {
622 .driver_name = "pcmuio",
623 .module = THIS_MODULE,
624 .attach = pcmuio_attach,
625 .detach = pcmuio_detach,
626 .board_name = &pcmuio_boards[0].name,
627 .offset = sizeof(struct pcmuio_board),
628 .num_names = ARRAY_SIZE(pcmuio_boards),
630 module_comedi_driver(pcmuio_driver);
632 MODULE_AUTHOR("Comedi http://www.comedi.org");
633 MODULE_DESCRIPTION("Comedi low-level driver");
634 MODULE_LICENSE("GPL");