2 comedi/drivers/ni_tiocmd.c
3 Command support for NI general purpose counters
5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
20 * Description: National Instruments general purpose counters command support
21 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
22 * Herman.Bruyninckx@mech.kuleuven.ac.be,
23 * Wim.Meeussen@mech.kuleuven.ac.be,
24 * Klaas.Gadeyne@mech.kuleuven.ac.be,
25 * Frank Mori Hess <fmhess@users.sourceforge.net>
26 * Updated: Fri, 11 Apr 2008 12:32:35 +0100
29 * This module is not used directly by end-users. Rather, it
30 * is used by other drivers (for example ni_660x and ni_pcimio)
31 * to provide command support for NI's general purpose counters.
32 * It was originally split out of ni_tio.c to stop the 'ni_tio'
33 * module depending on the 'mite' module.
36 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
37 * DAQ 6601/6602 User Manual (NI 322137B-01)
38 * 340934b.pdf DAQ-STC reference manual
43 Support use of both banks X and Y
46 #include <linux/module.h>
47 #include "comedi_fc.h"
48 #include "ni_tio_internal.h"
51 static void ni_tio_configure_dma(struct ni_gpct *counter,
52 bool enable, bool read)
54 struct ni_gpct_device *counter_dev = counter->counter_dev;
55 unsigned cidx = counter->counter_index;
59 mask = GI_READ_ACKS_IRQ | GI_WRITE_ACKS_IRQ;
64 bits |= GI_READ_ACKS_IRQ;
66 bits |= GI_WRITE_ACKS_IRQ;
68 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), mask, bits);
70 switch (counter_dev->variant) {
71 case ni_gpct_variant_e_series:
73 case ni_gpct_variant_m_series:
74 case ni_gpct_variant_660x:
75 mask = GI_DMA_ENABLE | GI_DMA_INT_ENA | GI_DMA_WRITE;
79 bits |= GI_DMA_ENABLE | GI_DMA_INT_ENA;
82 ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), mask, bits);
87 static int ni_tio_input_inttrig(struct comedi_device *dev,
88 struct comedi_subdevice *s,
89 unsigned int trig_num)
91 struct ni_gpct *counter = s->private;
92 struct comedi_cmd *cmd = &s->async->cmd;
96 if (trig_num != cmd->start_src)
99 spin_lock_irqsave(&counter->lock, flags);
100 if (counter->mite_chan)
101 mite_dma_arm(counter->mite_chan);
104 spin_unlock_irqrestore(&counter->lock, flags);
107 ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
108 s->async->inttrig = NULL;
113 static int ni_tio_input_cmd(struct comedi_subdevice *s)
115 struct ni_gpct *counter = s->private;
116 struct ni_gpct_device *counter_dev = counter->counter_dev;
117 unsigned cidx = counter->counter_index;
118 struct comedi_async *async = s->async;
119 struct comedi_cmd *cmd = &async->cmd;
122 /* write alloc the entire buffer */
123 comedi_buf_write_alloc(s, async->prealloc_bufsz);
124 counter->mite_chan->dir = COMEDI_INPUT;
125 switch (counter_dev->variant) {
126 case ni_gpct_variant_m_series:
127 case ni_gpct_variant_660x:
128 mite_prep_dma(counter->mite_chan, 32, 32);
130 case ni_gpct_variant_e_series:
131 mite_prep_dma(counter->mite_chan, 16, 32);
137 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
138 ni_tio_configure_dma(counter, true, true);
140 if (cmd->start_src == TRIG_INT) {
141 async->inttrig = &ni_tio_input_inttrig;
142 } else { /* TRIG_NOW || TRIG_EXT || TRIG_OTHER */
143 async->inttrig = NULL;
144 mite_dma_arm(counter->mite_chan);
146 if (cmd->start_src == TRIG_NOW)
147 ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
148 else if (cmd->start_src == TRIG_EXT)
149 ret = ni_tio_arm(counter, 1, cmd->start_arg);
154 static int ni_tio_output_cmd(struct comedi_subdevice *s)
156 struct ni_gpct *counter = s->private;
158 dev_err(counter->counter_dev->dev->class_dev,
159 "output commands not yet implemented.\n");
162 counter->mite_chan->dir = COMEDI_OUTPUT;
163 mite_prep_dma(counter->mite_chan, 32, 32);
164 ni_tio_configure_dma(counter, true, false);
165 mite_dma_arm(counter->mite_chan);
166 return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
169 static int ni_tio_cmd_setup(struct comedi_subdevice *s)
171 struct comedi_cmd *cmd = &s->async->cmd;
172 struct ni_gpct *counter = s->private;
173 unsigned cidx = counter->counter_index;
174 int set_gate_source = 0;
175 unsigned gate_source;
178 if (cmd->scan_begin_src == TRIG_EXT) {
180 gate_source = cmd->scan_begin_arg;
181 } else if (cmd->convert_src == TRIG_EXT) {
183 gate_source = cmd->convert_arg;
186 retval = ni_tio_set_gate_src(counter, 0, gate_source);
187 if (cmd->flags & CMDF_WAKE_EOS) {
188 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
189 GI_GATE_INTERRUPT_ENABLE(cidx),
190 GI_GATE_INTERRUPT_ENABLE(cidx));
195 int ni_tio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
197 struct ni_gpct *counter = s->private;
198 struct comedi_async *async = s->async;
199 struct comedi_cmd *cmd = &async->cmd;
203 spin_lock_irqsave(&counter->lock, flags);
204 if (counter->mite_chan == NULL) {
205 dev_err(counter->counter_dev->dev->class_dev,
206 "commands only supported with DMA. ");
207 dev_err(counter->counter_dev->dev->class_dev,
208 "Interrupt-driven commands not yet implemented.\n");
211 retval = ni_tio_cmd_setup(s);
213 if (cmd->flags & CMDF_WRITE)
214 retval = ni_tio_output_cmd(s);
216 retval = ni_tio_input_cmd(s);
219 spin_unlock_irqrestore(&counter->lock, flags);
222 EXPORT_SYMBOL_GPL(ni_tio_cmd);
224 int ni_tio_cmdtest(struct comedi_device *dev,
225 struct comedi_subdevice *s,
226 struct comedi_cmd *cmd)
228 struct ni_gpct *counter = s->private;
230 unsigned int sources;
232 /* Step 1 : check if triggers are trivially valid */
234 sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
235 if (ni_tio_counting_mode_registers_present(counter->counter_dev))
237 err |= cfc_check_trigger_src(&cmd->start_src, sources);
239 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
240 TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER);
241 err |= cfc_check_trigger_src(&cmd->convert_src,
242 TRIG_NOW | TRIG_EXT | TRIG_OTHER);
243 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
244 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
249 /* Step 2a : make sure trigger sources are unique */
251 err |= cfc_check_trigger_is_unique(cmd->start_src);
252 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
253 err |= cfc_check_trigger_is_unique(cmd->convert_src);
255 /* Step 2b : and mutually compatible */
257 if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
263 /* Step 3: check if arguments are trivially valid */
265 switch (cmd->start_src) {
269 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
272 /* start_arg is the start_trigger passed to ni_tio_arm() */
276 if (cmd->scan_begin_src != TRIG_EXT)
277 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
279 if (cmd->convert_src != TRIG_EXT)
280 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
282 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
283 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
288 /* Step 4: fix up any arguments */
290 /* Step 5: check channel list if it exists */
294 EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
296 int ni_tio_cancel(struct ni_gpct *counter)
298 unsigned cidx = counter->counter_index;
301 ni_tio_arm(counter, 0, 0);
302 spin_lock_irqsave(&counter->lock, flags);
303 if (counter->mite_chan)
304 mite_dma_disarm(counter->mite_chan);
305 spin_unlock_irqrestore(&counter->lock, flags);
306 ni_tio_configure_dma(counter, false, false);
308 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
309 GI_GATE_INTERRUPT_ENABLE(cidx), 0x0);
312 EXPORT_SYMBOL_GPL(ni_tio_cancel);
314 /* During buffered input counter operation for e-series, the gate
315 interrupt is acked automatically by the dma controller, due to the
316 Gi_Read/Write_Acknowledges_IRQ bits in the input select register. */
317 static int should_ack_gate(struct ni_gpct *counter)
322 switch (counter->counter_dev->variant) {
323 case ni_gpct_variant_m_series:
324 /* not sure if 660x really supports gate
325 interrupts (the bits are not listed
326 in register-level manual) */
327 case ni_gpct_variant_660x:
329 case ni_gpct_variant_e_series:
330 spin_lock_irqsave(&counter->lock, flags);
332 if (counter->mite_chan == NULL ||
333 counter->mite_chan->dir != COMEDI_INPUT ||
334 (mite_done(counter->mite_chan))) {
338 spin_unlock_irqrestore(&counter->lock, flags);
344 static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter,
347 int *perm_stale_data,
350 unsigned cidx = counter->counter_index;
351 const unsigned short gxx_status = read_register(counter,
352 NITIO_SHARED_STATUS_REG(cidx));
353 const unsigned short gi_status = read_register(counter,
354 NITIO_STATUS_REG(cidx));
362 *perm_stale_data = 0;
366 if (gxx_status & GI_GATE_ERROR(cidx)) {
367 ack |= GI_GATE_ERROR_CONFIRM(cidx);
369 /*660x don't support automatic acknowledgement
370 of gate interrupt via dma read/write
371 and report bogus gate errors */
372 if (counter->counter_dev->variant !=
373 ni_gpct_variant_660x)
377 if (gxx_status & GI_TC_ERROR(cidx)) {
378 ack |= GI_TC_ERROR_CONFIRM(cidx);
382 if (gi_status & GI_TC)
383 ack |= GI_TC_INTERRUPT_ACK;
384 if (gi_status & GI_GATE_INTERRUPT) {
385 if (should_ack_gate(counter))
386 ack |= GI_GATE_INTERRUPT_ACK;
389 write_register(counter, ack, NITIO_INT_ACK_REG(cidx));
390 if (ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)) &
391 GI_LOADING_ON_GATE) {
392 if (gxx_status & GI_STALE_DATA(cidx)) {
396 if (read_register(counter, NITIO_STATUS2_REG(cidx)) &
397 GI_PERMANENT_STALE(cidx)) {
398 dev_info(counter->counter_dev->dev->class_dev,
399 "%s: Gi_Permanent_Stale_Data detected.\n",
402 *perm_stale_data = 1;
407 void ni_tio_acknowledge(struct ni_gpct *counter)
409 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
411 EXPORT_SYMBOL_GPL(ni_tio_acknowledge);
413 void ni_tio_handle_interrupt(struct ni_gpct *counter,
414 struct comedi_subdevice *s)
416 unsigned cidx = counter->counter_index;
417 unsigned gpct_mite_status;
423 ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
424 &perm_stale_data, NULL);
426 dev_notice(counter->counter_dev->dev->class_dev,
427 "%s: Gi_Gate_Error detected.\n", __func__);
428 s->async->events |= COMEDI_CB_OVERFLOW;
431 s->async->events |= COMEDI_CB_ERROR;
432 switch (counter->counter_dev->variant) {
433 case ni_gpct_variant_m_series:
434 case ni_gpct_variant_660x:
435 if (read_register(counter, NITIO_DMA_STATUS_REG(cidx)) &
437 dev_notice(counter->counter_dev->dev->class_dev,
438 "%s: Gi_DRQ_Error detected.\n", __func__);
439 s->async->events |= COMEDI_CB_OVERFLOW;
442 case ni_gpct_variant_e_series:
445 spin_lock_irqsave(&counter->lock, flags);
446 if (counter->mite_chan == NULL) {
447 spin_unlock_irqrestore(&counter->lock, flags);
450 gpct_mite_status = mite_get_status(counter->mite_chan);
451 if (gpct_mite_status & CHSR_LINKC)
453 counter->mite_chan->mite->mite_io_addr +
454 MITE_CHOR(counter->mite_chan->channel));
455 mite_sync_input_dma(counter->mite_chan, s);
456 spin_unlock_irqrestore(&counter->lock, flags);
458 EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
460 void ni_tio_set_mite_channel(struct ni_gpct *counter,
461 struct mite_channel *mite_chan)
465 spin_lock_irqsave(&counter->lock, flags);
466 counter->mite_chan = mite_chan;
467 spin_unlock_irqrestore(&counter->lock, flags);
469 EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
471 static int __init ni_tiocmd_init_module(void)
475 module_init(ni_tiocmd_init_module);
477 static void __exit ni_tiocmd_cleanup_module(void)
480 module_exit(ni_tiocmd_cleanup_module);
482 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
483 MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
484 MODULE_LICENSE("GPL");