drivers/staging/comedi/drivers/ni_tio.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Support for NI general purpose counters
   4  *
   5  * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   6  */
   7
   8 /*
   9  * Module: ni_tio
  10  * Description: National Instruments general purpose counters
  11  * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  12  *         Herman.Bruyninckx@mech.kuleuven.ac.be,
  13  *         Wim.Meeussen@mech.kuleuven.ac.be,
  14  *         Klaas.Gadeyne@mech.kuleuven.ac.be,
  15  *         Frank Mori Hess <fmhess@users.sourceforge.net>
  16  * Updated: Thu Nov 16 09:50:32 EST 2006
  17  * Status: works
  18  *
  19  * This module is not used directly by end-users.  Rather, it
  20  * is used by other drivers (for example ni_660x and ni_pcimio)
  21  * to provide support for NI's general purpose counters.  It was
  22  * originally based on the counter code from ni_660x.c and
  23  * ni_mio_common.c.
  24  *
  25  * References:
  26  * DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  27  * DAQ 6601/6602 User Manual (NI 322137B-01)
  28  * 340934b.pdf  DAQ-STC reference manual
  29  *
  30  * TODO: Support use of both banks X and Y
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/slab.h>
  35
  36 #include "ni_tio_internal.h"
  37
  38 /*
  39  * clock sources for ni e and m series boards,
  40  * get bits with GI_SRC_SEL()
  41  */
  42 #define NI_M_TIMEBASE_1_CLK             0x0     /* 20MHz */
  43 #define NI_M_PFI_CLK(x)                 (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  44 #define NI_M_RTSI_CLK(x)                (((x) == 7) ? 0x1b : (0xb + (x)))
  45 #define NI_M_TIMEBASE_2_CLK             0x12    /* 100KHz */
  46 #define NI_M_NEXT_TC_CLK                0x13
  47 #define NI_M_NEXT_GATE_CLK              0x14    /* Gi_Src_SubSelect=0 */
  48 #define NI_M_PXI_STAR_TRIGGER_CLK       0x14    /* Gi_Src_SubSelect=1 */
  49 #define NI_M_PXI10_CLK                  0x1d
  50 #define NI_M_TIMEBASE_3_CLK             0x1e    /* 80MHz, Gi_Src_SubSelect=0 */
  51 #define NI_M_ANALOG_TRIGGER_OUT_CLK     0x1e    /* Gi_Src_SubSelect=1 */
  52 #define NI_M_LOGIC_LOW_CLK              0x1f
  53 #define NI_M_MAX_PFI_CHAN               15
  54 #define NI_M_MAX_RTSI_CHAN              7
  55
  56 /*
  57  * clock sources for ni_660x boards,
  58  * get bits with GI_SRC_SEL()
  59  */
  60 #define NI_660X_TIMEBASE_1_CLK          0x0     /* 20MHz */
  61 #define NI_660X_SRC_PIN_I_CLK           0x1
  62 #define NI_660X_SRC_PIN_CLK(x)          (0x2 + (x))
  63 #define NI_660X_NEXT_GATE_CLK           0xa
  64 #define NI_660X_RTSI_CLK(x)             (0xb + (x))
  65 #define NI_660X_TIMEBASE_2_CLK          0x12    /* 100KHz */
  66 #define NI_660X_NEXT_TC_CLK             0x13
  67 #define NI_660X_TIMEBASE_3_CLK          0x1e    /* 80MHz */
  68 #define NI_660X_LOGIC_LOW_CLK           0x1f
  69 #define NI_660X_MAX_SRC_PIN             7
  70 #define NI_660X_MAX_RTSI_CHAN           6
  71
  72 /* ni m series gate_select */
  73 #define NI_M_TIMESTAMP_MUX_GATE_SEL     0x0
  74 #define NI_M_PFI_GATE_SEL(x)            (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  75 #define NI_M_RTSI_GATE_SEL(x)           (((x) == 7) ? 0x1b : (0xb + (x)))
  76 #define NI_M_AI_START2_GATE_SEL         0x12
  77 #define NI_M_PXI_STAR_TRIGGER_GATE_SEL  0x13
  78 #define NI_M_NEXT_OUT_GATE_SEL          0x14
  79 #define NI_M_AI_START1_GATE_SEL         0x1c
  80 #define NI_M_NEXT_SRC_GATE_SEL          0x1d
  81 #define NI_M_ANALOG_TRIG_OUT_GATE_SEL   0x1e
  82 #define NI_M_LOGIC_LOW_GATE_SEL         0x1f
  83
  84 /* ni_660x gate select */
  85 #define NI_660X_SRC_PIN_I_GATE_SEL      0x0
  86 #define NI_660X_GATE_PIN_I_GATE_SEL     0x1
  87 #define NI_660X_PIN_GATE_SEL(x)         (0x2 + (x))
  88 #define NI_660X_NEXT_SRC_GATE_SEL       0xa
  89 #define NI_660X_RTSI_GATE_SEL(x)        (0xb + (x))
  90 #define NI_660X_NEXT_OUT_GATE_SEL       0x14
  91 #define NI_660X_LOGIC_LOW_GATE_SEL      0x1f
  92 #define NI_660X_MAX_GATE_PIN            7
  93
  94 /* ni_660x second gate select */
  95 #define NI_660X_SRC_PIN_I_GATE2_SEL     0x0
  96 #define NI_660X_UD_PIN_I_GATE2_SEL      0x1
  97 #define NI_660X_UD_PIN_GATE2_SEL(x)     (0x2 + (x))
  98 #define NI_660X_NEXT_SRC_GATE2_SEL      0xa
  99 #define NI_660X_RTSI_GATE2_SEL(x)       (0xb + (x))
 100 #define NI_660X_NEXT_OUT_GATE2_SEL      0x14
 101 #define NI_660X_SELECTED_GATE2_SEL      0x1e
 102 #define NI_660X_LOGIC_LOW_GATE2_SEL     0x1f
 103 #define NI_660X_MAX_UP_DOWN_PIN         7
 104
 105 static inline unsigned int GI_PRESCALE_X2(enum ni_gpct_variant variant)
 106 {
 107         switch (variant) {
 108         case ni_gpct_variant_e_series:
 109         default:
 110                 return 0;
 111         case ni_gpct_variant_m_series:
 112                 return GI_M_PRESCALE_X2;
 113         case ni_gpct_variant_660x:
 114                 return GI_660X_PRESCALE_X2;
 115         }
 116 }
 117
 118 static inline unsigned int GI_PRESCALE_X8(enum ni_gpct_variant variant)
 119 {
 120         switch (variant) {
 121         case ni_gpct_variant_e_series:
 122         default:
 123                 return 0;
 124         case ni_gpct_variant_m_series:
 125                 return GI_M_PRESCALE_X8;
 126         case ni_gpct_variant_660x:
 127                 return GI_660X_PRESCALE_X8;
 128         }
 129 }
 130
 131 static bool ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev)
 132 {
 133         switch (counter_dev->variant) {
 134         case ni_gpct_variant_e_series:
 135         default:
 136                 return false;
 137         case ni_gpct_variant_m_series:
 138         case ni_gpct_variant_660x:
 139                 return true;
 140         }
 141 }
 142
 143 /**
 144  * ni_tio_write() - Write a TIO register using the driver provided callback.
 145  * @counter: struct ni_gpct counter.
 146  * @value: the value to write
 147  * @reg: the register to write.
 148  */
 149 void ni_tio_write(struct ni_gpct *counter, unsigned int value,
 150                   enum ni_gpct_register reg)
 151 {
 152         if (reg < NITIO_NUM_REGS)
 153                 counter->counter_dev->write(counter, value, reg);
 154 }
 155 EXPORT_SYMBOL_GPL(ni_tio_write);
 156
 157 /**
 158  * ni_tio_read() - Read a TIO register using the driver provided callback.
 159  * @counter: struct ni_gpct counter.
 160  * @reg: the register to read.
 161  */
 162 unsigned int ni_tio_read(struct ni_gpct *counter, enum ni_gpct_register reg)
 163 {
 164         if (reg < NITIO_NUM_REGS)
 165                 return counter->counter_dev->read(counter, reg);
 166         return 0;
 167 }
 168 EXPORT_SYMBOL_GPL(ni_tio_read);
 169
 170 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
 171 {
 172         unsigned int cidx = counter->counter_index;
 173
 174         ni_tio_write(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx));
 175 }
 176
 177 static int ni_tio_clock_period_ps(const struct ni_gpct *counter,
 178                                   unsigned int generic_clock_source,
 179                                   u64 *period_ps)
 180 {
 181         u64 clock_period_ps;
 182
 183         switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 184         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 185                 clock_period_ps = 50000;
 186                 break;
 187         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 188                 clock_period_ps = 10000000;
 189                 break;
 190         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 191                 clock_period_ps = 12500;
 192                 break;
 193         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 194                 clock_period_ps = 100000;
 195                 break;
 196         default:
 197                 /*
 198                  * clock period is specified by user with prescaling
 199                  * already taken into account.
 200                  */
 201                 *period_ps = counter->clock_period_ps;
 202                 return 0;
 203         }
 204
 205         switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 206         case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 207                 break;
 208         case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 209                 clock_period_ps *= 2;
 210                 break;
 211         case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 212                 clock_period_ps *= 8;
 213                 break;
 214         default:
 215                 return -EINVAL;
 216         }
 217         *period_ps = clock_period_ps;
 218         return 0;
 219 }
 220
 221 static void ni_tio_set_bits_transient(struct ni_gpct *counter,
 222                                       enum ni_gpct_register reg,
 223                                       unsigned int mask, unsigned int value,
 224                                       unsigned int transient)
 225 {
 226         struct ni_gpct_device *counter_dev = counter->counter_dev;
 227         unsigned long flags;
 228
 229         if (reg < NITIO_NUM_REGS) {
 230                 spin_lock_irqsave(&counter_dev->regs_lock, flags);
 231                 counter_dev->regs[reg] &= ~mask;
 232                 counter_dev->regs[reg] |= (value & mask);
 233                 ni_tio_write(counter, counter_dev->regs[reg] | transient, reg);
 234                 mmiowb();
 235                 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 236         }
 237 }
 238
 239 /**
 240  * ni_tio_set_bits() - Safely write a counter register.
 241  * @counter: struct ni_gpct counter.
 242  * @reg: the register to write.
 243  * @mask: the bits to change.
 244  * @value: the new bits value.
 245  *
 246  * Used to write to, and update the software copy, a register whose bits may
 247  * be twiddled in interrupt context, or whose software copy may be read in
 248  * interrupt context.
 249  */
 250 void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg,
 251                      unsigned int mask, unsigned int value)
 252 {
 253         ni_tio_set_bits_transient(counter, reg, mask, value, 0x0);
 254 }
 255 EXPORT_SYMBOL_GPL(ni_tio_set_bits);
 256
 257 /**
 258  * ni_tio_get_soft_copy() - Safely read the software copy of a counter register.
 259  * @counter: struct ni_gpct counter.
 260  * @reg: the register to read.
 261  *
 262  * Used to get the software copy of a register whose bits might be modified
 263  * in interrupt context, or whose software copy might need to be read in
 264  * interrupt context.
 265  */
 266 unsigned int ni_tio_get_soft_copy(const struct ni_gpct *counter,
 267                                   enum ni_gpct_register reg)
 268 {
 269         struct ni_gpct_device *counter_dev = counter->counter_dev;
 270         unsigned int value = 0;
 271         unsigned long flags;
 272
 273         if (reg < NITIO_NUM_REGS) {
 274                 spin_lock_irqsave(&counter_dev->regs_lock, flags);
 275                 value = counter_dev->regs[reg];
 276                 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 277         }
 278         return value;
 279 }
 280 EXPORT_SYMBOL_GPL(ni_tio_get_soft_copy);
 281
 282 static unsigned int ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
 283 {
 284         struct ni_gpct_device *counter_dev = counter->counter_dev;
 285         unsigned int cidx = counter->counter_index;
 286         unsigned int counting_mode_bits =
 287                 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
 288         unsigned int bits = 0;
 289
 290         if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 291             GI_SRC_POL_INVERT)
 292                 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
 293         if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
 294                 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
 295         if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
 296                 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
 297         return bits;
 298 }
 299
 300 static int ni_m_series_clock_src_select(const struct ni_gpct *counter,
 301                                         unsigned int *clk_src)
 302 {
 303         struct ni_gpct_device *counter_dev = counter->counter_dev;
 304         unsigned int cidx = counter->counter_index;
 305         unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
 306         unsigned int clock_source = 0;
 307         unsigned int src;
 308         unsigned int i;
 309
 310         src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
 311                                                   NITIO_INPUT_SEL_REG(cidx)));
 312
 313         switch (src) {
 314         case NI_M_TIMEBASE_1_CLK:
 315                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 316                 break;
 317         case NI_M_TIMEBASE_2_CLK:
 318                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 319                 break;
 320         case NI_M_TIMEBASE_3_CLK:
 321                 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
 322                         clock_source =
 323                             NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
 324                 else
 325                         clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 326                 break;
 327         case NI_M_LOGIC_LOW_CLK:
 328                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 329                 break;
 330         case NI_M_NEXT_GATE_CLK:
 331                 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
 332                         clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
 333                 else
 334                         clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 335                 break;
 336         case NI_M_PXI10_CLK:
 337                 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
 338                 break;
 339         case NI_M_NEXT_TC_CLK:
 340                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 341                 break;
 342         default:
 343                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 344                         if (src == NI_M_RTSI_CLK(i)) {
 345                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 346                                 break;
 347                         }
 348                 }
 349                 if (i <= NI_M_MAX_RTSI_CHAN)
 350                         break;
 351                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 352                         if (src == NI_M_PFI_CLK(i)) {
 353                                 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
 354                                 break;
 355                         }
 356                 }
 357                 if (i <= NI_M_MAX_PFI_CHAN)
 358                         break;
 359                 return -EINVAL;
 360         }
 361         clock_source |= ni_tio_clock_src_modifiers(counter);
 362         *clk_src = clock_source;
 363         return 0;
 364 }
 365
 366 static int ni_660x_clock_src_select(const struct ni_gpct *counter,
 367                                     unsigned int *clk_src)
 368 {
 369         unsigned int clock_source = 0;
 370         unsigned int cidx = counter->counter_index;
 371         unsigned int src;
 372         unsigned int i;
 373
 374         src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
 375                                                   NITIO_INPUT_SEL_REG(cidx)));
 376
 377         switch (src) {
 378         case NI_660X_TIMEBASE_1_CLK:
 379                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 380                 break;
 381         case NI_660X_TIMEBASE_2_CLK:
 382                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 383                 break;
 384         case NI_660X_TIMEBASE_3_CLK:
 385                 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 386                 break;
 387         case NI_660X_LOGIC_LOW_CLK:
 388                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 389                 break;
 390         case NI_660X_SRC_PIN_I_CLK:
 391                 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
 392                 break;
 393         case NI_660X_NEXT_GATE_CLK:
 394                 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 395                 break;
 396         case NI_660X_NEXT_TC_CLK:
 397                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 398                 break;
 399         default:
 400                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 401                         if (src == NI_660X_RTSI_CLK(i)) {
 402                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 403                                 break;
 404                         }
 405                 }
 406                 if (i <= NI_660X_MAX_RTSI_CHAN)
 407                         break;
 408                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 409                         if (src == NI_660X_SRC_PIN_CLK(i)) {
 410                                 clock_source =
 411                                     NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
 412                                 break;
 413                         }
 414                 }
 415                 if (i <= NI_660X_MAX_SRC_PIN)
 416                         break;
 417                 return -EINVAL;
 418         }
 419         clock_source |= ni_tio_clock_src_modifiers(counter);
 420         *clk_src = clock_source;
 421         return 0;
 422 }
 423
 424 static int ni_tio_generic_clock_src_select(const struct ni_gpct *counter,
 425                                            unsigned int *clk_src)
 426 {
 427         switch (counter->counter_dev->variant) {
 428         case ni_gpct_variant_e_series:
 429         case ni_gpct_variant_m_series:
 430         default:
 431                 return ni_m_series_clock_src_select(counter, clk_src);
 432         case ni_gpct_variant_660x:
 433                 return ni_660x_clock_src_select(counter, clk_src);
 434         }
 435 }
 436
 437 static void ni_tio_set_sync_mode(struct ni_gpct *counter)
 438 {
 439         struct ni_gpct_device *counter_dev = counter->counter_dev;
 440         unsigned int cidx = counter->counter_index;
 441         static const u64 min_normal_sync_period_ps = 25000;
 442         unsigned int mask = 0;
 443         unsigned int bits = 0;
 444         unsigned int reg;
 445         unsigned int mode;
 446         unsigned int clk_src = 0;
 447         u64 ps = 0;
 448         int ret;
 449         bool force_alt_sync;
 450
 451         /* only m series and 660x variants have counting mode registers */
 452         switch (counter_dev->variant) {
 453         case ni_gpct_variant_e_series:
 454         default:
 455                 return;
 456         case ni_gpct_variant_m_series:
 457                 mask = GI_M_ALT_SYNC;
 458                 break;
 459         case ni_gpct_variant_660x:
 460                 mask = GI_660X_ALT_SYNC;
 461                 break;
 462         }
 463
 464         reg = NITIO_CNT_MODE_REG(cidx);
 465         mode = ni_tio_get_soft_copy(counter, reg);
 466         switch (mode & GI_CNT_MODE_MASK) {
 467         case GI_CNT_MODE_QUADX1:
 468         case GI_CNT_MODE_QUADX2:
 469         case GI_CNT_MODE_QUADX4:
 470         case GI_CNT_MODE_SYNC_SRC:
 471                 force_alt_sync = true;
 472                 break;
 473         default:
 474                 force_alt_sync = false;
 475                 break;
 476         }
 477
 478         ret = ni_tio_generic_clock_src_select(counter, &clk_src);
 479         if (ret)
 480                 return;
 481         ret = ni_tio_clock_period_ps(counter, clk_src, &ps);
 482         if (ret)
 483                 return;
 484         /*
 485          * It's not clear what we should do if clock_period is unknown, so we
 486          * are not using the alt sync bit in that case.
 487          */
 488         if (force_alt_sync || (ps && ps < min_normal_sync_period_ps))
 489                 bits = mask;
 490
 491         ni_tio_set_bits(counter, reg, mask, bits);
 492 }
 493
 494 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned int mode)
 495 {
 496         struct ni_gpct_device *counter_dev = counter->counter_dev;
 497         unsigned int cidx = counter->counter_index;
 498         unsigned int mode_reg_mask;
 499         unsigned int mode_reg_values;
 500         unsigned int input_select_bits = 0;
 501         /* these bits map directly on to the mode register */
 502         static const unsigned int mode_reg_direct_mask =
 503             NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
 504             NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
 505             NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
 506             NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
 507
 508         mode_reg_mask = mode_reg_direct_mask | GI_RELOAD_SRC_SWITCHING;
 509         mode_reg_values = mode & mode_reg_direct_mask;
 510         switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
 511         case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
 512                 break;
 513         case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
 514                 mode_reg_values |= GI_RELOAD_SRC_SWITCHING;
 515                 break;
 516         case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
 517                 input_select_bits |= GI_GATE_SEL_LOAD_SRC;
 518                 mode_reg_mask |= GI_GATING_MODE_MASK;
 519                 mode_reg_values |= GI_LEVEL_GATING;
 520                 break;
 521         default:
 522                 break;
 523         }
 524         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 525                         mode_reg_mask, mode_reg_values);
 526
 527         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 528                 unsigned int bits = 0;
 529
 530                 bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
 531                 bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
 532                 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
 533                         bits |= GI_INDEX_MODE;
 534                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 535                                 GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
 536                                 GI_INDEX_MODE, bits);
 537                 ni_tio_set_sync_mode(counter);
 538         }
 539
 540         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK,
 541                         GI_CNT_DIR(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT));
 542
 543         if (mode & NI_GPCT_OR_GATE_BIT)
 544                 input_select_bits |= GI_OR_GATE;
 545         if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
 546                 input_select_bits |= GI_OUTPUT_POL_INVERT;
 547         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 548                         GI_GATE_SEL_LOAD_SRC | GI_OR_GATE |
 549                         GI_OUTPUT_POL_INVERT, input_select_bits);
 550
 551         return 0;
 552 }
 553
 554 int ni_tio_arm(struct ni_gpct *counter, bool arm, unsigned int start_trigger)
 555 {
 556         struct ni_gpct_device *counter_dev = counter->counter_dev;
 557         unsigned int cidx = counter->counter_index;
 558         unsigned int transient_bits = 0;
 559
 560         if (arm) {
 561                 unsigned int mask = 0;
 562                 unsigned int bits = 0;
 563
 564                 /* only m series and 660x have counting mode registers */
 565                 switch (counter_dev->variant) {
 566                 case ni_gpct_variant_e_series:
 567                 default:
 568                         break;
 569                 case ni_gpct_variant_m_series:
 570                         mask = GI_M_HW_ARM_SEL_MASK;
 571                         break;
 572                 case ni_gpct_variant_660x:
 573                         mask = GI_660X_HW_ARM_SEL_MASK;
 574                         break;
 575                 }
 576
 577                 switch (start_trigger) {
 578                 case NI_GPCT_ARM_IMMEDIATE:
 579                         transient_bits |= GI_ARM;
 580                         break;
 581                 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 582                         transient_bits |= GI_ARM | GI_ARM_COPY;
 583                         break;
 584                 default:
 585                         /*
 586                          * for m series and 660x, pass-through the least
 587                          * significant bits so we can figure out what select
 588                          * later
 589                          */
 590                         if (mask && (start_trigger & NI_GPCT_ARM_UNKNOWN)) {
 591                                 bits |= GI_HW_ARM_ENA |
 592                                         (GI_HW_ARM_SEL(start_trigger) & mask);
 593                         } else {
 594                                 return -EINVAL;
 595                         }
 596                         break;
 597                 }
 598
 599                 if (mask)
 600                         ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 601                                         GI_HW_ARM_ENA | mask, bits);
 602         } else {
 603                 transient_bits |= GI_DISARM;
 604         }
 605         ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
 606                                   0, 0, transient_bits);
 607         return 0;
 608 }
 609 EXPORT_SYMBOL_GPL(ni_tio_arm);
 610
 611 static int ni_660x_clk_src(unsigned int clock_source, unsigned int *bits)
 612 {
 613         unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 614         unsigned int ni_660x_clock;
 615         unsigned int i;
 616
 617         switch (clk_src) {
 618         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 619                 ni_660x_clock = NI_660X_TIMEBASE_1_CLK;
 620                 break;
 621         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 622                 ni_660x_clock = NI_660X_TIMEBASE_2_CLK;
 623                 break;
 624         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 625                 ni_660x_clock = NI_660X_TIMEBASE_3_CLK;
 626                 break;
 627         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 628                 ni_660x_clock = NI_660X_LOGIC_LOW_CLK;
 629                 break;
 630         case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
 631                 ni_660x_clock = NI_660X_SRC_PIN_I_CLK;
 632                 break;
 633         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 634                 ni_660x_clock = NI_660X_NEXT_GATE_CLK;
 635                 break;
 636         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 637                 ni_660x_clock = NI_660X_NEXT_TC_CLK;
 638                 break;
 639         default:
 640                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 641                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 642                                 ni_660x_clock = NI_660X_RTSI_CLK(i);
 643                                 break;
 644                         }
 645                 }
 646                 if (i <= NI_660X_MAX_RTSI_CHAN)
 647                         break;
 648                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 649                         if (clk_src == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
 650                                 ni_660x_clock = NI_660X_SRC_PIN_CLK(i);
 651                                 break;
 652                         }
 653                 }
 654                 if (i <= NI_660X_MAX_SRC_PIN)
 655                         break;
 656                 return -EINVAL;
 657         }
 658         *bits = GI_SRC_SEL(ni_660x_clock);
 659         return 0;
 660 }
 661
 662 static int ni_m_clk_src(unsigned int clock_source, unsigned int *bits)
 663 {
 664         unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 665         unsigned int ni_m_series_clock;
 666         unsigned int i;
 667
 668         switch (clk_src) {
 669         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 670                 ni_m_series_clock = NI_M_TIMEBASE_1_CLK;
 671                 break;
 672         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 673                 ni_m_series_clock = NI_M_TIMEBASE_2_CLK;
 674                 break;
 675         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 676                 ni_m_series_clock = NI_M_TIMEBASE_3_CLK;
 677                 break;
 678         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 679                 ni_m_series_clock = NI_M_LOGIC_LOW_CLK;
 680                 break;
 681         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 682                 ni_m_series_clock = NI_M_NEXT_GATE_CLK;
 683                 break;
 684         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 685                 ni_m_series_clock = NI_M_NEXT_TC_CLK;
 686                 break;
 687         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 688                 ni_m_series_clock = NI_M_PXI10_CLK;
 689                 break;
 690         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 691                 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK;
 692                 break;
 693         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 694                 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK;
 695                 break;
 696         default:
 697                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 698                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 699                                 ni_m_series_clock = NI_M_RTSI_CLK(i);
 700                                 break;
 701                         }
 702                 }
 703                 if (i <= NI_M_MAX_RTSI_CHAN)
 704                         break;
 705                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 706                         if (clk_src == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
 707                                 ni_m_series_clock = NI_M_PFI_CLK(i);
 708                                 break;
 709                         }
 710                 }
 711                 if (i <= NI_M_MAX_PFI_CHAN)
 712                         break;
 713                 return -EINVAL;
 714         }
 715         *bits = GI_SRC_SEL(ni_m_series_clock);
 716         return 0;
 717 };
 718
 719 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
 720                                         unsigned int clock_source)
 721 {
 722         struct ni_gpct_device *counter_dev = counter->counter_dev;
 723         unsigned int cidx = counter->counter_index;
 724         unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
 725
 726         if (counter_dev->variant != ni_gpct_variant_m_series)
 727                 return;
 728         switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 729                 /* Gi_Source_Subselect is zero */
 730         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 731         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 732                 counter_dev->regs[second_gate_reg] &= ~GI_SRC_SUBSEL;
 733                 break;
 734                 /* Gi_Source_Subselect is one */
 735         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 736         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 737                 counter_dev->regs[second_gate_reg] |= GI_SRC_SUBSEL;
 738                 break;
 739                 /* Gi_Source_Subselect doesn't matter */
 740         default:
 741                 return;
 742         }
 743         ni_tio_write(counter, counter_dev->regs[second_gate_reg],
 744                      second_gate_reg);
 745 }
 746
 747 static int ni_tio_set_clock_src(struct ni_gpct *counter,
 748                                 unsigned int clock_source,
 749                                 unsigned int period_ns)
 750 {
 751         struct ni_gpct_device *counter_dev = counter->counter_dev;
 752         unsigned int cidx = counter->counter_index;
 753         unsigned int bits = 0;
 754         int ret;
 755
 756         switch (counter_dev->variant) {
 757         case ni_gpct_variant_660x:
 758                 ret = ni_660x_clk_src(clock_source, &bits);
 759                 break;
 760         case ni_gpct_variant_e_series:
 761         case ni_gpct_variant_m_series:
 762         default:
 763                 ret = ni_m_clk_src(clock_source, &bits);
 764                 break;
 765         }
 766         if (ret) {
 767                 struct comedi_device *dev = counter_dev->dev;
 768
 769                 dev_err(dev->class_dev, "invalid clock source 0x%x\n",
 770                         clock_source);
 771                 return ret;
 772         }
 773
 774         if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
 775                 bits |= GI_SRC_POL_INVERT;
 776         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 777                         GI_SRC_SEL_MASK | GI_SRC_POL_INVERT, bits);
 778         ni_tio_set_source_subselect(counter, clock_source);
 779
 780         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 781                 bits = 0;
 782                 switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 783                 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 784                         break;
 785                 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 786                         bits |= GI_PRESCALE_X2(counter_dev->variant);
 787                         break;
 788                 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 789                         bits |= GI_PRESCALE_X8(counter_dev->variant);
 790                         break;
 791                 default:
 792                         return -EINVAL;
 793                 }
 794                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 795                                 GI_PRESCALE_X2(counter_dev->variant) |
 796                                 GI_PRESCALE_X8(counter_dev->variant), bits);
 797         }
 798         counter->clock_period_ps = period_ns * 1000;
 799         ni_tio_set_sync_mode(counter);
 800         return 0;
 801 }
 802
 803 static int ni_tio_get_clock_src(struct ni_gpct *counter,
 804                                 unsigned int *clock_source,
 805                                 unsigned int *period_ns)
 806 {
 807         u64 temp64 = 0;
 808         int ret;
 809
 810         ret = ni_tio_generic_clock_src_select(counter, clock_source);
 811         if (ret)
 812                 return ret;
 813         ret = ni_tio_clock_period_ps(counter, *clock_source, &temp64);
 814         if (ret)
 815                 return ret;
 816         do_div(temp64, 1000);   /* ps to ns */
 817         *period_ns = temp64;
 818         return 0;
 819 }
 820
 821 static inline void ni_tio_set_gate_raw(struct ni_gpct *counter,
 822                                        unsigned int gate_source)
 823 {
 824         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(counter->counter_index),
 825                         GI_GATE_SEL_MASK, GI_GATE_SEL(gate_source));
 826 }
 827
 828 static inline void ni_tio_set_gate2_raw(struct ni_gpct *counter,
 829                                         unsigned int gate_source)
 830 {
 831         ni_tio_set_bits(counter, NITIO_GATE2_REG(counter->counter_index),
 832                         GI_GATE2_SEL_MASK, GI_GATE2_SEL(gate_source));
 833 }
 834
 835 /* Set the mode bits for gate. */
 836 static inline void ni_tio_set_gate_mode(struct ni_gpct *counter,
 837                                         unsigned int src)
 838 {
 839         unsigned int mode_bits = 0;
 840
 841         if (CR_CHAN(src) & NI_GPCT_DISABLED_GATE_SELECT) {
 842                 /*
 843                  * Allowing bitwise comparison here to allow non-zero raw
 844                  * register value to be used for channel when disabling.
 845                  */
 846                 mode_bits = GI_GATING_DISABLED;
 847         } else {
 848                 if (src & CR_INVERT)
 849                         mode_bits |= GI_GATE_POL_INVERT;
 850                 if (src & CR_EDGE)
 851                         mode_bits |= GI_RISING_EDGE_GATING;
 852                 else
 853                         mode_bits |= GI_LEVEL_GATING;
 854         }
 855         ni_tio_set_bits(counter, NITIO_MODE_REG(counter->counter_index),
 856                         GI_GATE_POL_INVERT | GI_GATING_MODE_MASK,
 857                         mode_bits);
 858 }
 859
 860 /*
 861  * Set the mode bits for gate2.
 862  *
 863  * Previously, the code this function represents did not actually write anything
 864  * to the register.  Rather, writing to this register was reserved for the code
 865  * ni ni_tio_set_gate2_raw.
 866  */
 867 static inline void ni_tio_set_gate2_mode(struct ni_gpct *counter,
 868                                          unsigned int src)
 869 {
 870         /*
 871          * The GI_GATE2_MODE bit was previously set in the code that also sets
 872          * the gate2 source.
 873          * We'll set mode bits _after_ source bits now, and thus, this function
 874          * will effectively enable the second gate after all bits are set.
 875          */
 876         unsigned int mode_bits = GI_GATE2_MODE;
 877
 878         if (CR_CHAN(src) & NI_GPCT_DISABLED_GATE_SELECT)
 879                 /*
 880                  * Allowing bitwise comparison here to allow non-zero raw
 881                  * register value to be used for channel when disabling.
 882                  */
 883                 mode_bits = GI_GATING_DISABLED;
 884         if (src & CR_INVERT)
 885                 mode_bits |= GI_GATE2_POL_INVERT;
 886
 887         ni_tio_set_bits(counter, NITIO_GATE2_REG(counter->counter_index),
 888                         GI_GATE2_POL_INVERT | GI_GATE2_MODE, mode_bits);
 889 }
 890
 891 static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 892 {
 893         unsigned int chan = CR_CHAN(gate_source);
 894         unsigned int gate_sel;
 895         unsigned int i;
 896
 897         switch (chan) {
 898         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 899                 gate_sel = NI_660X_NEXT_SRC_GATE_SEL;
 900                 break;
 901         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 902         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 903         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 904         case NI_GPCT_GATE_PIN_i_GATE_SELECT:
 905                 gate_sel = chan & 0x1f;
 906                 break;
 907         default:
 908                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 909                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 910                                 gate_sel = chan & 0x1f;
 911                                 break;
 912                         }
 913                 }
 914                 if (i <= NI_660X_MAX_RTSI_CHAN)
 915                         break;
 916                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
 917                         if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
 918                                 gate_sel = chan & 0x1f;
 919                                 break;
 920                         }
 921                 }
 922                 if (i <= NI_660X_MAX_GATE_PIN)
 923                         break;
 924                 return -EINVAL;
 925         }
 926         ni_tio_set_gate_raw(counter, gate_sel);
 927         return 0;
 928 }
 929
 930 static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 931 {
 932         unsigned int chan = CR_CHAN(gate_source);
 933         unsigned int gate_sel;
 934         unsigned int i;
 935
 936         switch (chan) {
 937         case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
 938         case NI_GPCT_AI_START2_GATE_SELECT:
 939         case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
 940         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 941         case NI_GPCT_AI_START1_GATE_SELECT:
 942         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 943         case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
 944         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 945                 gate_sel = chan & 0x1f;
 946                 break;
 947         default:
 948                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 949                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 950                                 gate_sel = chan & 0x1f;
 951                                 break;
 952                         }
 953                 }
 954                 if (i <= NI_M_MAX_RTSI_CHAN)
 955                         break;
 956                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 957                         if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
 958                                 gate_sel = chan & 0x1f;
 959                                 break;
 960                         }
 961                 }
 962                 if (i <= NI_M_MAX_PFI_CHAN)
 963                         break;
 964                 return -EINVAL;
 965         }
 966         ni_tio_set_gate_raw(counter, gate_sel);
 967         return 0;
 968 }
 969
 970 static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
 971 {
 972         unsigned int chan = CR_CHAN(gate_source);
 973         unsigned int gate2_sel;
 974         unsigned int i;
 975
 976         switch (chan) {
 977         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 978         case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
 979         case NI_GPCT_SELECTED_GATE_GATE_SELECT:
 980         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 981         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 982                 gate2_sel = chan & 0x1f;
 983                 break;
 984         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 985                 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL;
 986                 break;
 987         default:
 988                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 989                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 990                                 gate2_sel = chan & 0x1f;
 991                                 break;
 992                         }
 993                 }
 994                 if (i <= NI_660X_MAX_RTSI_CHAN)
 995                         break;
 996                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
 997                         if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
 998                                 gate2_sel = chan & 0x1f;
 999                                 break;
1000                         }
1001                 }
1002                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1003                         break;
1004                 return -EINVAL;
1005         }
1006         ni_tio_set_gate2_raw(counter, gate2_sel);
1007         return 0;
1008 }
1009
1010 static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
1011 {
1012         /*
1013          * FIXME: We don't know what the m-series second gate codes are,
1014          * so we'll just pass the bits through for now.
1015          */
1016         ni_tio_set_gate2_raw(counter, gate_source);
1017         return 0;
1018 }
1019
1020 int ni_tio_set_gate_src_raw(struct ni_gpct *counter,
1021                             unsigned int gate, unsigned int src)
1022 {
1023         struct ni_gpct_device *counter_dev = counter->counter_dev;
1024
1025         switch (gate) {
1026         case 0:
1027                 /* 1.  start by disabling gate */
1028                 ni_tio_set_gate_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1029                 /* 2.  set the requested gate source */
1030                 ni_tio_set_gate_raw(counter, src);
1031                 /* 3.  reenable & set mode to starts things back up */
1032                 ni_tio_set_gate_mode(counter, src);
1033                 break;
1034         case 1:
1035                 if (!ni_tio_has_gate2_registers(counter_dev))
1036                         return -EINVAL;
1037
1038                 /* 1.  start by disabling gate */
1039                 ni_tio_set_gate2_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1040                 /* 2.  set the requested gate source */
1041                 ni_tio_set_gate2_raw(counter, src);
1042                 /* 3.  reenable & set mode to starts things back up */
1043                 ni_tio_set_gate2_mode(counter, src);
1044                 break;
1045         default:
1046                 return -EINVAL;
1047         }
1048         return 0;
1049 }
1050 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src_raw);
1051
1052 int ni_tio_set_gate_src(struct ni_gpct *counter,
1053                         unsigned int gate, unsigned int src)
1054 {
1055         struct ni_gpct_device *counter_dev = counter->counter_dev;
1056         /*
1057          * mask off disable flag.  This high bit still passes CR_CHAN.
1058          * Doing this allows one to both set the gate as disabled, but also
1059          * change the route value of the gate.
1060          */
1061         int chan = CR_CHAN(src) & (~NI_GPCT_DISABLED_GATE_SELECT);
1062         int ret;
1063
1064         switch (gate) {
1065         case 0:
1066                 /* 1.  start by disabling gate */
1067                 ni_tio_set_gate_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1068                 /* 2.  set the requested gate source */
1069                 switch (counter_dev->variant) {
1070                 case ni_gpct_variant_e_series:
1071                 case ni_gpct_variant_m_series:
1072                         ret = ni_m_set_gate(counter, chan);
1073                         break;
1074                 case ni_gpct_variant_660x:
1075                         ret = ni_660x_set_gate(counter, chan);
1076                         break;
1077                 default:
1078                         return -EINVAL;
1079                 }
1080                 if (ret)
1081                         return ret;
1082                 /* 3.  reenable & set mode to starts things back up */
1083                 ni_tio_set_gate_mode(counter, src);
1084                 break;
1085         case 1:
1086                 if (!ni_tio_has_gate2_registers(counter_dev))
1087                         return -EINVAL;
1088
1089                 /* 1.  start by disabling gate */
1090                 ni_tio_set_gate2_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1091                 /* 2.  set the requested gate source */
1092                 switch (counter_dev->variant) {
1093                 case ni_gpct_variant_m_series:
1094                         ret = ni_m_set_gate2(counter, chan);
1095                         break;
1096                 case ni_gpct_variant_660x:
1097                         ret = ni_660x_set_gate2(counter, chan);
1098                         break;
1099                 default:
1100                         return -EINVAL;
1101                 }
1102                 if (ret)
1103                         return ret;
1104                 /* 3.  reenable & set mode to starts things back up */
1105                 ni_tio_set_gate2_mode(counter, src);
1106                 break;
1107         default:
1108                 return -EINVAL;
1109         }
1110         return 0;
1111 }
1112 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1113
1114 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned int index,
1115                                 unsigned int source)
1116 {
1117         struct ni_gpct_device *counter_dev = counter->counter_dev;
1118         unsigned int cidx = counter->counter_index;
1119         unsigned int abz_reg, shift, mask;
1120
1121         if (counter_dev->variant != ni_gpct_variant_m_series)
1122                 return -EINVAL;
1123
1124         abz_reg = NITIO_ABZ_REG(cidx);
1125
1126         /* allow for new device-global names */
1127         if (index == NI_GPCT_SOURCE_ENCODER_A ||
1128             (index >= NI_CtrA(0) && index <= NI_CtrA(-1))) {
1129                 shift = 10;
1130         } else if (index == NI_GPCT_SOURCE_ENCODER_B ||
1131             (index >= NI_CtrB(0) && index <= NI_CtrB(-1))) {
1132                 shift = 5;
1133         } else if (index == NI_GPCT_SOURCE_ENCODER_Z ||
1134             (index >= NI_CtrZ(0) && index <= NI_CtrZ(-1))) {
1135                 shift = 0;
1136         } else {
1137                 return -EINVAL;
1138         }
1139
1140         mask = 0x1f << shift;
1141         if (source > 0x1f)
1142                 source = 0x1f;  /* Disable gate */
1143
1144         counter_dev->regs[abz_reg] &= ~mask;
1145         counter_dev->regs[abz_reg] |= (source << shift) & mask;
1146         ni_tio_write(counter, counter_dev->regs[abz_reg], abz_reg);
1147         return 0;
1148 }
1149
1150 static int ni_tio_get_other_src(struct ni_gpct *counter, unsigned int index,
1151                                 unsigned int *source)
1152 {
1153         struct ni_gpct_device *counter_dev = counter->counter_dev;
1154         unsigned int cidx = counter->counter_index;
1155         unsigned int abz_reg, shift, mask;
1156
1157         if (counter_dev->variant != ni_gpct_variant_m_series)
1158                 /* A,B,Z only valid for m-series */
1159                 return -EINVAL;
1160
1161         abz_reg = NITIO_ABZ_REG(cidx);
1162
1163         /* allow for new device-global names */
1164         if (index == NI_GPCT_SOURCE_ENCODER_A ||
1165             (index >= NI_CtrA(0) && index <= NI_CtrA(-1))) {
1166                 shift = 10;
1167         } else if (index == NI_GPCT_SOURCE_ENCODER_B ||
1168             (index >= NI_CtrB(0) && index <= NI_CtrB(-1))) {
1169                 shift = 5;
1170         } else if (index == NI_GPCT_SOURCE_ENCODER_Z ||
1171             (index >= NI_CtrZ(0) && index <= NI_CtrZ(-1))) {
1172                 shift = 0;
1173         } else {
1174                 return -EINVAL;
1175         }
1176
1177         mask = 0x1f;
1178
1179         *source = (ni_tio_get_soft_copy(counter, abz_reg) >> shift) & mask;
1180         return 0;
1181 }
1182
1183 static int ni_660x_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1184 {
1185         unsigned int source;
1186         unsigned int i;
1187
1188         switch (gate) {
1189         case NI_660X_SRC_PIN_I_GATE_SEL:
1190                 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1191                 break;
1192         case NI_660X_GATE_PIN_I_GATE_SEL:
1193                 source = NI_GPCT_GATE_PIN_i_GATE_SELECT;
1194                 break;
1195         case NI_660X_NEXT_SRC_GATE_SEL:
1196                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1197                 break;
1198         case NI_660X_NEXT_OUT_GATE_SEL:
1199                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1200                 break;
1201         case NI_660X_LOGIC_LOW_GATE_SEL:
1202                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1203                 break;
1204         default:
1205                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1206                         if (gate == NI_660X_RTSI_GATE_SEL(i)) {
1207                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1208                                 break;
1209                         }
1210                 }
1211                 if (i <= NI_660X_MAX_RTSI_CHAN)
1212                         break;
1213                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
1214                         if (gate == NI_660X_PIN_GATE_SEL(i)) {
1215                                 source = NI_GPCT_GATE_PIN_GATE_SELECT(i);
1216                                 break;
1217                         }
1218                 }
1219                 if (i <= NI_660X_MAX_GATE_PIN)
1220                         break;
1221                 return -EINVAL;
1222         }
1223         *src = source;
1224         return 0;
1225 }
1226
1227 static int ni_m_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1228 {
1229         unsigned int source;
1230         unsigned int i;
1231
1232         switch (gate) {
1233         case NI_M_TIMESTAMP_MUX_GATE_SEL:
1234                 source = NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1235                 break;
1236         case NI_M_AI_START2_GATE_SEL:
1237                 source = NI_GPCT_AI_START2_GATE_SELECT;
1238                 break;
1239         case NI_M_PXI_STAR_TRIGGER_GATE_SEL:
1240                 source = NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1241                 break;
1242         case NI_M_NEXT_OUT_GATE_SEL:
1243                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1244                 break;
1245         case NI_M_AI_START1_GATE_SEL:
1246                 source = NI_GPCT_AI_START1_GATE_SELECT;
1247                 break;
1248         case NI_M_NEXT_SRC_GATE_SEL:
1249                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1250                 break;
1251         case NI_M_ANALOG_TRIG_OUT_GATE_SEL:
1252                 source = NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1253                 break;
1254         case NI_M_LOGIC_LOW_GATE_SEL:
1255                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1256                 break;
1257         default:
1258                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
1259                         if (gate == NI_M_RTSI_GATE_SEL(i)) {
1260                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1261                                 break;
1262                         }
1263                 }
1264                 if (i <= NI_M_MAX_RTSI_CHAN)
1265                         break;
1266                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
1267                         if (gate == NI_M_PFI_GATE_SEL(i)) {
1268                                 source = NI_GPCT_PFI_GATE_SELECT(i);
1269                                 break;
1270                         }
1271                 }
1272                 if (i <= NI_M_MAX_PFI_CHAN)
1273                         break;
1274                 return -EINVAL;
1275         }
1276         *src = source;
1277         return 0;
1278 }
1279
1280 static int ni_660x_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1281 {
1282         unsigned int source;
1283         unsigned int i;
1284
1285         switch (gate) {
1286         case NI_660X_SRC_PIN_I_GATE2_SEL:
1287                 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1288                 break;
1289         case NI_660X_UD_PIN_I_GATE2_SEL:
1290                 source = NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1291                 break;
1292         case NI_660X_NEXT_SRC_GATE2_SEL:
1293                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1294                 break;
1295         case NI_660X_NEXT_OUT_GATE2_SEL:
1296                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1297                 break;
1298         case NI_660X_SELECTED_GATE2_SEL:
1299                 source = NI_GPCT_SELECTED_GATE_GATE_SELECT;
1300                 break;
1301         case NI_660X_LOGIC_LOW_GATE2_SEL:
1302                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1303                 break;
1304         default:
1305                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1306                         if (gate == NI_660X_RTSI_GATE2_SEL(i)) {
1307                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1308                                 break;
1309                         }
1310                 }
1311                 if (i <= NI_660X_MAX_RTSI_CHAN)
1312                         break;
1313                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1314                         if (gate == NI_660X_UD_PIN_GATE2_SEL(i)) {
1315                                 source = NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1316                                 break;
1317                         }
1318                 }
1319                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1320                         break;
1321                 return -EINVAL;
1322         }
1323         *src = source;
1324         return 0;
1325 }
1326
1327 static int ni_m_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1328 {
1329         /*
1330          * FIXME: the second gate sources for the m series are undocumented,
1331          * so we just return the raw bits for now.
1332          */
1333         *src = gate;
1334         return 0;
1335 }
1336
1337 static inline unsigned int ni_tio_get_gate_mode(struct ni_gpct *counter)
1338 {
1339         unsigned int mode = ni_tio_get_soft_copy(
1340                 counter, NITIO_MODE_REG(counter->counter_index));
1341         unsigned int ret = 0;
1342
1343         if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED)
1344                 ret |= NI_GPCT_DISABLED_GATE_SELECT;
1345         if (mode & GI_GATE_POL_INVERT)
1346                 ret |= CR_INVERT;
1347         if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1348                 ret |= CR_EDGE;
1349
1350         return ret;
1351 }
1352
1353 static inline unsigned int ni_tio_get_gate2_mode(struct ni_gpct *counter)
1354 {
1355         unsigned int mode = ni_tio_get_soft_copy(
1356                 counter, NITIO_GATE2_REG(counter->counter_index));
1357         unsigned int ret = 0;
1358
1359         if (!(mode & GI_GATE2_MODE))
1360                 ret |= NI_GPCT_DISABLED_GATE_SELECT;
1361         if (mode & GI_GATE2_POL_INVERT)
1362                 ret |= CR_INVERT;
1363
1364         return ret;
1365 }
1366
1367 static inline unsigned int ni_tio_get_gate_val(struct ni_gpct *counter)
1368 {
1369         return GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter,
1370                 NITIO_INPUT_SEL_REG(counter->counter_index)));
1371 }
1372
1373 static inline unsigned int ni_tio_get_gate2_val(struct ni_gpct *counter)
1374 {
1375         return GI_BITS_TO_GATE2(ni_tio_get_soft_copy(counter,
1376                 NITIO_GATE2_REG(counter->counter_index)));
1377 }
1378
1379 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned int gate_index,
1380                                unsigned int *gate_source)
1381 {
1382         unsigned int gate;
1383         int ret;
1384
1385         switch (gate_index) {
1386         case 0:
1387                 gate = ni_tio_get_gate_val(counter);
1388                 switch (counter->counter_dev->variant) {
1389                 case ni_gpct_variant_e_series:
1390                 case ni_gpct_variant_m_series:
1391                 default:
1392                         ret = ni_m_gate_to_generic_gate(gate, gate_source);
1393                         break;
1394                 case ni_gpct_variant_660x:
1395                         ret = ni_660x_gate_to_generic_gate(gate, gate_source);
1396                         break;
1397                 }
1398                 if (ret)
1399                         return ret;
1400                 *gate_source |= ni_tio_get_gate_mode(counter);
1401                 break;
1402         case 1:
1403                 gate = ni_tio_get_gate2_val(counter);
1404                 switch (counter->counter_dev->variant) {
1405                 case ni_gpct_variant_e_series:
1406                 case ni_gpct_variant_m_series:
1407                 default:
1408                         ret = ni_m_gate2_to_generic_gate(gate, gate_source);
1409                         break;
1410                 case ni_gpct_variant_660x:
1411                         ret = ni_660x_gate2_to_generic_gate(gate, gate_source);
1412                         break;
1413                 }
1414                 if (ret)
1415                         return ret;
1416                 *gate_source |= ni_tio_get_gate2_mode(counter);
1417                 break;
1418         default:
1419                 return -EINVAL;
1420         }
1421         return 0;
1422 }
1423
1424 static int ni_tio_get_gate_src_raw(struct ni_gpct *counter,
1425                                    unsigned int gate_index,
1426                                    unsigned int *gate_source)
1427 {
1428         switch (gate_index) {
1429         case 0:
1430                 *gate_source = ni_tio_get_gate_mode(counter)
1431                              | ni_tio_get_gate_val(counter);
1432                 break;
1433         case 1:
1434                 *gate_source = ni_tio_get_gate2_mode(counter)
1435                              | ni_tio_get_gate2_val(counter);
1436                 break;
1437         default:
1438                 return -EINVAL;
1439         }
1440         return 0;
1441 }
1442
1443 int ni_tio_insn_config(struct comedi_device *dev,
1444                        struct comedi_subdevice *s,
1445                        struct comedi_insn *insn,
1446                        unsigned int *data)
1447 {
1448         struct ni_gpct *counter = s->private;
1449         unsigned int cidx = counter->counter_index;
1450         unsigned int status;
1451         int ret = 0;
1452
1453         switch (data[0]) {
1454         case INSN_CONFIG_SET_COUNTER_MODE:
1455                 ret = ni_tio_set_counter_mode(counter, data[1]);
1456                 break;
1457         case INSN_CONFIG_ARM:
1458                 ret = ni_tio_arm(counter, true, data[1]);
1459                 break;
1460         case INSN_CONFIG_DISARM:
1461                 ret = ni_tio_arm(counter, false, 0);
1462                 break;
1463         case INSN_CONFIG_GET_COUNTER_STATUS:
1464                 data[1] = 0;
1465                 status = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1466                 if (status & GI_ARMED(cidx)) {
1467                         data[1] |= COMEDI_COUNTER_ARMED;
1468                         if (status & GI_COUNTING(cidx))
1469                                 data[1] |= COMEDI_COUNTER_COUNTING;
1470                 }
1471                 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
1472                 break;
1473         case INSN_CONFIG_SET_CLOCK_SRC:
1474                 ret = ni_tio_set_clock_src(counter, data[1], data[2]);
1475                 break;
1476         case INSN_CONFIG_GET_CLOCK_SRC:
1477                 ret = ni_tio_get_clock_src(counter, &data[1], &data[2]);
1478                 break;
1479         case INSN_CONFIG_SET_GATE_SRC:
1480                 ret = ni_tio_set_gate_src(counter, data[1], data[2]);
1481                 break;
1482         case INSN_CONFIG_GET_GATE_SRC:
1483                 ret = ni_tio_get_gate_src(counter, data[1], &data[2]);
1484                 break;
1485         case INSN_CONFIG_SET_OTHER_SRC:
1486                 ret = ni_tio_set_other_src(counter, data[1], data[2]);
1487                 break;
1488         case INSN_CONFIG_RESET:
1489                 ni_tio_reset_count_and_disarm(counter);
1490                 break;
1491         default:
1492                 return -EINVAL;
1493         }
1494         return ret ? ret : insn->n;
1495 }
1496 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1497
1498 /**
1499  * Retrieves the register value of the current source of the output selector for
1500  * the given destination.
1501  *
1502  * If the terminal for the destination is not already configured as an output,
1503  * this function returns -EINVAL as error.
1504  *
1505  * Return: the register value of the destination output selector;
1506  *         -EINVAL if terminal is not configured for output.
1507  */
1508 int ni_tio_get_routing(struct ni_gpct_device *counter_dev, unsigned int dest)
1509 {
1510         /* we need to know the actual counter below... */
1511         int ctr_index = (dest - NI_COUNTER_NAMES_BASE) % NI_MAX_COUNTERS;
1512         struct ni_gpct *counter = &counter_dev->counters[ctr_index];
1513         int ret = 1;
1514         unsigned int reg;
1515
1516         if (dest >= NI_CtrA(0) && dest <= NI_CtrZ(-1)) {
1517                 ret = ni_tio_get_other_src(counter, dest, &reg);
1518         } else if (dest >= NI_CtrGate(0) && dest <= NI_CtrGate(-1)) {
1519                 ret = ni_tio_get_gate_src_raw(counter, 0, &reg);
1520         } else if (dest >= NI_CtrAux(0) && dest <= NI_CtrAux(-1)) {
1521                 ret = ni_tio_get_gate_src_raw(counter, 1, &reg);
1522         /*
1523          * This case is not possible through this interface.  A user must use
1524          * INSN_CONFIG_SET_CLOCK_SRC instead.
1525          * } else if (dest >= NI_CtrSource(0) && dest <= NI_CtrSource(-1)) {
1526          *      ret = ni_tio_set_clock_src(counter, &reg, &period_ns);
1527          */
1528         }
1529
1530         if (ret)
1531                 return -EINVAL;
1532
1533         return reg;
1534 }
1535 EXPORT_SYMBOL_GPL(ni_tio_get_routing);
1536
1537 /**
1538  * Sets the register value of the selector MUX for the given destination.
1539  * @counter_dev:Pointer to general counter device.
1540  * @destination:Device-global identifier of route destination.
1541  * @register_value:
1542  *              The first several bits of this value should store the desired
1543  *              value to write to the register.  All other bits are for
1544  *              transmitting information that modify the mode of the particular
1545  *              destination/gate.  These mode bits might include a bitwise or of
1546  *              CR_INVERT and CR_EDGE.  Note that the calling function should
1547  *              have already validated the correctness of this value.
1548  */
1549 int ni_tio_set_routing(struct ni_gpct_device *counter_dev, unsigned int dest,
1550                        unsigned int reg)
1551 {
1552         /* we need to know the actual counter below... */
1553         int ctr_index = (dest - NI_COUNTER_NAMES_BASE) % NI_MAX_COUNTERS;
1554         struct ni_gpct *counter = &counter_dev->counters[ctr_index];
1555         int ret;
1556
1557         if (dest >= NI_CtrA(0) && dest <= NI_CtrZ(-1)) {
1558                 ret = ni_tio_set_other_src(counter, dest, reg);
1559         } else if (dest >= NI_CtrGate(0) && dest <= NI_CtrGate(-1)) {
1560                 ret = ni_tio_set_gate_src_raw(counter, 0, reg);
1561         } else if (dest >= NI_CtrAux(0) && dest <= NI_CtrAux(-1)) {
1562                 ret = ni_tio_set_gate_src_raw(counter, 1, reg);
1563         /*
1564          * This case is not possible through this interface.  A user must use
1565          * INSN_CONFIG_SET_CLOCK_SRC instead.
1566          * } else if (dest >= NI_CtrSource(0) && dest <= NI_CtrSource(-1)) {
1567          *      ret = ni_tio_set_clock_src(counter, reg, period_ns);
1568          */
1569         } else {
1570                 return -EINVAL;
1571         }
1572
1573         return ret;
1574 }
1575 EXPORT_SYMBOL_GPL(ni_tio_set_routing);
1576
1577 /**
1578  * Sets the given destination MUX to its default value or disable it.
1579  *
1580  * Return: 0 if successful; -EINVAL if terminal is unknown.
1581  */
1582 int ni_tio_unset_routing(struct ni_gpct_device *counter_dev, unsigned int dest)
1583 {
1584         if (dest >= NI_GATES_NAMES_BASE && dest <= NI_GATES_NAMES_MAX)
1585                 /* Disable gate (via mode bits) and set to default 0-value */
1586                 return ni_tio_set_routing(counter_dev, dest,
1587                                           NI_GPCT_DISABLED_GATE_SELECT);
1588         /*
1589          * This case is not possible through this interface.  A user must use
1590          * INSN_CONFIG_SET_CLOCK_SRC instead.
1591          * if (dest >= NI_CtrSource(0) && dest <= NI_CtrSource(-1))
1592          *      return ni_tio_set_clock_src(counter, reg, period_ns);
1593          */
1594
1595         return -EINVAL;
1596 }
1597 EXPORT_SYMBOL_GPL(ni_tio_unset_routing);
1598
1599 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1600                                             struct comedi_subdevice *s)
1601 {
1602         struct ni_gpct *counter = s->private;
1603         unsigned int cidx = counter->counter_index;
1604         unsigned int val;
1605
1606         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
1607         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1608                         GI_SAVE_TRACE, GI_SAVE_TRACE);
1609
1610         /*
1611          * The count doesn't get latched until the next clock edge, so it is
1612          * possible the count may change (once) while we are reading. Since
1613          * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1614          * a 32 bit register according to 660x docs), we need to read twice
1615          * and make sure the reading hasn't changed. If it has, a third read
1616          * will be correct since the count value will definitely have latched
1617          * by then.
1618          */
1619         val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1620         if (val != ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)))
1621                 val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1622
1623         return val;
1624 }
1625
1626 int ni_tio_insn_read(struct comedi_device *dev,
1627                      struct comedi_subdevice *s,
1628                      struct comedi_insn *insn,
1629                      unsigned int *data)
1630 {
1631         struct ni_gpct *counter = s->private;
1632         struct ni_gpct_device *counter_dev = counter->counter_dev;
1633         unsigned int channel = CR_CHAN(insn->chanspec);
1634         unsigned int cidx = counter->counter_index;
1635         int i;
1636
1637         for (i = 0; i < insn->n; i++) {
1638                 switch (channel) {
1639                 case 0:
1640                         data[i] = ni_tio_read_sw_save_reg(dev, s);
1641                         break;
1642                 case 1:
1643                         data[i] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
1644                         break;
1645                 case 2:
1646                         data[i] = counter_dev->regs[NITIO_LOADB_REG(cidx)];
1647                         break;
1648                 }
1649         }
1650         return insn->n;
1651 }
1652 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1653
1654 static unsigned int ni_tio_next_load_register(struct ni_gpct *counter)
1655 {
1656         unsigned int cidx = counter->counter_index;
1657         unsigned int bits = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1658
1659         return (bits & GI_NEXT_LOAD_SRC(cidx))
1660                         ? NITIO_LOADB_REG(cidx)
1661                         : NITIO_LOADA_REG(cidx);
1662 }
1663
1664 int ni_tio_insn_write(struct comedi_device *dev,
1665                       struct comedi_subdevice *s,
1666                       struct comedi_insn *insn,
1667                       unsigned int *data)
1668 {
1669         struct ni_gpct *counter = s->private;
1670         struct ni_gpct_device *counter_dev = counter->counter_dev;
1671         unsigned int channel = CR_CHAN(insn->chanspec);
1672         unsigned int cidx = counter->counter_index;
1673         unsigned int load_reg;
1674
1675         if (insn->n < 1)
1676                 return 0;
1677         switch (channel) {
1678         case 0:
1679                 /*
1680                  * Unsafe if counter is armed.
1681                  * Should probably check status and return -EBUSY if armed.
1682                  */
1683
1684                 /*
1685                  * Don't disturb load source select, just use whichever
1686                  * load register is already selected.
1687                  */
1688                 load_reg = ni_tio_next_load_register(counter);
1689                 ni_tio_write(counter, data[0], load_reg);
1690                 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1691                                           0, 0, GI_LOAD);
1692                 /* restore load reg */
1693                 ni_tio_write(counter, counter_dev->regs[load_reg], load_reg);
1694                 break;
1695         case 1:
1696                 counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0];
1697                 ni_tio_write(counter, data[0], NITIO_LOADA_REG(cidx));
1698                 break;
1699         case 2:
1700                 counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0];
1701                 ni_tio_write(counter, data[0], NITIO_LOADB_REG(cidx));
1702                 break;
1703         default:
1704                 return -EINVAL;
1705         }
1706         return 0;
1707 }
1708 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1709
1710 void ni_tio_init_counter(struct ni_gpct *counter)
1711 {
1712         struct ni_gpct_device *counter_dev = counter->counter_dev;
1713         unsigned int cidx = counter->counter_index;
1714
1715         ni_tio_reset_count_and_disarm(counter);
1716
1717         /* initialize counter registers */
1718         counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0;
1719         ni_tio_write(counter, 0x0, NITIO_AUTO_INC_REG(cidx));
1720
1721         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1722                         ~0, GI_SYNC_GATE);
1723
1724         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
1725
1726         counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0;
1727         ni_tio_write(counter, 0x0, NITIO_LOADA_REG(cidx));
1728
1729         counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0;
1730         ni_tio_write(counter, 0x0, NITIO_LOADB_REG(cidx));
1731
1732         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
1733
1734         if (ni_tio_counting_mode_registers_present(counter_dev))
1735                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
1736
1737         if (ni_tio_has_gate2_registers(counter_dev)) {
1738                 counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0;
1739                 ni_tio_write(counter, 0x0, NITIO_GATE2_REG(cidx));
1740         }
1741
1742         ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
1743
1744         ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
1745 }
1746 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1747
1748 struct ni_gpct_device *
1749 ni_gpct_device_construct(struct comedi_device *dev,
1750                          void (*write)(struct ni_gpct *counter,
1751                                        unsigned int value,
1752                                        enum ni_gpct_register reg),
1753                          unsigned int (*read)(struct ni_gpct *counter,
1754                                               enum ni_gpct_register reg),
1755                          enum ni_gpct_variant variant,
1756                          unsigned int num_counters,
1757                          unsigned int counters_per_chip,
1758                          const struct ni_route_tables *routing_tables)
1759 {
1760         struct ni_gpct_device *counter_dev;
1761         struct ni_gpct *counter;
1762         unsigned int i;
1763
1764         if (num_counters == 0 || counters_per_chip == 0)
1765                 return NULL;
1766
1767         counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL);
1768         if (!counter_dev)
1769                 return NULL;
1770
1771         counter_dev->dev = dev;
1772         counter_dev->write = write;
1773         counter_dev->read = read;
1774         counter_dev->variant = variant;
1775         counter_dev->routing_tables = routing_tables;
1776
1777         spin_lock_init(&counter_dev->regs_lock);
1778
1779         counter_dev->counters = kcalloc(num_counters, sizeof(*counter),
1780                                         GFP_KERNEL);
1781         if (!counter_dev->counters) {
1782                 kfree(counter_dev);
1783                 return NULL;
1784         }
1785
1786         for (i = 0; i < num_counters; ++i) {
1787                 counter = &counter_dev->counters[i];
1788                 counter->counter_dev = counter_dev;
1789                 counter->chip_index = i / counters_per_chip;
1790                 counter->counter_index = i % counters_per_chip;
1791                 spin_lock_init(&counter->lock);
1792         }
1793         counter_dev->num_counters = num_counters;
1794         counter_dev->counters_per_chip = counters_per_chip;
1795
1796         return counter_dev;
1797 }
1798 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1799
1800 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
1801 {
1802         if (!counter_dev)
1803                 return;
1804         kfree(counter_dev->counters);
1805         kfree(counter_dev);
1806 }
1807 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
1808
1809 static int __init ni_tio_init_module(void)
1810 {
1811         return 0;
1812 }
1813 module_init(ni_tio_init_module);
1814
1815 static void __exit ni_tio_cleanup_module(void)
1816 {
1817 }
1818 module_exit(ni_tio_cleanup_module);
1819
1820 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1821 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1822 MODULE_LICENSE("GPL");