2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: National Instruments PCI-MIO-E series and M series (all boards)
21 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
22 Herman Bruyninckx, Terry Barnaby
24 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
25 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
26 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
27 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
28 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224,
29 PCI-6225, PXI-6225, PCI-6229, PCI-6250,
30 PCI-6251, PXI-6251, PCIe-6251, PXIe-6251,
31 PCI-6254, PCI-6259, PCIe-6259,
32 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
33 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
34 PXI-6071E, PCI-6070E, PXI-6070E,
35 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
37 Updated: Mon, 09 Jan 2012 14:52:48 +0000
39 These boards are almost identical to the AT-MIO E series, except that
40 they use the PCI bus instead of ISA (i.e., AT). See the notes for
41 the ni_atmio.o driver for additional information about these boards.
43 Autocalibration is supported on many of the devices, using the
44 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
45 M-Series boards do analog input and analog output calibration entirely
46 in software. The software calibration corrects
47 the analog input for offset, gain and
48 nonlinearity. The analog outputs are corrected for offset and gain.
49 See the comedilib documentation on comedi_get_softcal_converter() for
52 By default, the driver uses DMA to transfer analog input data to
53 memory. When DMA is enabled, not all triggering features are
56 Digital I/O may not work on 673x.
58 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
59 With this board all of the convertors perform one simultaineous sample during
60 a scan interval. The period for a scan is used for the convert time in a
61 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
63 The RTSI trigger bus is supported on these cards on
64 subdevice 10. See the comedilib documentation for details.
66 Information (number of channels, bits, etc.) for some devices may be
67 incorrect. Please check this and submit a bug if there are problems
70 SCXI is probably broken for m-series boards.
73 - When DMA is enabled, COMEDI_EV_CONVERT does
78 The PCI-MIO E series driver was originally written by
79 Tomasz Motylewski <...>, and ported to comedi by ds.
83 341079b.pdf PCI E Series Register-Level Programmer Manual
84 340934b.pdf DAQ-STC reference manual
86 322080b.pdf 6711/6713/6715 User Manual
88 320945c.pdf PCI E Series User Manual
89 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
93 need to deal with external reference for DAC, and other DAC
94 properties in board properties
96 deal with at-mio-16de-10 revision D to N changes, etc.
98 need to add other CALDAC type
100 need to slow down DAC loading. I don't trust NI's claim that
101 two writes to the PCI bus slows IO enough. I would prefer to
102 use udelay(). Timing specs: (clock)
110 #include <linux/module.h>
111 #include <linux/delay.h>
113 #include "../comedi_pci.h"
115 #include <asm/byteorder.h>
122 /* These are not all the possible ao ranges for 628x boards.
123 They can do OFFSET +- REFERENCE where OFFSET can be
124 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
125 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
126 63 different possibilities. An AO channel
127 can not act as it's own OFFSET or REFERENCE.
129 static const struct comedi_lrange range_ni_M_628x_ao = {
143 static const struct comedi_lrange range_ni_M_625x_ao = {
151 enum ni_pcimio_boardid {
152 BOARD_PCIMIO_16XE_50,
153 BOARD_PCIMIO_16XE_10,
212 static const struct ni_board_struct ni_boards[] = {
213 [BOARD_PCIMIO_16XE_50] = {
214 .name = "pci-mio-16xe-50",
216 .ai_maxdata = 0xffff,
217 .ai_fifo_depth = 2048,
219 .gainlkup = ai_gain_8,
222 .ao_maxdata = 0x0fff,
223 .ao_range_table = &range_bipolar10,
225 .caldac = { dac8800, dac8043 },
227 [BOARD_PCIMIO_16XE_10] = {
228 .name = "pci-mio-16xe-10", /* aka pci-6030E */
230 .ai_maxdata = 0xffff,
231 .ai_fifo_depth = 512,
233 .gainlkup = ai_gain_14,
236 .ao_maxdata = 0xffff,
237 .ao_fifo_depth = 2048,
238 .ao_range_table = &range_ni_E_ao_ext,
240 .caldac = { dac8800, dac8043, ad8522 },
245 .ai_maxdata = 0xffff,
246 .ai_fifo_depth = 512,
248 .gainlkup = ai_gain_4,
251 .ao_maxdata = 0xffff,
252 .ao_range_table = &range_bipolar10,
254 .caldac = { ad8804_debug },
259 .ai_maxdata = 0xffff,
260 .ai_fifo_depth = 512,
262 .gainlkup = ai_gain_14,
265 .ao_maxdata = 0xffff,
266 .ao_fifo_depth = 2048,
267 .ao_range_table = &range_ni_E_ao_ext,
269 .caldac = { dac8800, dac8043, ad8522 },
271 [BOARD_PCIMIO_16E_1] = {
272 .name = "pci-mio-16e-1", /* aka pci-6070e */
274 .ai_maxdata = 0x0fff,
275 .ai_fifo_depth = 512,
276 .gainlkup = ai_gain_16,
279 .ao_maxdata = 0x0fff,
280 .ao_fifo_depth = 2048,
281 .ao_range_table = &range_ni_E_ao_ext,
283 .caldac = { mb88341 },
285 [BOARD_PCIMIO_16E_4] = {
286 .name = "pci-mio-16e-4", /* aka pci-6040e */
288 .ai_maxdata = 0x0fff,
289 .ai_fifo_depth = 512,
290 .gainlkup = ai_gain_16,
292 * there have been reported problems with
293 * full speed on this board
297 .ao_maxdata = 0x0fff,
298 .ao_fifo_depth = 512,
299 .ao_range_table = &range_ni_E_ao_ext,
301 .caldac = { ad8804_debug }, /* doc says mb88341 */
306 .ai_maxdata = 0x0fff,
307 .ai_fifo_depth = 512,
308 .gainlkup = ai_gain_16,
311 .ao_maxdata = 0x0fff,
312 .ao_fifo_depth = 512,
313 .ao_range_table = &range_ni_E_ao_ext,
315 .caldac = { mb88341 },
320 .ai_maxdata = 0xffff,
321 .ai_fifo_depth = 512,
323 .gainlkup = ai_gain_14,
326 .ao_maxdata = 0xffff,
327 .ao_fifo_depth = 2048,
328 .ao_range_table = &range_ni_E_ao_ext,
330 .caldac = { dac8800, dac8043, ad8522 },
335 .ai_maxdata = 0xffff,
336 .ai_fifo_depth = 512,
338 .gainlkup = ai_gain_14,
340 .caldac = { dac8800, dac8043, ad8522 },
345 .ai_maxdata = 0xffff,
346 .ai_fifo_depth = 512,
348 .gainlkup = ai_gain_14,
350 .caldac = { dac8800, dac8043, ad8522 },
355 .ai_maxdata = 0x0fff,
356 .ai_fifo_depth = 512,
358 .gainlkup = ai_gain_16,
361 .ao_maxdata = 0x0fff,
362 .ao_fifo_depth = 2048,
363 .ao_range_table = &range_ni_E_ao_ext,
365 .caldac = { ad8804_debug },
370 .ai_maxdata = 0x0fff,
371 .ai_fifo_depth = 512,
372 .gainlkup = ai_gain_4,
374 .caldac = { ad8804_debug }, /* manual is wrong */
379 .ai_maxdata = 0x0fff,
380 .ai_fifo_depth = 512,
381 .gainlkup = ai_gain_4,
384 .ao_maxdata = 0x0fff,
385 .ao_range_table = &range_bipolar10,
387 .caldac = { ad8804_debug }, /* manual is wrong */
392 .ai_maxdata = 0x0fff,
393 .ai_fifo_depth = 512,
394 .gainlkup = ai_gain_4,
397 .ao_maxdata = 0x0fff,
398 .ao_range_table = &range_bipolar10,
400 .caldac = { ad8804_debug }, /* manual is wrong */
406 .ai_maxdata = 0x0fff,
407 .ai_fifo_depth = 512,
408 .gainlkup = ai_gain_4,
411 .ao_maxdata = 0x0fff,
412 .ao_range_table = &range_ni_E_ao_ext,
414 .caldac = { ad8804_debug }, /* manual is wrong */
420 .ai_maxdata = 0xffff,
421 .ai_fifo_depth = 512,
423 .gainlkup = ai_gain_4,
425 .caldac = { ad8804_debug },
430 .ai_maxdata = 0xffff,
431 .ai_fifo_depth = 512,
433 .gainlkup = ai_gain_4,
436 .ao_maxdata = 0x0fff,
437 .ao_range_table = &range_bipolar10,
439 .caldac = { ad8804_debug },
444 .ai_maxdata = 0xffff,
445 .ai_fifo_depth = 512,
447 .gainlkup = ai_gain_16,
450 .ao_maxdata = 0xffff,
451 .ao_fifo_depth = 2048,
452 .ao_range_table = &range_ni_E_ao_ext,
454 /* manual is wrong */
455 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
460 .ai_maxdata = 0x0fff,
461 .ai_fifo_depth = 8192,
463 .gainlkup = ai_gain_611x,
466 .ao_maxdata = 0xffff,
467 .reg_type = ni_reg_611x,
468 .ao_range_table = &range_bipolar10,
469 .ao_fifo_depth = 2048,
471 .caldac = { ad8804, ad8804 },
476 .ai_maxdata = 0x0fff,
477 .ai_fifo_depth = 8192,
478 .gainlkup = ai_gain_611x,
481 .ao_maxdata = 0xffff,
482 .reg_type = ni_reg_611x,
483 .ao_range_table = &range_bipolar10,
484 .ao_fifo_depth = 2048,
486 .caldac = { ad8804, ad8804 },
489 /* The 6115 boards probably need their own driver */
490 [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */
493 .ai_maxdata = 0x0fff,
494 .ai_fifo_depth = 8192,
495 .gainlkup = ai_gain_611x,
498 .ao_maxdata = 0xffff,
500 .ao_fifo_depth = 2048,
504 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
508 [BOARD_PXI6115] = { /* .device_id = ????, */
511 .ai_maxdata = 0x0fff,
512 .ai_fifo_depth = 8192,
513 .gainlkup = ai_gain_611x,
516 .ao_maxdata = 0xffff,
518 .ao_fifo_depth = 2048,
522 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
528 .ao_maxdata = 0x0fff,
529 /* data sheet says 8192, but fifo really holds 16384 samples */
530 .ao_fifo_depth = 16384,
531 .ao_range_table = &range_bipolar10,
533 .reg_type = ni_reg_6711,
534 .caldac = { ad8804_debug },
539 .ao_maxdata = 0x0fff,
540 .ao_fifo_depth = 16384,
541 .ao_range_table = &range_bipolar10,
543 .reg_type = ni_reg_6711,
544 .caldac = { ad8804_debug },
549 .ao_maxdata = 0x0fff,
550 .ao_fifo_depth = 16384,
551 .ao_range_table = &range_bipolar10,
553 .reg_type = ni_reg_6713,
554 .caldac = { ad8804_debug, ad8804_debug },
559 .ao_maxdata = 0x0fff,
560 .ao_fifo_depth = 16384,
561 .ao_range_table = &range_bipolar10,
563 .reg_type = ni_reg_6713,
564 .caldac = { ad8804_debug, ad8804_debug },
569 .ao_maxdata = 0xffff,
570 .ao_fifo_depth = 8192,
571 .ao_range_table = &range_bipolar10,
573 .reg_type = ni_reg_6711,
574 .caldac = { ad8804_debug },
577 [BOARD_PXI6731] = { /* .device_id = ????, */
580 .ao_maxdata = 0xffff,
581 .ao_fifo_depth = 8192,
582 .ao_range_table = &range_bipolar10,
583 .reg_type = ni_reg_6711,
584 .caldac = { ad8804_debug },
590 .ao_maxdata = 0xffff,
591 .ao_fifo_depth = 16384,
592 .ao_range_table = &range_bipolar10,
594 .reg_type = ni_reg_6713,
595 .caldac = { ad8804_debug, ad8804_debug },
600 .ao_maxdata = 0xffff,
601 .ao_fifo_depth = 16384,
602 .ao_range_table = &range_bipolar10,
604 .reg_type = ni_reg_6713,
605 .caldac = { ad8804_debug, ad8804_debug },
610 .ai_maxdata = 0x0fff,
611 .ai_fifo_depth = 512,
613 .gainlkup = ai_gain_16,
616 .ao_maxdata = 0x0fff,
617 .ao_fifo_depth = 2048,
618 .ao_range_table = &range_ni_E_ao_ext,
620 .caldac = { ad8804_debug },
625 .ai_maxdata = 0x0fff,
626 .ai_fifo_depth = 512,
628 .gainlkup = ai_gain_16,
631 .ao_maxdata = 0x0fff,
632 .ao_fifo_depth = 2048,
633 .ao_range_table = &range_ni_E_ao_ext,
635 .caldac = { ad8804_debug },
640 .ai_maxdata = 0xffff,
641 .ai_fifo_depth = 512,
643 .gainlkup = ai_gain_16,
646 .ao_maxdata = 0xffff,
647 .ao_fifo_depth = 2048,
648 .ao_range_table = &range_ni_E_ao_ext,
650 .caldac = { mb88341, mb88341, ad8522 },
655 .ai_maxdata = 0xffff,
656 .ai_fifo_depth = 512,
658 .gainlkup = ai_gain_14,
661 .ao_maxdata = 0xffff,
662 .ao_fifo_depth = 2048,
663 .ao_range_table = &range_ni_E_ao_ext,
665 .caldac = { dac8800, dac8043, ad8522 },
670 .ai_maxdata = 0xffff,
671 .ai_fifo_depth = 512,
673 .gainlkup = ai_gain_4,
676 .ao_maxdata = 0xffff,
677 .ao_range_table = &range_bipolar10,
679 .caldac = { ad8804_debug },
684 .ai_maxdata = 0xffff,
685 .ai_fifo_depth = 512, /* FIXME: guess */
686 .gainlkup = ai_gain_622x,
688 .reg_type = ni_reg_622x,
689 .caldac = { caldac_none },
694 .ai_maxdata = 0xffff,
695 .ai_fifo_depth = 4095,
696 .gainlkup = ai_gain_622x,
699 .ao_maxdata = 0xffff,
700 .ao_fifo_depth = 8191,
701 .ao_range_table = &range_bipolar10,
702 .reg_type = ni_reg_622x,
704 .caldac = { caldac_none },
706 [BOARD_PCI6221_37PIN] = {
707 .name = "pci-6221_37pin",
709 .ai_maxdata = 0xffff,
710 .ai_fifo_depth = 4095,
711 .gainlkup = ai_gain_622x,
714 .ao_maxdata = 0xffff,
715 .ao_fifo_depth = 8191,
716 .ao_range_table = &range_bipolar10,
717 .reg_type = ni_reg_622x,
719 .caldac = { caldac_none },
724 .ai_maxdata = 0xffff,
725 .ai_fifo_depth = 4095,
726 .gainlkup = ai_gain_622x,
728 .reg_type = ni_reg_622x,
730 .caldac = { caldac_none },
735 .ai_maxdata = 0xffff,
736 .ai_fifo_depth = 4095,
737 .gainlkup = ai_gain_622x,
739 .reg_type = ni_reg_622x,
741 .caldac = { caldac_none },
746 .ai_maxdata = 0xffff,
747 .ai_fifo_depth = 4095,
748 .gainlkup = ai_gain_622x,
751 .ao_maxdata = 0xffff,
752 .ao_fifo_depth = 8191,
753 .ao_range_table = &range_bipolar10,
754 .reg_type = ni_reg_622x,
757 .caldac = { caldac_none },
762 .ai_maxdata = 0xffff,
763 .ai_fifo_depth = 4095,
764 .gainlkup = ai_gain_622x,
767 .ao_maxdata = 0xffff,
768 .ao_fifo_depth = 8191,
769 .ao_range_table = &range_bipolar10,
770 .reg_type = ni_reg_622x,
773 .caldac = { caldac_none },
778 .ai_maxdata = 0xffff,
779 .ai_fifo_depth = 4095,
780 .gainlkup = ai_gain_622x,
783 .ao_maxdata = 0xffff,
784 .ao_fifo_depth = 8191,
785 .ao_range_table = &range_bipolar10,
786 .reg_type = ni_reg_622x,
789 .caldac = { caldac_none },
794 .ai_maxdata = 0xffff,
795 .ai_fifo_depth = 4095,
796 .gainlkup = ai_gain_628x,
798 .reg_type = ni_reg_625x,
799 .caldac = { caldac_none },
804 .ai_maxdata = 0xffff,
805 .ai_fifo_depth = 4095,
806 .gainlkup = ai_gain_628x,
809 .ao_maxdata = 0xffff,
810 .ao_fifo_depth = 8191,
811 .ao_range_table = &range_ni_M_625x_ao,
812 .reg_type = ni_reg_625x,
814 .caldac = { caldac_none },
819 .ai_maxdata = 0xffff,
820 .ai_fifo_depth = 4095,
821 .gainlkup = ai_gain_628x,
824 .ao_maxdata = 0xffff,
825 .ao_fifo_depth = 8191,
826 .ao_range_table = &range_ni_M_625x_ao,
827 .reg_type = ni_reg_625x,
829 .caldac = { caldac_none },
834 .ai_maxdata = 0xffff,
835 .ai_fifo_depth = 4095,
836 .gainlkup = ai_gain_628x,
839 .ao_maxdata = 0xffff,
840 .ao_fifo_depth = 8191,
841 .ao_range_table = &range_ni_M_625x_ao,
842 .reg_type = ni_reg_625x,
844 .caldac = { caldac_none },
849 .ai_maxdata = 0xffff,
850 .ai_fifo_depth = 4095,
851 .gainlkup = ai_gain_628x,
854 .ao_maxdata = 0xffff,
855 .ao_fifo_depth = 8191,
856 .ao_range_table = &range_ni_M_625x_ao,
857 .reg_type = ni_reg_625x,
859 .caldac = { caldac_none },
864 .ai_maxdata = 0xffff,
865 .ai_fifo_depth = 4095,
866 .gainlkup = ai_gain_628x,
868 .reg_type = ni_reg_625x,
870 .caldac = { caldac_none },
875 .ai_maxdata = 0xffff,
876 .ai_fifo_depth = 4095,
877 .gainlkup = ai_gain_628x,
880 .ao_maxdata = 0xffff,
881 .ao_fifo_depth = 8191,
882 .ao_range_table = &range_ni_M_625x_ao,
883 .reg_type = ni_reg_625x,
886 .caldac = { caldac_none },
891 .ai_maxdata = 0xffff,
892 .ai_fifo_depth = 4095,
893 .gainlkup = ai_gain_628x,
896 .ao_maxdata = 0xffff,
897 .ao_fifo_depth = 8191,
898 .ao_range_table = &range_ni_M_625x_ao,
899 .reg_type = ni_reg_625x,
902 .caldac = { caldac_none },
907 .ai_maxdata = 0x3ffff,
908 .ai_fifo_depth = 2047,
909 .gainlkup = ai_gain_628x,
911 .ao_fifo_depth = 8191,
912 .reg_type = ni_reg_628x,
913 .caldac = { caldac_none },
918 .ai_maxdata = 0x3ffff,
919 .ai_fifo_depth = 2047,
920 .gainlkup = ai_gain_628x,
923 .ao_maxdata = 0xffff,
924 .ao_fifo_depth = 8191,
925 .ao_range_table = &range_ni_M_628x_ao,
926 .reg_type = ni_reg_628x,
928 .caldac = { caldac_none },
933 .ai_maxdata = 0x3ffff,
934 .ai_fifo_depth = 2047,
935 .gainlkup = ai_gain_628x,
938 .ao_maxdata = 0xffff,
939 .ao_fifo_depth = 8191,
940 .ao_range_table = &range_ni_M_628x_ao,
941 .reg_type = ni_reg_628x,
943 .caldac = { caldac_none },
948 .ai_maxdata = 0x3ffff,
949 .ai_fifo_depth = 2047,
950 .gainlkup = ai_gain_628x,
952 .reg_type = ni_reg_628x,
954 .caldac = { caldac_none },
959 .ai_maxdata = 0x3ffff,
960 .ai_fifo_depth = 2047,
961 .gainlkup = ai_gain_628x,
964 .ao_maxdata = 0xffff,
965 .ao_fifo_depth = 8191,
966 .ao_range_table = &range_ni_M_628x_ao,
967 .reg_type = ni_reg_628x,
970 .caldac = { caldac_none },
975 .ai_maxdata = 0xffff,
976 .ai_fifo_depth = 1024,
977 .gainlkup = ai_gain_6143,
979 .reg_type = ni_reg_6143,
980 .caldac = { ad8804_debug, ad8804_debug },
985 .ai_maxdata = 0xffff,
986 .ai_fifo_depth = 1024,
987 .gainlkup = ai_gain_6143,
989 .reg_type = ni_reg_6143,
990 .caldac = { ad8804_debug, ad8804_debug },
994 #include "ni_mio_common.c"
996 static int pcimio_ai_change(struct comedi_device *dev,
997 struct comedi_subdevice *s)
999 struct ni_private *devpriv = dev->private;
1002 ret = mite_buf_change(devpriv->ai_mite_ring, s);
1009 static int pcimio_ao_change(struct comedi_device *dev,
1010 struct comedi_subdevice *s)
1012 struct ni_private *devpriv = dev->private;
1015 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1022 static int pcimio_gpct0_change(struct comedi_device *dev,
1023 struct comedi_subdevice *s)
1025 struct ni_private *devpriv = dev->private;
1028 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1035 static int pcimio_gpct1_change(struct comedi_device *dev,
1036 struct comedi_subdevice *s)
1038 struct ni_private *devpriv = dev->private;
1041 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1048 static int pcimio_dio_change(struct comedi_device *dev,
1049 struct comedi_subdevice *s)
1051 struct ni_private *devpriv = dev->private;
1054 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1061 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1063 struct ni_private *devpriv = dev->private;
1064 struct mite *mite = devpriv->mite;
1065 resource_size_t daq_phys_addr;
1066 static const int Start_Cal_EEPROM = 0x400;
1067 static const unsigned window_size = 10;
1068 static const int serial_number_eeprom_offset = 0x4;
1069 static const int serial_number_eeprom_length = 0x4;
1070 unsigned old_iodwbsr_bits;
1071 unsigned old_iodwbsr1_bits;
1072 unsigned old_iodwcr1_bits;
1075 /* IO Window 1 needs to be temporarily mapped to read the eeprom */
1076 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
1078 old_iodwbsr_bits = readl(mite->mmio + MITE_IODWBSR);
1079 old_iodwbsr1_bits = readl(mite->mmio + MITE_IODWBSR_1);
1080 old_iodwcr1_bits = readl(mite->mmio + MITE_IODWCR_1);
1081 writel(0x0, mite->mmio + MITE_IODWBSR);
1082 writel(((0x80 | window_size) | daq_phys_addr),
1083 mite->mmio + MITE_IODWBSR_1);
1084 writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1085 writel(0xf, mite->mmio + 0x30);
1087 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1088 for (i = 0; i < serial_number_eeprom_length; ++i) {
1089 char *byte_ptr = (char *)&devpriv->serial_number + i;
1090 *byte_ptr = ni_readb(dev, serial_number_eeprom_offset + i);
1092 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1094 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1095 devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i);
1097 writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1);
1098 writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR);
1099 writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1100 writel(0x0, mite->mmio + 0x30);
1103 static void init_6143(struct comedi_device *dev)
1105 const struct ni_board_struct *board = dev->board_ptr;
1106 struct ni_private *devpriv = dev->private;
1108 /* Disable interrupts */
1109 ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG);
1111 /* Initialise 6143 AI specific bits */
1113 /* Set G0,G1 DMA mode to E series version */
1114 ni_writeb(dev, 0x00, NI6143_MAGIC_REG);
1115 /* Set EOCMode, ADCMode and pipelinedelay */
1116 ni_writeb(dev, 0x80, NI6143_PIPELINE_DELAY_REG);
1118 ni_writeb(dev, 0x00, NI6143_EOC_SET_REG);
1120 /* Set the FIFO half full level */
1121 ni_writel(dev, board->ai_fifo_depth / 2, NI6143_AI_FIFO_FLAG_REG);
1123 /* Strobe Relay disable bit */
1124 devpriv->ai_calib_source_enabled = 0;
1125 ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF,
1126 NI6143_CALIB_CHAN_REG);
1127 ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG);
1130 static void pcimio_detach(struct comedi_device *dev)
1132 struct ni_private *devpriv = dev->private;
1134 mio_common_detach(dev);
1136 free_irq(dev->irq, dev);
1138 mite_free_ring(devpriv->ai_mite_ring);
1139 mite_free_ring(devpriv->ao_mite_ring);
1140 mite_free_ring(devpriv->cdo_mite_ring);
1141 mite_free_ring(devpriv->gpct_mite_ring[0]);
1142 mite_free_ring(devpriv->gpct_mite_ring[1]);
1143 mite_detach(devpriv->mite);
1147 comedi_pci_disable(dev);
1150 static int pcimio_auto_attach(struct comedi_device *dev,
1151 unsigned long context)
1153 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1154 const struct ni_board_struct *board = NULL;
1155 struct ni_private *devpriv;
1159 if (context < ARRAY_SIZE(ni_boards))
1160 board = &ni_boards[context];
1163 dev->board_ptr = board;
1164 dev->board_name = board->name;
1166 ret = comedi_pci_enable(dev);
1170 ret = ni_alloc_private(dev);
1173 devpriv = dev->private;
1175 devpriv->mite = mite_attach(dev, false); /* use win0 */
1179 if (board->reg_type & ni_reg_m_series_mask)
1180 devpriv->is_m_series = 1;
1181 if (board->reg_type & ni_reg_6xxx_mask)
1182 devpriv->is_6xxx = 1;
1183 if (board->reg_type == ni_reg_611x)
1184 devpriv->is_611x = 1;
1185 if (board->reg_type == ni_reg_6143)
1186 devpriv->is_6143 = 1;
1187 if (board->reg_type == ni_reg_622x)
1188 devpriv->is_622x = 1;
1189 if (board->reg_type == ni_reg_625x)
1190 devpriv->is_625x = 1;
1191 if (board->reg_type == ni_reg_628x)
1192 devpriv->is_628x = 1;
1193 if (board->reg_type & ni_reg_67xx_mask)
1194 devpriv->is_67xx = 1;
1195 if (board->reg_type == ni_reg_6711)
1196 devpriv->is_6711 = 1;
1197 if (board->reg_type == ni_reg_6713)
1198 devpriv->is_6713 = 1;
1200 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1201 if (!devpriv->ai_mite_ring)
1203 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1204 if (!devpriv->ao_mite_ring)
1206 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1207 if (!devpriv->cdo_mite_ring)
1209 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1210 if (!devpriv->gpct_mite_ring[0])
1212 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1213 if (!devpriv->gpct_mite_ring[1])
1216 if (devpriv->is_m_series)
1217 m_series_init_eeprom_buffer(dev);
1218 if (devpriv->is_6143)
1223 ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED,
1224 dev->board_name, dev);
1229 ret = ni_E_init(dev, 0, 1);
1233 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1234 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1235 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1236 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1237 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1242 static struct comedi_driver ni_pcimio_driver = {
1243 .driver_name = "ni_pcimio",
1244 .module = THIS_MODULE,
1245 .auto_attach = pcimio_auto_attach,
1246 .detach = pcimio_detach,
1249 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1250 const struct pci_device_id *id)
1252 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1255 static const struct pci_device_id ni_pcimio_pci_table[] = {
1256 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 }, /* 0x1620? */
1257 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1258 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1259 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1260 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1261 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1262 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1263 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1264 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1265 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1266 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1267 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1268 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1269 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1270 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1271 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1272 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1273 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1274 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1275 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1276 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1277 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1278 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1279 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1280 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1281 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1282 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1283 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1284 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1285 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1286 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1287 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1288 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1289 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1290 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1291 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1292 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1293 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1294 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1295 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1296 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1297 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1298 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1299 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1300 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1301 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1302 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1303 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1304 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1305 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1306 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1307 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1308 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1309 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1310 { PCI_VDEVICE(NI, 0x70ad), BOARD_PXI6251 },
1313 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1315 static struct pci_driver ni_pcimio_pci_driver = {
1316 .name = "ni_pcimio",
1317 .id_table = ni_pcimio_pci_table,
1318 .probe = ni_pcimio_pci_probe,
1319 .remove = comedi_pci_auto_unconfig,
1321 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1323 MODULE_AUTHOR("Comedi http://www.comedi.org");
1324 MODULE_DESCRIPTION("Comedi low-level driver");
1325 MODULE_LICENSE("GPL");