2 comedi/drivers/gsc_hpdi.c
3 This is a driver for the General Standards Corporation High
4 Speed Parallel Digital Interface rs485 boards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2003 Coherent Imaging Systems
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
25 * Description: General Standards Corporation High
26 * Speed Parallel Digital Interface rs485 boards
27 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
28 * Status: only receive mode works, transmit not supported
29 * Updated: Thu, 01 Nov 2012 16:17:38 +0000
30 * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
33 * Configuration options:
36 * Manual configuration of supported devices is not supported; they are
37 * configured automatically.
39 * There are some additional hpdi models available from GSC for which
40 * support could be added to this driver.
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/delay.h>
48 #include <linux/interrupt.h>
50 #include "../comedidev.h"
53 #include "comedi_fc.h"
55 static void abort_dma(struct comedi_device *dev, unsigned int channel);
57 #define TIMER_BASE 50 /* 20MHz master clock */
58 #define DMA_BUFFER_SIZE 0x10000
59 #define NUM_DMA_BUFFERS 4
60 #define NUM_DMA_DESCRIPTORS 256
63 FIRMWARE_REV_REG = 0x0,
64 BOARD_CONTROL_REG = 0x4,
65 BOARD_STATUS_REG = 0x8,
66 TX_PROG_ALMOST_REG = 0xc,
67 RX_PROG_ALMOST_REG = 0x10,
70 TX_STATUS_COUNT_REG = 0x1c,
71 TX_LINE_VALID_COUNT_REG = 0x20,
72 TX_LINE_INVALID_COUNT_REG = 0x24,
73 RX_STATUS_COUNT_REG = 0x28,
74 RX_LINE_COUNT_REG = 0x2c,
75 INTERRUPT_CONTROL_REG = 0x30,
76 INTERRUPT_STATUS_REG = 0x34,
77 TX_CLOCK_DIVIDER_REG = 0x38,
78 TX_FIFO_SIZE_REG = 0x40,
79 RX_FIFO_SIZE_REG = 0x44,
80 TX_FIFO_WORDS_REG = 0x48,
81 RX_FIFO_WORDS_REG = 0x4c,
82 INTERRUPT_EDGE_LEVEL_REG = 0x50,
83 INTERRUPT_POLARITY_REG = 0x54,
88 enum firmware_revision_bits {
89 FEATURES_REG_PRESENT_BIT = 0x8000,
92 enum board_control_bits {
93 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
94 TX_FIFO_RESET_BIT = 0x2,
95 RX_FIFO_RESET_BIT = 0x4,
98 DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
99 /* for ch 0, ch 1 can only transmit (when present) */
100 LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
102 CABLE_THROTTLE_ENABLE_BIT = 0x20,
103 TEST_MODE_ENABLE_BIT = 0x80000000,
106 enum board_status_bits {
107 COMMAND_LINE_STATUS_MASK = 0x7f,
108 TX_IN_PROGRESS_BIT = 0x80,
109 TX_NOT_EMPTY_BIT = 0x100,
110 TX_NOT_ALMOST_EMPTY_BIT = 0x200,
111 TX_NOT_ALMOST_FULL_BIT = 0x400,
112 TX_NOT_FULL_BIT = 0x800,
113 RX_NOT_EMPTY_BIT = 0x1000,
114 RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
115 RX_NOT_ALMOST_FULL_BIT = 0x4000,
116 RX_NOT_FULL_BIT = 0x8000,
117 BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
118 BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
119 TX_OVERRUN_BIT = 0x200000,
120 RX_UNDERRUN_BIT = 0x400000,
121 RX_OVERRUN_BIT = 0x800000,
124 static uint32_t almost_full_bits(unsigned int num_words)
126 /* XXX need to add or subtract one? */
127 return (num_words << 16) & 0xff0000;
130 static uint32_t almost_empty_bits(unsigned int num_words)
132 return num_words & 0xffff;
136 FIFO_SIZE_PRESENT_BIT = 0x1,
137 FIFO_WORDS_PRESENT_BIT = 0x2,
138 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
139 GPIO_SUPPORTED_BIT = 0x8,
140 PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
141 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
144 enum interrupt_sources {
145 FRAME_VALID_START_INTR = 0,
146 FRAME_VALID_END_INTR = 1,
147 TX_FIFO_EMPTY_INTR = 8,
148 TX_FIFO_ALMOST_EMPTY_INTR = 9,
149 TX_FIFO_ALMOST_FULL_INTR = 10,
150 TX_FIFO_FULL_INTR = 11,
152 RX_ALMOST_EMPTY_INTR = 13,
153 RX_ALMOST_FULL_INTR = 14,
157 static uint32_t intr_bit(int interrupt_source)
159 return 0x1 << interrupt_source;
162 static unsigned int fifo_size(uint32_t fifo_size_bits)
164 return fifo_size_bits & 0xfffff;
168 const char *name; /* board name */
169 int device_id; /* pci device id */
170 int subdevice_id; /* pci subdevice id */
173 static const struct hpdi_board hpdi_boards[] = {
175 .name = "pci-hpdi32",
176 .device_id = PCI_DEVICE_ID_PLX_9080,
177 .subdevice_id = 0x2400,
181 .name = "pxi-hpdi32",
183 .subdevice_id = 0x2705,
188 struct hpdi_private {
189 /* base addresses (ioremapped) */
190 void __iomem *plx9080_iobase;
191 void __iomem *hpdi_iobase;
192 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
193 /* physical addresses of dma buffers */
194 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
195 /* array of dma descriptors read by plx9080, allocated to get proper
197 struct plx_dma_desc *dma_desc;
198 /* physical address of dma descriptor array */
199 dma_addr_t dma_desc_phys_addr;
200 unsigned int num_dma_descriptors;
201 /* pointer to start of buffers indexed by descriptor */
202 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
203 /* index of the dma descriptor that is currently being used */
204 volatile unsigned int dma_desc_index;
205 unsigned int tx_fifo_size;
206 unsigned int rx_fifo_size;
207 volatile unsigned long dio_count;
208 /* software copies of values written to hpdi registers */
209 volatile uint32_t bits[24];
210 /* number of bytes at which to generate COMEDI_CB_BLOCK events */
211 volatile unsigned int block_size;
214 static void disable_plx_interrupts(struct comedi_device *dev)
216 struct hpdi_private *devpriv = dev->private;
218 writel(0, devpriv->plx9080_iobase + PLX_INTRCS_REG);
221 static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
224 struct hpdi_private *devpriv = dev->private;
226 writel(bits | devpriv->bits[offset / sizeof(uint32_t)],
227 devpriv->hpdi_iobase + offset);
230 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
232 struct hpdi_private *devpriv = dev->private;
233 struct comedi_async *async = dev->read_subdev->async;
234 uint32_t next_transfer_addr;
237 void __iomem *pci_addr_reg;
241 devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
244 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
246 /* loop until we have read all the full buffers */
248 for (next_transfer_addr = readl(pci_addr_reg);
249 (next_transfer_addr <
250 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
252 || next_transfer_addr >=
253 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
254 pci_start_addr) + devpriv->block_size)
255 && j < devpriv->num_dma_descriptors; j++) {
256 /* transfer data from dma buffer to comedi buffer */
257 num_samples = devpriv->block_size / sizeof(uint32_t);
258 if (async->cmd.stop_src == TRIG_COUNT) {
259 if (num_samples > devpriv->dio_count)
260 num_samples = devpriv->dio_count;
261 devpriv->dio_count -= num_samples;
263 cfc_write_array_to_buffer(dev->read_subdev,
264 devpriv->desc_dio_buffer[devpriv->
266 num_samples * sizeof(uint32_t));
267 devpriv->dma_desc_index++;
268 devpriv->dma_desc_index %= devpriv->num_dma_descriptors;
270 /* XXX check for buffer overrun somehow */
273 static irqreturn_t handle_interrupt(int irq, void *d)
275 struct comedi_device *dev = d;
276 struct hpdi_private *devpriv = dev->private;
277 struct comedi_subdevice *s = dev->read_subdev;
278 struct comedi_async *async = s->async;
279 uint32_t hpdi_intr_status, hpdi_board_status;
282 uint8_t dma0_status, dma1_status;
288 plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
289 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
292 hpdi_intr_status = readl(devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
293 hpdi_board_status = readl(devpriv->hpdi_iobase + BOARD_STATUS_REG);
295 if (hpdi_intr_status) {
296 writel(hpdi_intr_status,
297 devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
299 /* spin lock makes sure no one else changes plx dma control reg */
300 spin_lock_irqsave(&dev->spinlock, flags);
301 dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
302 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
303 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
304 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
306 if (dma0_status & PLX_DMA_EN_BIT)
307 drain_dma_buffers(dev, 0);
309 spin_unlock_irqrestore(&dev->spinlock, flags);
311 /* spin lock makes sure no one else changes plx dma control reg */
312 spin_lock_irqsave(&dev->spinlock, flags);
313 dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
314 if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
315 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
316 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
318 spin_unlock_irqrestore(&dev->spinlock, flags);
320 /* clear possible plx9080 interrupt sources */
321 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
322 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
323 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
326 if (hpdi_board_status & RX_OVERRUN_BIT) {
327 comedi_error(dev, "rx fifo overrun");
328 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
331 if (hpdi_board_status & RX_UNDERRUN_BIT) {
332 comedi_error(dev, "rx fifo underrun");
333 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
336 if (devpriv->dio_count == 0)
337 async->events |= COMEDI_CB_EOA;
339 cfc_handle_events(dev, s);
344 static void abort_dma(struct comedi_device *dev, unsigned int channel)
346 struct hpdi_private *devpriv = dev->private;
349 /* spinlock for plx dma control/status reg */
350 spin_lock_irqsave(&dev->spinlock, flags);
352 plx9080_abort_dma(devpriv->plx9080_iobase, channel);
354 spin_unlock_irqrestore(&dev->spinlock, flags);
357 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
359 struct hpdi_private *devpriv = dev->private;
361 hpdi_writel(dev, 0, BOARD_CONTROL_REG);
363 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
370 static int gsc_hpdi_cmd(struct comedi_device *dev,
371 struct comedi_subdevice *s)
373 struct hpdi_private *devpriv = dev->private;
374 struct comedi_async *async = s->async;
375 struct comedi_cmd *cmd = &async->cmd;
382 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
386 devpriv->dma_desc_index = 0;
389 * These register are supposedly unused during chained dma,
390 * but I have found that left over values from last operation
391 * occasionally cause problems with transfer of first dma
392 * block. Initializing them to zero seems to fix the problem.
394 writel(0, devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
395 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
396 writel(0, devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
398 /* give location of first dma descriptor */
399 bits = devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
400 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
401 writel(bits, devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
403 /* enable dma transfer */
404 spin_lock_irqsave(&dev->spinlock, flags);
405 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
406 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
407 spin_unlock_irqrestore(&dev->spinlock, flags);
409 if (cmd->stop_src == TRIG_COUNT)
410 devpriv->dio_count = cmd->stop_arg;
412 devpriv->dio_count = 1;
414 /* clear over/under run status flags */
415 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
416 devpriv->hpdi_iobase + BOARD_STATUS_REG);
418 /* enable interrupts */
419 writel(intr_bit(RX_FULL_INTR),
420 devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
422 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
427 static int gsc_hpdi_cmd_test(struct comedi_device *dev,
428 struct comedi_subdevice *s,
429 struct comedi_cmd *cmd)
437 /* Step 1 : check if triggers are trivially valid */
439 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
440 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
441 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
442 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
443 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
448 /* Step 2a : make sure trigger sources are unique */
450 err |= cfc_check_trigger_is_unique(cmd->stop_src);
452 /* Step 2b : and mutually compatible */
457 /* Step 3: check if arguments are trivially valid */
459 if (!cmd->chanlist_len || !cmd->chanlist) {
460 cmd->chanlist_len = 32;
463 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
465 if (cmd->stop_src == TRIG_COUNT)
466 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
468 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
473 /* step 4: fix up any arguments */
478 /* step 5: complain about special chanlist considerations */
480 for (i = 0; i < cmd->chanlist_len; i++) {
481 if (CR_CHAN(cmd->chanlist[i]) != i) {
482 /* XXX could support 8 or 16 channels */
483 dev_err(dev->class_dev,
484 "chanlist must be ch 0 to 31 in order");
497 /* setup dma descriptors so a link completes every 'len' bytes */
498 static int gsc_hpdi_setup_dma_descriptors(struct comedi_device *dev,
501 struct hpdi_private *devpriv = dev->private;
502 dma_addr_t phys_addr = devpriv->dma_desc_phys_addr;
503 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
504 PLX_XFER_LOCAL_TO_PCI;
505 unsigned int offset = 0;
506 unsigned int idx = 0;
509 if (len > DMA_BUFFER_SIZE)
510 len = DMA_BUFFER_SIZE;
511 len -= len % sizeof(uint32_t);
515 for (i = 0; i < NUM_DMA_DESCRIPTORS && idx < NUM_DMA_BUFFERS; i++) {
516 devpriv->dma_desc[i].pci_start_addr =
517 cpu_to_le32(devpriv->dio_buffer_phys_addr[idx] + offset);
518 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
519 devpriv->dma_desc[i].transfer_size = cpu_to_le32(len);
520 devpriv->dma_desc[i].next = cpu_to_le32((phys_addr +
521 (i + 1) * sizeof(devpriv->dma_desc[0])) | next_bits);
523 devpriv->desc_dio_buffer[i] = devpriv->dio_buffer[idx] +
524 (offset / sizeof(uint32_t));
527 if (len + offset > DMA_BUFFER_SIZE) {
532 devpriv->num_dma_descriptors = i;
533 /* fix last descriptor to point back to first */
534 devpriv->dma_desc[i - 1].next = cpu_to_le32(phys_addr | next_bits);
536 devpriv->block_size = len;
541 static int gsc_hpdi_dio_insn_config(struct comedi_device *dev,
542 struct comedi_subdevice *s,
543 struct comedi_insn *insn,
549 case INSN_CONFIG_BLOCK_SIZE:
550 ret = gsc_hpdi_setup_dma_descriptors(dev, data[1]);
557 ret = comedi_dio_insn_config(dev, s, insn, data, 0xffffffff);
566 static int init_hpdi(struct comedi_device *dev)
568 struct hpdi_private *devpriv = dev->private;
569 uint32_t plx_intcsr_bits;
571 writel(BOARD_RESET_BIT, devpriv->hpdi_iobase + BOARD_CONTROL_REG);
574 writel(almost_empty_bits(32) | almost_full_bits(32),
575 devpriv->hpdi_iobase + RX_PROG_ALMOST_REG);
576 writel(almost_empty_bits(32) | almost_full_bits(32),
577 devpriv->hpdi_iobase + TX_PROG_ALMOST_REG);
579 devpriv->tx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
581 devpriv->rx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
584 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
586 /* enable interrupts */
588 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
590 writel(plx_intcsr_bits, devpriv->plx9080_iobase + PLX_INTRCS_REG);
595 static void init_plx9080(struct comedi_device *dev)
597 struct hpdi_private *devpriv = dev->private;
599 void __iomem *plx_iobase = devpriv->plx9080_iobase;
602 bits = BIGEND_DMA0 | BIGEND_DMA1;
606 writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
608 disable_plx_interrupts(dev);
613 /* configure dma0 mode */
615 /* enable ready input */
616 bits |= PLX_DMA_EN_READYIN_BIT;
617 /* enable dma chaining */
618 bits |= PLX_EN_CHAIN_BIT;
619 /* enable interrupt on dma done
620 * (probably don't need this, since chain never finishes) */
621 bits |= PLX_EN_DMA_DONE_INTR_BIT;
622 /* don't increment local address during transfers
623 * (we are transferring from a fixed fifo register) */
624 bits |= PLX_LOCAL_ADDR_CONST_BIT;
625 /* route dma interrupt to pci bus */
626 bits |= PLX_DMA_INTR_PCI_BIT;
627 /* enable demand mode */
628 bits |= PLX_DEMAND_MODE_BIT;
629 /* enable local burst mode */
630 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
631 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
632 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
635 static const struct hpdi_board *hpdi_find_board(struct pci_dev *pcidev)
639 for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++)
640 if (pcidev->device == hpdi_boards[i].device_id &&
641 pcidev->subsystem_device == hpdi_boards[i].subdevice_id)
642 return &hpdi_boards[i];
646 static int hpdi_auto_attach(struct comedi_device *dev,
647 unsigned long context_unused)
649 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
650 const struct hpdi_board *thisboard;
651 struct hpdi_private *devpriv;
652 struct comedi_subdevice *s;
656 thisboard = hpdi_find_board(pcidev);
658 dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n",
662 dev->board_ptr = thisboard;
663 dev->board_name = thisboard->name;
665 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
669 retval = comedi_pci_enable(dev);
672 pci_set_master(pcidev);
674 devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
675 devpriv->hpdi_iobase = pci_ioremap_bar(pcidev, 2);
676 if (!devpriv->plx9080_iobase || !devpriv->hpdi_iobase) {
677 dev_warn(dev->class_dev, "failed to remap io memory\n");
684 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
685 dev->board_name, dev)) {
686 dev_warn(dev->class_dev,
687 "unable to allocate irq %u\n", pcidev->irq);
690 dev->irq = pcidev->irq;
692 dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
694 /* allocate pci dma buffers */
695 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
696 devpriv->dio_buffer[i] =
697 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
698 &devpriv->dio_buffer_phys_addr[i]);
700 /* allocate dma descriptors */
701 devpriv->dma_desc = pci_alloc_consistent(pcidev,
702 sizeof(struct plx_dma_desc) *
704 &devpriv->dma_desc_phys_addr);
705 if (devpriv->dma_desc_phys_addr & 0xf) {
706 dev_warn(dev->class_dev,
707 " dma descriptors not quad-word aligned (bug)\n");
711 retval = gsc_hpdi_setup_dma_descriptors(dev, 0x1000);
715 retval = comedi_alloc_subdevices(dev, 1);
719 /* Digital I/O subdevice */
720 s = &dev->subdevices[0];
721 dev->read_subdev = s;
722 s->type = COMEDI_SUBD_DIO;
723 s->subdev_flags = SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL |
726 s->len_chanlist = 32;
728 s->range_table = &range_digital;
729 s->insn_config = gsc_hpdi_dio_insn_config;
730 s->do_cmd = gsc_hpdi_cmd;
731 s->do_cmdtest = gsc_hpdi_cmd_test;
732 s->cancel = hpdi_cancel;
734 return init_hpdi(dev);
737 static void hpdi_detach(struct comedi_device *dev)
739 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
740 struct hpdi_private *devpriv = dev->private;
744 free_irq(dev->irq, dev);
746 if (devpriv->plx9080_iobase) {
747 disable_plx_interrupts(dev);
748 iounmap(devpriv->plx9080_iobase);
750 if (devpriv->hpdi_iobase)
751 iounmap(devpriv->hpdi_iobase);
752 /* free pci dma buffers */
753 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
754 if (devpriv->dio_buffer[i])
755 pci_free_consistent(pcidev,
757 devpriv->dio_buffer[i],
759 dio_buffer_phys_addr[i]);
761 /* free dma descriptors */
762 if (devpriv->dma_desc)
763 pci_free_consistent(pcidev,
764 sizeof(struct plx_dma_desc) *
767 devpriv->dma_desc_phys_addr);
769 comedi_pci_disable(dev);
772 static struct comedi_driver gsc_hpdi_driver = {
773 .driver_name = "gsc_hpdi",
774 .module = THIS_MODULE,
775 .auto_attach = hpdi_auto_attach,
776 .detach = hpdi_detach,
779 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
780 const struct pci_device_id *id)
782 return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
785 static const struct pci_device_id gsc_hpdi_pci_table[] = {
786 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
790 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
792 static struct pci_driver gsc_hpdi_pci_driver = {
794 .id_table = gsc_hpdi_pci_table,
795 .probe = gsc_hpdi_pci_probe,
796 .remove = comedi_pci_auto_unconfig,
798 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
800 MODULE_AUTHOR("Comedi http://www.comedi.org");
801 MODULE_DESCRIPTION("Comedi low-level driver");
802 MODULE_LICENSE("GPL");