3 comedi/drivers/aio_aio12_8.c
5 Driver for Access I/O Products PC-104 AIO12-8 Analog I/O Board
6 Copyright (C) 2006 C&C Technologies, Inc.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
22 Description: Access I/O Products PC-104 AIO12-8 Analog I/O Board
23 Author: Pablo Mejia <pablo.mejia@cctechnol.com>
24 Devices: [Access I/O] PC-104 AIO12-8 (aio_aio12_8)
25 [Access I/O] PC-104 AI12-8 (aio_ai12_8)
26 [Access I/O] PC-104 AO12-8 (aio_ao12_8)
29 Configuration Options:
30 [0] - I/O port base address
34 Only synchronous operations are supported.
38 #include <linux/module.h>
39 #include "../comedidev.h"
45 #define AIO12_8_STATUS_REG 0x00
46 #define AIO12_8_STATUS_ADC_EOC BIT(7)
47 #define AIO12_8_STATUS_PORT_C_COS BIT(6)
48 #define AIO12_8_STATUS_IRQ_ENA BIT(2)
49 #define AIO12_8_INTERRUPT_REG 0x01
50 #define AIO12_8_INTERRUPT_ADC BIT(7)
51 #define AIO12_8_INTERRUPT_COS BIT(6)
52 #define AIO12_8_INTERRUPT_COUNTER1 BIT(5)
53 #define AIO12_8_INTERRUPT_PORT_C3 BIT(4)
54 #define AIO12_8_INTERRUPT_PORT_C0 BIT(3)
55 #define AIO12_8_INTERRUPT_ENA BIT(2)
56 #define AIO12_8_ADC_REG 0x02
57 #define AIO12_8_ADC_MODE(x) (((x) & 0x3) << 6)
58 #define AIO12_8_ADC_MODE_NORMAL AIO12_8_ADC_MODE(0)
59 #define AIO12_8_ADC_MODE_INT_CLK AIO12_8_ADC_MODE(1)
60 #define AIO12_8_ADC_MODE_STANDBY AIO12_8_ADC_MODE(2)
61 #define AIO12_8_ADC_MODE_POWERDOWN AIO12_8_ADC_MODE(3)
62 #define AIO12_8_ADC_ACQ(x) (((x) & 0x1) << 5)
63 #define AIO12_8_ADC_ACQ_3USEC AIO12_8_ADC_ACQ(0)
64 #define AIO12_8_ADC_ACQ_PROGRAM AIO12_8_ADC_ACQ(1)
65 #define AIO12_8_ADC_RANGE(x) ((x) << 3)
66 #define AIO12_8_ADC_CHAN(x) ((x) << 0)
67 #define AIO12_8_DAC_REG(x) (0x04 + (x) * 2)
68 #define AIO12_8_8254_BASE_REG 0x0c
69 #define AIO12_8_8255_BASE_REG 0x10
70 #define AIO12_8_DIO_CONTROL_REG 0x14
71 #define AIO12_8_DIO_CONTROL_TST BIT(0)
72 #define AIO12_8_ADC_TRIGGER_REG 0x15
73 #define AIO12_8_ADC_TRIGGER_RANGE(x) ((x) << 3)
74 #define AIO12_8_ADC_TRIGGER_CHAN(x) ((x) << 0)
75 #define AIO12_8_TRIGGER_REG 0x16
76 #define AIO12_8_TRIGGER_ADTRIG BIT(1)
77 #define AIO12_8_TRIGGER_DACTRIG BIT(0)
78 #define AIO12_8_COS_REG 0x17
79 #define AIO12_8_DAC_ENABLE_REG 0x18
80 #define AIO12_8_DAC_ENABLE_REF_ENA BIT(0)
82 struct aio12_8_boardtype {
88 static const struct aio12_8_boardtype board_types[] = {
90 .name = "aio_aio12_8",
102 static int aio_aio12_8_ai_eoc(struct comedi_device *dev,
103 struct comedi_subdevice *s,
104 struct comedi_insn *insn,
105 unsigned long context)
109 status = inb(dev->iobase + AIO12_8_STATUS_REG);
110 if (status & AIO12_8_STATUS_ADC_EOC)
115 static int aio_aio12_8_ai_read(struct comedi_device *dev,
116 struct comedi_subdevice *s,
117 struct comedi_insn *insn, unsigned int *data)
119 unsigned int chan = CR_CHAN(insn->chanspec);
120 unsigned int range = CR_RANGE(insn->chanspec);
121 unsigned char control;
126 * Setup the control byte for internal 2MHz clock, 3uS conversion,
127 * at the desired range of the requested channel.
129 control = AIO12_8_ADC_MODE_NORMAL | AIO12_8_ADC_ACQ_3USEC |
130 AIO12_8_ADC_RANGE(range) | AIO12_8_ADC_CHAN(chan);
132 /* Read status to clear EOC latch */
133 inb(dev->iobase + AIO12_8_STATUS_REG);
135 for (n = 0; n < insn->n; n++) {
136 /* Setup and start conversion */
137 outb(control, dev->iobase + AIO12_8_ADC_REG);
139 /* Wait for conversion to complete */
140 ret = comedi_timeout(dev, s, insn, aio_aio12_8_ai_eoc, 0);
144 data[n] = inw(dev->iobase + AIO12_8_ADC_REG) & s->maxdata;
150 static int aio_aio12_8_ao_insn_write(struct comedi_device *dev,
151 struct comedi_subdevice *s,
152 struct comedi_insn *insn,
155 unsigned int chan = CR_CHAN(insn->chanspec);
156 unsigned int val = s->readback[chan];
160 outb(AIO12_8_DAC_ENABLE_REF_ENA, dev->iobase + AIO12_8_DAC_ENABLE_REG);
162 for (i = 0; i < insn->n; i++) {
164 outw(val, dev->iobase + AIO12_8_DAC_REG(chan));
166 s->readback[chan] = val;
171 static const struct comedi_lrange range_aio_aio12_8 = {
180 static int aio_aio12_8_attach(struct comedi_device *dev,
181 struct comedi_devconfig *it)
183 const struct aio12_8_boardtype *board = dev->board_ptr;
184 struct comedi_subdevice *s;
187 ret = comedi_request_region(dev, it->options[0], 32);
191 ret = comedi_alloc_subdevices(dev, 4);
195 s = &dev->subdevices[0];
196 if (board->ai_nchan) {
197 /* Analog input subdevice */
198 s->type = COMEDI_SUBD_AI;
199 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF;
200 s->n_chan = board->ai_nchan;
202 s->range_table = &range_aio_aio12_8;
203 s->insn_read = aio_aio12_8_ai_read;
205 s->type = COMEDI_SUBD_UNUSED;
208 s = &dev->subdevices[1];
209 if (board->ao_nchan) {
210 /* Analog output subdevice */
211 s->type = COMEDI_SUBD_AO;
212 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_DIFF;
215 s->range_table = &range_aio_aio12_8;
216 s->insn_write = aio_aio12_8_ao_insn_write;
218 ret = comedi_alloc_subdev_readback(s);
222 s->type = COMEDI_SUBD_UNUSED;
225 s = &dev->subdevices[2];
226 /* 8255 Digital i/o subdevice */
227 ret = subdev_8255_init(dev, s, NULL, AIO12_8_8255_BASE_REG);
231 s = &dev->subdevices[3];
232 /* 8254 counter/timer subdevice */
233 s->type = COMEDI_SUBD_UNUSED;
238 static struct comedi_driver aio_aio12_8_driver = {
239 .driver_name = "aio_aio12_8",
240 .module = THIS_MODULE,
241 .attach = aio_aio12_8_attach,
242 .detach = comedi_legacy_detach,
243 .board_name = &board_types[0].name,
244 .num_names = ARRAY_SIZE(board_types),
245 .offset = sizeof(struct aio12_8_boardtype),
247 module_comedi_driver(aio_aio12_8_driver);
249 MODULE_AUTHOR("Comedi http://www.comedi.org");
250 MODULE_DESCRIPTION("Comedi low-level driver");
251 MODULE_LICENSE("GPL");