2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 /* cpp contortions to concatenate w/arg prescan */
22 #define _PADLINE(line) pad ## line
23 #define _XSTR(line) _PADLINE(line)
24 #define PAD _XSTR(__LINE__)
27 /* enumeration in SB is based on the premise that cores are contiguos in the
30 #define SB_BUS_SIZE 0x10000 /* Each bus gets 64Kbytes for cores */
31 #define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE)
32 #define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE) /* Max cores per bus */
35 * Sonics Configuration Space Registers.
37 #define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
38 #define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
40 #define SBIPSFLAG 0x08
41 #define SBTPSFLAG 0x18
42 #define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
43 #define SBTMERRLOG 0x50 /* sonics >= 2.3 */
44 #define SBADMATCH3 0x60
45 #define SBADMATCH2 0x68
46 #define SBADMATCH1 0x70
47 #define SBIMSTATE 0x90
49 #define SBTMSTATELOW 0x98
50 #define SBTMSTATEHIGH 0x9c
52 #define SBIMCONFIGLOW 0xa8
53 #define SBIMCONFIGHIGH 0xac
54 #define SBADMATCH0 0xb0
55 #define SBTMCONFIGLOW 0xb8
56 #define SBTMCONFIGHIGH 0xbc
57 #define SBBCONFIG 0xc0
59 #define SBACTCNFG 0xd8
64 /* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
65 * a few registers *below* that line. I think it would be very confusing to try
66 * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
69 #define SBIMERRLOGA 0xea8
70 #define SBIMERRLOG 0xeb0
71 #define SBTMPORTCONNID0 0xed8
72 #define SBTMPORTLOCK0 0xef8
74 #ifndef _LANGUAGE_ASSEMBLY
76 typedef volatile struct _sbconfig {
78 uint32 sbipsflag; /* initiator port ocp slave flag */
80 uint32 sbtpsflag; /* target port ocp slave flag */
82 uint32 sbtmerrloga; /* (sonics >= 2.3) */
84 uint32 sbtmerrlog; /* (sonics >= 2.3) */
86 uint32 sbadmatch3; /* address match3 */
88 uint32 sbadmatch2; /* address match2 */
90 uint32 sbadmatch1; /* address match1 */
92 uint32 sbimstate; /* initiator agent state */
93 uint32 sbintvec; /* interrupt mask */
94 uint32 sbtmstatelow; /* target state */
95 uint32 sbtmstatehigh; /* target state */
96 uint32 sbbwa0; /* bandwidth allocation table0 */
98 uint32 sbimconfiglow; /* initiator configuration */
99 uint32 sbimconfighigh; /* initiator configuration */
100 uint32 sbadmatch0; /* address match0 */
102 uint32 sbtmconfiglow; /* target configuration */
103 uint32 sbtmconfighigh; /* target configuration */
104 uint32 sbbconfig; /* broadcast configuration */
106 uint32 sbbstate; /* broadcast state */
108 uint32 sbactcnfg; /* activate configuration */
110 uint32 sbflagst; /* current sbflags */
112 uint32 sbidlow; /* identification */
113 uint32 sbidhigh; /* identification */
116 #endif /* _LANGUAGE_ASSEMBLY */
119 #define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
120 #define SBIPS_INT1_SHIFT 0
121 #define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
122 #define SBIPS_INT2_SHIFT 8
123 #define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
124 #define SBIPS_INT3_SHIFT 16
125 #define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
126 #define SBIPS_INT4_SHIFT 24
129 #define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
130 #define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
133 #define SBTMEL_CM 0x00000007 /* command */
134 #define SBTMEL_CI 0x0000ff00 /* connection id */
135 #define SBTMEL_EC 0x0f000000 /* error code */
136 #define SBTMEL_ME 0x80000000 /* multiple error */
139 #define SBIM_PC 0xf /* pipecount */
140 #define SBIM_AP_MASK 0x30 /* arbitration policy */
141 #define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
142 #define SBIM_AP_TS 0x10 /* use timesliaces only */
143 #define SBIM_AP_TK 0x20 /* use token only */
144 #define SBIM_AP_RSV 0x30 /* reserved */
145 #define SBIM_IBE 0x20000 /* inbanderror */
146 #define SBIM_TO 0x40000 /* timeout */
147 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
148 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
151 #define SBTML_RESET 0x0001 /* reset */
152 #define SBTML_REJ_MASK 0x0006 /* reject field */
153 #define SBTML_REJ 0x0002 /* reject */
154 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
156 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
159 #define SBTMH_SERR 0x0001 /* serror */
160 #define SBTMH_INT 0x0002 /* interrupt */
161 #define SBTMH_BUSY 0x0004 /* busy */
162 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
164 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
167 #define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
168 #define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
169 #define SBBWA_TAB1_SHIFT 16
172 #define SBIMCL_STO_MASK 0x7 /* service timeout */
173 #define SBIMCL_RTO_MASK 0x70 /* request timeout */
174 #define SBIMCL_RTO_SHIFT 4
175 #define SBIMCL_CID_MASK 0xff0000 /* connection id */
176 #define SBIMCL_CID_SHIFT 16
179 #define SBIMCH_IEM_MASK 0xc /* inband error mode */
180 #define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
181 #define SBIMCH_TEM_SHIFT 4
182 #define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
183 #define SBIMCH_BEM_SHIFT 6
186 #define SBAM_TYPE_MASK 0x3 /* address type */
187 #define SBAM_AD64 0x4 /* reserved */
188 #define SBAM_ADINT0_MASK 0xf8 /* type0 size */
189 #define SBAM_ADINT0_SHIFT 3
190 #define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
191 #define SBAM_ADINT1_SHIFT 3
192 #define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
193 #define SBAM_ADINT2_SHIFT 3
194 #define SBAM_ADEN 0x400 /* enable */
195 #define SBAM_ADNEG 0x800 /* negative decode */
196 #define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
197 #define SBAM_BASE0_SHIFT 8
198 #define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
199 #define SBAM_BASE1_SHIFT 12
200 #define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
201 #define SBAM_BASE2_SHIFT 16
204 #define SBTMCL_CD_MASK 0xff /* clock divide */
205 #define SBTMCL_CO_MASK 0xf800 /* clock offset */
206 #define SBTMCL_CO_SHIFT 11
207 #define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
208 #define SBTMCL_IF_SHIFT 18
209 #define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
210 #define SBTMCL_IM_SHIFT 24
213 #define SBTMCH_BM_MASK 0x3 /* busy mode */
214 #define SBTMCH_RM_MASK 0x3 /* retry mode */
215 #define SBTMCH_RM_SHIFT 2
216 #define SBTMCH_SM_MASK 0x30 /* stop mode */
217 #define SBTMCH_SM_SHIFT 4
218 #define SBTMCH_EM_MASK 0x300 /* sb error mode */
219 #define SBTMCH_EM_SHIFT 8
220 #define SBTMCH_IM_MASK 0xc00 /* int mode */
221 #define SBTMCH_IM_SHIFT 10
224 #define SBBC_LAT_MASK 0x3 /* sb latency */
225 #define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
226 #define SBBC_MAX0_SHIFT 16
227 #define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
228 #define SBBC_MAX1_SHIFT 20
231 #define SBBS_SRD 0x1 /* st reg disable */
232 #define SBBS_HRD 0x2 /* hold reg disable */
235 #define SBIDL_CS_MASK 0x3 /* config space */
236 #define SBIDL_AR_MASK 0x38 /* # address ranges supported */
237 #define SBIDL_AR_SHIFT 3
238 #define SBIDL_SYNCH 0x40 /* sync */
239 #define SBIDL_INIT 0x80 /* initiator */
240 #define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
241 #define SBIDL_MINLAT_SHIFT 8
242 #define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
243 #define SBIDL_MAXLAT_SHIFT 12
244 #define SBIDL_FIRST 0x10000 /* this initiator is first */
245 #define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
246 #define SBIDL_CW_SHIFT 18
247 #define SBIDL_TP_MASK 0xf00000 /* target ports */
248 #define SBIDL_TP_SHIFT 20
249 #define SBIDL_IP_MASK 0xf000000 /* initiator ports */
250 #define SBIDL_IP_SHIFT 24
251 #define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
252 #define SBIDL_RV_SHIFT 28
253 #define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
254 #define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
257 #define SBIDH_RC_MASK 0x000f /* revision code */
258 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
259 #define SBIDH_RCE_SHIFT 8
260 #define SBCOREREV(sbidh) \
261 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
262 #define SBIDH_CC_MASK 0x8ff0 /* core code */
263 #define SBIDH_CC_SHIFT 4
264 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
265 #define SBIDH_VC_SHIFT 16
267 #define SB_COMMIT 0xfd8 /* update buffered registers value */
270 #define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
272 #endif /* _SBCONFIG_H */