2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _bcmsrom_tbl_h_
18 #define _bcmsrom_tbl_h_
31 #define SRFL_MORE 1 /* value continues as described by the next entry */
32 #define SRFL_NOFFS 2 /* value bits can't be all one's */
33 #define SRFL_PRHEX 4 /* value is in hexdecimal format */
34 #define SRFL_PRSIGN 8 /* value is in signed decimal format */
35 #define SRFL_CCODE 0x10 /* value is in country code format */
36 #define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
37 #define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
38 #define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */
41 * - Ethernet address spans across 3 consective words
44 * - Add multiple entries next to each other if a value spans across multiple words
45 * (even multiple fields in the same word) with each entry except the last having
46 * it's SRFL_MORE bit set.
47 * - Ethernet address entry does not follow above rule and must not have SRFL_MORE
48 * bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
49 * - The last entry's name field must be NULL to indicate the end of the table. Other
50 * entries must have non-NULL name.
53 static const sromvar_t pci_sromvars[] = {
54 {"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff},
55 {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
56 {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
57 {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
58 {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
59 {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
60 {"", 0, 0, SROM_BFL2, 0xffff},
61 {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
62 {"", 0, 0, SROM3_BFL2, 0xffff},
63 {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff},
64 {"", 0, 0, SROM4_BFL1, 0xffff},
65 {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff},
66 {"", 0, 0, SROM5_BFL1, 0xffff},
67 {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff},
68 {"", 0, 0, SROM8_BFL1, 0xffff},
69 {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff},
70 {"", 0, 0, SROM4_BFL3, 0xffff},
71 {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff},
72 {"", 0, 0, SROM5_BFL3, 0xffff},
73 {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff},
74 {"", 0, 0, SROM8_BFL3, 0xffff},
75 {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
76 {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
77 {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
78 {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
79 {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
80 {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff},
81 {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
82 {"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
83 {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
84 {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
85 {"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff},
86 {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
87 {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
88 {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
89 {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
90 {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
91 {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
92 {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
93 {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
94 {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
95 {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
96 {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
97 {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
98 {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
99 {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
100 {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
101 {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
102 {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
103 {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
104 {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
105 {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
106 {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
107 {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
108 {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
109 {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
110 {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
111 {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
112 {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
113 {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
114 {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
115 {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
116 {"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff},
117 {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
118 {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
119 {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00},
120 {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
121 {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
122 {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
123 {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
124 {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
125 {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
126 {"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff},
127 {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00},
128 {"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff},
129 {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00},
130 {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
131 {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
132 {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
133 {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
134 {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
135 {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
136 {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
137 {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
138 {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
139 {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
140 {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
141 {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
142 {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
143 {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
144 {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
145 {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
146 {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
147 {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
148 {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
149 {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
150 {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
151 {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
152 {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
153 {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
154 {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
155 {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
156 {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
157 {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
158 {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
159 {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
160 {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
161 {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
162 {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
163 {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
164 {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
165 {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
166 {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
167 {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
168 {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
169 {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
170 {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
171 {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
172 {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
173 {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
174 {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
175 {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
176 {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
177 {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00},
178 {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
179 {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
180 {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
181 {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
182 {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
183 {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
184 {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
185 {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
186 {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
187 {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
188 {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
189 {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
190 {"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
191 {"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
192 {"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
193 {"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
194 {"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
195 {"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
196 {"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
197 {"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
198 {"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
199 {"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
200 {"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00},
201 {"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
202 {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
203 {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
204 {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
205 {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
206 {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
207 {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
208 {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
209 {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
210 {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
211 {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
212 {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
213 {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
214 {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
215 {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
216 {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
217 {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
219 {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
220 {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
221 {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
222 {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
223 {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
224 {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
225 {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
226 {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
227 {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
228 {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
229 {"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff},
230 {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff},
231 {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff},
232 {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff},
233 {"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
234 {"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
235 {"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
237 {"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
238 {"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
240 {"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
242 {"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
243 {"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
244 {"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
246 {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
247 {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
248 {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
249 {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
250 {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
251 {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
252 {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
253 {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
254 {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
255 {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
256 {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
257 {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
258 {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
259 {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
260 {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
261 {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
262 {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
263 {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
264 {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
265 {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
266 {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
267 {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
268 {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
269 {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
270 {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
271 {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
272 {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
273 {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
274 {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
275 {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
276 {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
277 {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
278 {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
279 {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
280 {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
281 {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
282 {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
283 {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
284 {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
285 {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
286 {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
287 {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
288 {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
289 {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
290 {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
291 {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
292 {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
293 {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
294 {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
295 {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
296 {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
297 {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
298 {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
299 {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
300 {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
301 {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
302 {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
303 {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
304 {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
305 {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
306 {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
307 {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
308 {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
309 {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
310 {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
311 {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
312 {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
313 {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
314 {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
315 {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
316 {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
317 {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
318 {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
319 {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
320 {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
321 {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
322 {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
323 {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
324 {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
325 {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
326 {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
327 {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
328 {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
329 {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
330 {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
331 {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
332 {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
333 {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
334 {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
335 {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
337 /* power per rate from sromrev 9 */
338 {"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
339 {"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
340 {"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20,
342 {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
343 {"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL,
345 {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
346 {"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20,
348 {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
349 {"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL,
351 {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
352 {"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20,
354 {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
355 {"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL,
357 {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
358 {"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20,
360 {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
361 {"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL,
363 {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
364 {"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
365 {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
366 {"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
367 {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
368 {"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
369 {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
370 {"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
371 {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
372 {"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL,
374 {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
375 {"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
376 {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
377 {"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
378 {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
379 {"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL,
381 {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
382 {"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
383 {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
384 {"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
385 {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
386 {"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL,
388 {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
389 {"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
390 {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
391 {"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
392 {"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
397 static const sromvar_t perpath_pci_sromvars[] = {
398 {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
399 {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
400 {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
401 {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
402 {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
403 {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
404 {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
405 {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
406 {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
407 {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
408 {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
409 {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
410 {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
411 {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
412 {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
413 {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
414 {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
415 {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
416 {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
417 {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
418 {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
419 {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
420 {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
421 {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
422 {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
423 {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
424 {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
425 {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
426 {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
427 {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
428 {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
429 {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
430 {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
431 {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
432 {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
433 {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
434 {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
435 {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
436 {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
437 {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
441 #if !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP))
442 #define PHY_TYPE_N 4 /* N-Phy value */
443 #define PHY_TYPE_LP 5 /* LP-Phy value */
444 #endif /* !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) */
445 #if !defined(PHY_TYPE_NULL)
446 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */
447 #endif /* !defined(PHY_TYPE_NULL) */
456 static const pavars_t pavars[] = {
458 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
459 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
460 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 0,
461 "pa5glw0a0 pa5glw1a0 pa5glw2a0"},
462 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 1,
463 "pa5glw0a1 pa5glw1a1 pa5glw2a1"},
464 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
465 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
466 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 0,
467 "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
468 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 1,
469 "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
471 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_2G, 0, "pa0b0 pa0b1 pa0b2"},
472 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GL, 0, "pa1lob0 pa1lob1 pa1lob2"},
473 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GM, 0, "pa1b0 pa1b1 pa1b2"},
474 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GH, 0, "pa1hib0 pa1hib1 pa1hib2"},
475 {PHY_TYPE_NULL, 0, 0, ""}
484 static const povars_t povars[] = {
486 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G,
487 "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 "
488 "mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"},
489 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL,
490 "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 "
491 "mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"},
492 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM,
493 "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 "
494 "mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"},
495 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH,
496 "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 "
497 "mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"},
498 {PHY_TYPE_NULL, 0, ""}
502 uint8 tag; /* Broadcom subtag name */
503 uint8 len; /* Length field of the tuple, note that it includes the
504 * subtag name (1 byte): 1 + tuple content length
509 #define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */
510 #define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */
511 #define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */
512 #define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */
514 static const cis_tuple_t cis_hnbuvars[] = {
515 {OTP_RAW1, 0, ""}, /* special case */
516 {OTP_VERS_1, 0, "smanf sproductname"}, /* special case (non BRCM tuple) */
517 {OTP_MANFID, 4, "2manfid 2prodid"}, /* special case (non BRCM tuple) */
518 {HNBU_SROMREV, 2, "1sromrev"},
519 /* NOTE: subdevid is also written to boardtype.
520 * Need to write HNBU_BOARDTYPE to change it if it is different.
522 {HNBU_CHIPID, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"},
523 {HNBU_BOARDREV, 3, "2boardrev"},
524 {HNBU_PAPARMS, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"},
525 {HNBU_AA, 3, "1aa2g 1aa5g"},
526 {HNBU_AA, 3, "1aa0 1aa1"}, /* backward compatibility */
527 {HNBU_AG, 5, "1ag0 1ag1 1ag2 1ag3"},
528 {HNBU_BOARDFLAGS, 9, "4boardflags 4boardflags2"},
529 {HNBU_LEDS, 5, "1ledbh0 1ledbh1 1ledbh2 1ledbh3"},
530 {HNBU_CCODE, 4, "2ccode 1cctl"},
531 {HNBU_CCKPO, 3, "2cckpo"},
532 {HNBU_OFDMPO, 5, "4ofdmpo"},
533 {HNBU_RDLID, 3, "2rdlid"},
534 {HNBU_RSSISMBXA2G, 3, "0rssismf2g 0rssismc2g 0rssisav2g 0bxa2g"}, /* special case */
535 {HNBU_RSSISMBXA5G, 3, "0rssismf5g 0rssismc5g 0rssisav5g 0bxa5g"}, /* special case */
536 {HNBU_XTALFREQ, 5, "4xtalfreq"},
537 {HNBU_TRI2G, 2, "1tri2g"},
538 {HNBU_TRI5G, 4, "1tri5gl 1tri5g 1tri5gh"},
539 {HNBU_RXPO2G, 2, "1rxpo2g"},
540 {HNBU_RXPO5G, 2, "1rxpo5g"},
541 {HNBU_BOARDNUM, 3, "2boardnum"},
542 {HNBU_MACADDR, 7, "6macaddr"}, /* special case */
543 {HNBU_RDLSN, 3, "2rdlsn"},
544 {HNBU_BOARDTYPE, 3, "2boardtype"},
545 {HNBU_LEDDC, 3, "2leddc"},
546 {HNBU_RDLRNDIS, 2, "1rdlndis"},
547 {HNBU_CHAINSWITCH, 5, "1txchain 1rxchain 2antswitch"},
548 {HNBU_REGREV, 2, "1regrev"},
549 {HNBU_FEM, 5, "0antswctl2g, 0triso2g, 0pdetrange2g, 0extpagain2g, 0tssipos2g" "0antswctl5g, 0triso5g, 0pdetrange5g, 0extpagain5g, 0tssipos5g"}, /* special case */
550 {HNBU_PAPARMS_C0, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 "
551 "2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 "
552 "2pa5gw1a0 2pa5gw2a0 2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 "
553 "2pa5ghw1a0 2pa5ghw2a0"},
554 {HNBU_PAPARMS_C1, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 "
555 "2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 "
556 "2pa5gw1a1 2pa5gw2a1 2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 "
557 "2pa5ghw1a1 2pa5ghw2a1"},
558 {HNBU_PO_CCKOFDM, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo "
560 {HNBU_PO_MCS2G, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 "
561 "2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"},
562 {HNBU_PO_MCS5GM, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 "
563 "2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"},
564 {HNBU_PO_MCS5GLH, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 "
565 "2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 "
566 "2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 "
567 "2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"},
568 {HNBU_CCKFILTTYPE, 2, "1cckdigfilttype"},
569 {HNBU_PO_CDD, 3, "2cddpo"},
570 {HNBU_PO_STBC, 3, "2stbcpo"},
571 {HNBU_PO_40M, 3, "2bw40po"},
572 {HNBU_PO_40MDUP, 3, "2bwduppo"},
573 {HNBU_RDLRWU, 2, "1rdlrwu"},
574 {HNBU_WPS, 3, "1wpsgpio 1wpsled"},
575 {HNBU_USBFS, 2, "1usbfs"},
576 {HNBU_CUSTOM1, 5, "4customvar1"},
577 {OTP_RAW, 0, ""}, /* special case */
578 {HNBU_OFDMPO5G, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"},
579 {HNBU_USBEPNUM, 3, "2usbepnum"},
583 #endif /* _bcmsrom_tbl_h_ */