drivers/spi/spi_s3c64xx.c

   1 /* linux/drivers/spi/spi_s3c64xx.c
   2  *
   3  * Copyright (C) 2009 Samsung Electronics Ltd.
   4  *      Jaswinder Singh <jassi.brar@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/module.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/spi/spi.h>
  29
  30 #include <mach/dma.h>
  31 #include <plat/s3c64xx-spi.h>
  32
  33 /* Registers and bit-fields */
  34
  35 #define S3C64XX_SPI_CH_CFG              0x00
  36 #define S3C64XX_SPI_CLK_CFG             0x04
  37 #define S3C64XX_SPI_MODE_CFG    0x08
  38 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  39 #define S3C64XX_SPI_INT_EN              0x10
  40 #define S3C64XX_SPI_STATUS              0x14
  41 #define S3C64XX_SPI_TX_DATA             0x18
  42 #define S3C64XX_SPI_RX_DATA             0x1C
  43 #define S3C64XX_SPI_PACKET_CNT  0x20
  44 #define S3C64XX_SPI_PENDING_CLR 0x24
  45 #define S3C64XX_SPI_SWAP_CFG    0x28
  46 #define S3C64XX_SPI_FB_CLK              0x2C
  47
  48 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  49 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  50 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  51 #define S3C64XX_SPI_CPOL_L              (1<<3)
  52 #define S3C64XX_SPI_CPHA_B              (1<<2)
  53 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  54 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  55
  56 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  57 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  58 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  59 #define S3C64XX_SPI_PSR_MASK            0xff
  60
  61 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  62 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  63 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  64 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  65 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  66 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  67 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  68 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  69 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  70 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  71 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  72
  73 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  74 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  75
  76 #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
  77
  78 #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
  79                                         (c)->regs + S3C64XX_SPI_SLAVE_SEL)
  80
  81 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  88
  89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  93 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  94 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  95
  96 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  97
  98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
  99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 102 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 103
 104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 105 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 106 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 107 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 109 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 110 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 111 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 112
 113 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 114
 115 #define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
 116                                         (((i)->fifo_lvl_mask + 1))) \
 117                                         ? 1 : 0)
 118
 119 #define S3C64XX_SPI_ST_TX_DONE(v, i) ((((v) >> (i)->rx_lvl_offset) & \
 120                                         (((i)->fifo_lvl_mask + 1) << 1)) \
 121                                         ? 1 : 0)
 122 #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
 123 #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
 124
 125 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 126 #define S3C64XX_SPI_TRAILCNT_OFF        19
 127
 128 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 129
 130 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 131
 132 #define SUSPND    (1<<0)
 133 #define SPIBUSY   (1<<1)
 134 #define RXBUSY    (1<<2)
 135 #define TXBUSY    (1<<3)
 136
 137 /**
 138  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 139  * @clk: Pointer to the spi clock.
 140  * @src_clk: Pointer to the clock used to generate SPI signals.
 141  * @master: Pointer to the SPI Protocol master.
 142  * @workqueue: Work queue for the SPI xfer requests.
 143  * @cntrlr_info: Platform specific data for the controller this driver manages.
 144  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 145  * @work: Work
 146  * @queue: To log SPI xfer requests.
 147  * @lock: Controller specific lock.
 148  * @state: Set of FLAGS to indicate status.
 149  * @rx_dmach: Controller's DMA channel for Rx.
 150  * @tx_dmach: Controller's DMA channel for Tx.
 151  * @sfr_start: BUS address of SPI controller regs.
 152  * @regs: Pointer to ioremap'ed controller registers.
 153  * @xfer_completion: To indicate completion of xfer task.
 154  * @cur_mode: Stores the active configuration of the controller.
 155  * @cur_bpw: Stores the active bits per word settings.
 156  * @cur_speed: Stores the active xfer clock speed.
 157  */
 158 struct s3c64xx_spi_driver_data {
 159         void __iomem                    *regs;
 160         struct clk                      *clk;
 161         struct clk                      *src_clk;
 162         struct platform_device          *pdev;
 163         struct spi_master               *master;
 164         struct workqueue_struct         *workqueue;
 165         struct s3c64xx_spi_info  *cntrlr_info;
 166         struct spi_device               *tgl_spi;
 167         struct work_struct              work;
 168         struct list_head                queue;
 169         spinlock_t                      lock;
 170         enum dma_ch                     rx_dmach;
 171         enum dma_ch                     tx_dmach;
 172         unsigned long                   sfr_start;
 173         struct completion               xfer_completion;
 174         unsigned                        state;
 175         unsigned                        cur_mode, cur_bpw;
 176         unsigned                        cur_speed;
 177 };
 178
 179 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 180         .name = "samsung-spi-dma",
 181 };
 182
 183 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 184 {
 185         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 186         void __iomem *regs = sdd->regs;
 187         unsigned long loops;
 188         u32 val;
 189
 190         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 191
 192         val = readl(regs + S3C64XX_SPI_CH_CFG);
 193         val |= S3C64XX_SPI_CH_SW_RST;
 194         val &= ~S3C64XX_SPI_CH_HS_EN;
 195         writel(val, regs + S3C64XX_SPI_CH_CFG);
 196
 197         /* Flush TxFIFO*/
 198         loops = msecs_to_loops(1);
 199         do {
 200                 val = readl(regs + S3C64XX_SPI_STATUS);
 201         } while (TX_FIFO_LVL(val, sci) && loops--);
 202
 203         /* Flush RxFIFO*/
 204         loops = msecs_to_loops(1);
 205         do {
 206                 val = readl(regs + S3C64XX_SPI_STATUS);
 207                 if (RX_FIFO_LVL(val, sci))
 208                         readl(regs + S3C64XX_SPI_RX_DATA);
 209                 else
 210                         break;
 211         } while (loops--);
 212
 213         val = readl(regs + S3C64XX_SPI_CH_CFG);
 214         val &= ~S3C64XX_SPI_CH_SW_RST;
 215         writel(val, regs + S3C64XX_SPI_CH_CFG);
 216
 217         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 218         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 219         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 220
 221         val = readl(regs + S3C64XX_SPI_CH_CFG);
 222         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 223         writel(val, regs + S3C64XX_SPI_CH_CFG);
 224 }
 225
 226 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 227                                 struct spi_device *spi,
 228                                 struct spi_transfer *xfer, int dma_mode)
 229 {
 230         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 231         void __iomem *regs = sdd->regs;
 232         u32 modecfg, chcfg;
 233
 234         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 235         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 236
 237         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 238         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 239
 240         if (dma_mode) {
 241                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 242         } else {
 243                 /* Always shift in data in FIFO, even if xfer is Tx only,
 244                  * this helps setting PCKT_CNT value for generating clocks
 245                  * as exactly needed.
 246                  */
 247                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 248                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 249                                         | S3C64XX_SPI_PACKET_CNT_EN,
 250                                         regs + S3C64XX_SPI_PACKET_CNT);
 251         }
 252
 253         if (xfer->tx_buf != NULL) {
 254                 sdd->state |= TXBUSY;
 255                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 256                 if (dma_mode) {
 257                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 258                         s3c2410_dma_config(sdd->tx_dmach, 1);
 259                         s3c2410_dma_enqueue(sdd->tx_dmach, (void *)sdd,
 260                                                 xfer->tx_dma, xfer->len);
 261                         s3c2410_dma_ctrl(sdd->tx_dmach, S3C2410_DMAOP_START);
 262                 } else {
 263                         unsigned char *buf = (unsigned char *) xfer->tx_buf;
 264                         int i = 0;
 265                         while (i < xfer->len)
 266                                 writeb(buf[i++], regs + S3C64XX_SPI_TX_DATA);
 267                 }
 268         }
 269
 270         if (xfer->rx_buf != NULL) {
 271                 sdd->state |= RXBUSY;
 272
 273                 if (sci->high_speed && sdd->cur_speed >= 30000000UL
 274                                         && !(sdd->cur_mode & SPI_CPHA))
 275                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 276
 277                 if (dma_mode) {
 278                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 279                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 280                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 281                                         | S3C64XX_SPI_PACKET_CNT_EN,
 282                                         regs + S3C64XX_SPI_PACKET_CNT);
 283                         s3c2410_dma_config(sdd->rx_dmach, 1);
 284                         s3c2410_dma_enqueue(sdd->rx_dmach, (void *)sdd,
 285                                                 xfer->rx_dma, xfer->len);
 286                         s3c2410_dma_ctrl(sdd->rx_dmach, S3C2410_DMAOP_START);
 287                 }
 288         }
 289
 290         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 291         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 292 }
 293
 294 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 295                                                 struct spi_device *spi)
 296 {
 297         struct s3c64xx_spi_csinfo *cs;
 298
 299         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 300                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 301                         /* Deselect the last toggled device */
 302                         cs = sdd->tgl_spi->controller_data;
 303                         cs->set_level(cs->line,
 304                                         spi->mode & SPI_CS_HIGH ? 0 : 1);
 305                 }
 306                 sdd->tgl_spi = NULL;
 307         }
 308
 309         cs = spi->controller_data;
 310         cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 311 }
 312
 313 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 314                                 struct spi_transfer *xfer, int dma_mode)
 315 {
 316         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 317         void __iomem *regs = sdd->regs;
 318         unsigned long val;
 319         int ms;
 320
 321         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 322         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 323         ms += 10; /* some tolerance */
 324
 325         if (dma_mode) {
 326                 val = msecs_to_jiffies(ms) + 10;
 327                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 328         } else {
 329                 u32 status;
 330                 val = msecs_to_loops(ms);
 331                 do {
 332                         status = readl(regs + S3C64XX_SPI_STATUS);
 333                 } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
 334         }
 335
 336         if (!val)
 337                 return -EIO;
 338
 339         if (dma_mode) {
 340                 u32 status;
 341
 342                 /*
 343                  * DmaTx returns after simply writing data in the FIFO,
 344                  * w/o waiting for real transmission on the bus to finish.
 345                  * DmaRx returns only after Dma read data from FIFO which
 346                  * needs bus transmission to finish, so we don't worry if
 347                  * Xfer involved Rx(with or without Tx).
 348                  */
 349                 if (xfer->rx_buf == NULL) {
 350                         val = msecs_to_loops(10);
 351                         status = readl(regs + S3C64XX_SPI_STATUS);
 352                         while ((TX_FIFO_LVL(status, sci)
 353                                 || !S3C64XX_SPI_ST_TX_DONE(status, sci))
 354                                         && --val) {
 355                                 cpu_relax();
 356                                 status = readl(regs + S3C64XX_SPI_STATUS);
 357                         }
 358
 359                         if (!val)
 360                                 return -EIO;
 361                 }
 362         } else {
 363                 unsigned char *buf;
 364                 int i;
 365
 366                 /* If it was only Tx */
 367                 if (xfer->rx_buf == NULL) {
 368                         sdd->state &= ~TXBUSY;
 369                         return 0;
 370                 }
 371
 372                 i = 0;
 373                 buf = xfer->rx_buf;
 374                 while (i < xfer->len)
 375                         buf[i++] = readb(regs + S3C64XX_SPI_RX_DATA);
 376
 377                 sdd->state &= ~RXBUSY;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 384                                                 struct spi_device *spi)
 385 {
 386         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 387
 388         if (sdd->tgl_spi == spi)
 389                 sdd->tgl_spi = NULL;
 390
 391         cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 392 }
 393
 394 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 395 {
 396         void __iomem *regs = sdd->regs;
 397         u32 val;
 398
 399         /* Disable Clock */
 400         val = readl(regs + S3C64XX_SPI_CLK_CFG);
 401         val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 402         writel(val, regs + S3C64XX_SPI_CLK_CFG);
 403
 404         /* Set Polarity and Phase */
 405         val = readl(regs + S3C64XX_SPI_CH_CFG);
 406         val &= ~(S3C64XX_SPI_CH_SLAVE |
 407                         S3C64XX_SPI_CPOL_L |
 408                         S3C64XX_SPI_CPHA_B);
 409
 410         if (sdd->cur_mode & SPI_CPOL)
 411                 val |= S3C64XX_SPI_CPOL_L;
 412
 413         if (sdd->cur_mode & SPI_CPHA)
 414                 val |= S3C64XX_SPI_CPHA_B;
 415
 416         writel(val, regs + S3C64XX_SPI_CH_CFG);
 417
 418         /* Set Channel & DMA Mode */
 419         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 420         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 421                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 422
 423         switch (sdd->cur_bpw) {
 424         case 32:
 425                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 426                 break;
 427         case 16:
 428                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 429                 break;
 430         default:
 431                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 432                 break;
 433         }
 434         val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; /* Always 8bits wide */
 435
 436         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 437
 438         /* Configure Clock */
 439         val = readl(regs + S3C64XX_SPI_CLK_CFG);
 440         val &= ~S3C64XX_SPI_PSR_MASK;
 441         val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 442                         & S3C64XX_SPI_PSR_MASK);
 443         writel(val, regs + S3C64XX_SPI_CLK_CFG);
 444
 445         /* Enable Clock */
 446         val = readl(regs + S3C64XX_SPI_CLK_CFG);
 447         val |= S3C64XX_SPI_ENCLK_ENABLE;
 448         writel(val, regs + S3C64XX_SPI_CLK_CFG);
 449 }
 450
 451 static void s3c64xx_spi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id,
 452                                  int size, enum s3c2410_dma_buffresult res)
 453 {
 454         struct s3c64xx_spi_driver_data *sdd = buf_id;
 455         unsigned long flags;
 456
 457         spin_lock_irqsave(&sdd->lock, flags);
 458
 459         if (res == S3C2410_RES_OK)
 460                 sdd->state &= ~RXBUSY;
 461         else
 462                 dev_err(&sdd->pdev->dev, "DmaAbrtRx-%d\n", size);
 463
 464         /* If the other done */
 465         if (!(sdd->state & TXBUSY))
 466                 complete(&sdd->xfer_completion);
 467
 468         spin_unlock_irqrestore(&sdd->lock, flags);
 469 }
 470
 471 static void s3c64xx_spi_dma_txcb(struct s3c2410_dma_chan *chan, void *buf_id,
 472                                  int size, enum s3c2410_dma_buffresult res)
 473 {
 474         struct s3c64xx_spi_driver_data *sdd = buf_id;
 475         unsigned long flags;
 476
 477         spin_lock_irqsave(&sdd->lock, flags);
 478
 479         if (res == S3C2410_RES_OK)
 480                 sdd->state &= ~TXBUSY;
 481         else
 482                 dev_err(&sdd->pdev->dev, "DmaAbrtTx-%d \n", size);
 483
 484         /* If the other done */
 485         if (!(sdd->state & RXBUSY))
 486                 complete(&sdd->xfer_completion);
 487
 488         spin_unlock_irqrestore(&sdd->lock, flags);
 489 }
 490
 491 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 492
 493 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 494                                                 struct spi_message *msg)
 495 {
 496         struct device *dev = &sdd->pdev->dev;
 497         struct spi_transfer *xfer;
 498
 499         if (msg->is_dma_mapped)
 500                 return 0;
 501
 502         /* First mark all xfer unmapped */
 503         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 504                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 505                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 506         }
 507
 508         /* Map until end or first fail */
 509         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 510
 511                 if (xfer->tx_buf != NULL) {
 512                         xfer->tx_dma = dma_map_single(dev,
 513                                         (void *)xfer->tx_buf, xfer->len,
 514                                         DMA_TO_DEVICE);
 515                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 516                                 dev_err(dev, "dma_map_single Tx failed\n");
 517                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 518                                 return -ENOMEM;
 519                         }
 520                 }
 521
 522                 if (xfer->rx_buf != NULL) {
 523                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 524                                                 xfer->len, DMA_FROM_DEVICE);
 525                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 526                                 dev_err(dev, "dma_map_single Rx failed\n");
 527                                 dma_unmap_single(dev, xfer->tx_dma,
 528                                                 xfer->len, DMA_TO_DEVICE);
 529                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 530                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 531                                 return -ENOMEM;
 532                         }
 533                 }
 534         }
 535
 536         return 0;
 537 }
 538
 539 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 540                                                 struct spi_message *msg)
 541 {
 542         struct device *dev = &sdd->pdev->dev;
 543         struct spi_transfer *xfer;
 544
 545         if (msg->is_dma_mapped)
 546                 return;
 547
 548         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 549
 550                 if (xfer->rx_buf != NULL
 551                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 552                         dma_unmap_single(dev, xfer->rx_dma,
 553                                                 xfer->len, DMA_FROM_DEVICE);
 554
 555                 if (xfer->tx_buf != NULL
 556                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 557                         dma_unmap_single(dev, xfer->tx_dma,
 558                                                 xfer->len, DMA_TO_DEVICE);
 559         }
 560 }
 561
 562 static void handle_msg(struct s3c64xx_spi_driver_data *sdd,
 563                                         struct spi_message *msg)
 564 {
 565         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 566         struct spi_device *spi = msg->spi;
 567         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 568         struct spi_transfer *xfer;
 569         int status = 0, cs_toggle = 0;
 570         u32 speed;
 571         u8 bpw;
 572
 573         /* If Master's(controller) state differs from that needed by Slave */
 574         if (sdd->cur_speed != spi->max_speed_hz
 575                         || sdd->cur_mode != spi->mode
 576                         || sdd->cur_bpw != spi->bits_per_word) {
 577                 sdd->cur_bpw = spi->bits_per_word;
 578                 sdd->cur_speed = spi->max_speed_hz;
 579                 sdd->cur_mode = spi->mode;
 580                 s3c64xx_spi_config(sdd);
 581         }
 582
 583         /* Map all the transfers if needed */
 584         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 585                 dev_err(&spi->dev,
 586                         "Xfer: Unable to map message buffers!\n");
 587                 status = -ENOMEM;
 588                 goto out;
 589         }
 590
 591         /* Configure feedback delay */
 592         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 593
 594         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 595
 596                 unsigned long flags;
 597                 int use_dma;
 598
 599                 INIT_COMPLETION(sdd->xfer_completion);
 600
 601                 /* Only BPW and Speed may change across transfers */
 602                 bpw = xfer->bits_per_word ? : spi->bits_per_word;
 603                 speed = xfer->speed_hz ? : spi->max_speed_hz;
 604
 605                 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 606                         sdd->cur_bpw = bpw;
 607                         sdd->cur_speed = speed;
 608                         s3c64xx_spi_config(sdd);
 609                 }
 610
 611                 /* Polling method for xfers not bigger than FIFO capacity */
 612                 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
 613                         use_dma = 0;
 614                 else
 615                         use_dma = 1;
 616
 617                 spin_lock_irqsave(&sdd->lock, flags);
 618
 619                 /* Pending only which is to be done */
 620                 sdd->state &= ~RXBUSY;
 621                 sdd->state &= ~TXBUSY;
 622
 623                 enable_datapath(sdd, spi, xfer, use_dma);
 624
 625                 /* Slave Select */
 626                 enable_cs(sdd, spi);
 627
 628                 /* Start the signals */
 629                 S3C64XX_SPI_ACT(sdd);
 630
 631                 spin_unlock_irqrestore(&sdd->lock, flags);
 632
 633                 status = wait_for_xfer(sdd, xfer, use_dma);
 634
 635                 /* Quiese the signals */
 636                 S3C64XX_SPI_DEACT(sdd);
 637
 638                 if (status) {
 639                         dev_err(&spi->dev, "I/O Error: "
 640                                 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 641                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 642                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 643                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 644                                 xfer->len);
 645
 646                         if (use_dma) {
 647                                 if (xfer->tx_buf != NULL
 648                                                 && (sdd->state & TXBUSY))
 649                                         s3c2410_dma_ctrl(sdd->tx_dmach,
 650                                                         S3C2410_DMAOP_FLUSH);
 651                                 if (xfer->rx_buf != NULL
 652                                                 && (sdd->state & RXBUSY))
 653                                         s3c2410_dma_ctrl(sdd->rx_dmach,
 654                                                         S3C2410_DMAOP_FLUSH);
 655                         }
 656
 657                         goto out;
 658                 }
 659
 660                 if (xfer->delay_usecs)
 661                         udelay(xfer->delay_usecs);
 662
 663                 if (xfer->cs_change) {
 664                         /* Hint that the next mssg is gonna be
 665                            for the same device */
 666                         if (list_is_last(&xfer->transfer_list,
 667                                                 &msg->transfers))
 668                                 cs_toggle = 1;
 669                         else
 670                                 disable_cs(sdd, spi);
 671                 }
 672
 673                 msg->actual_length += xfer->len;
 674
 675                 flush_fifo(sdd);
 676         }
 677
 678 out:
 679         if (!cs_toggle || status)
 680                 disable_cs(sdd, spi);
 681         else
 682                 sdd->tgl_spi = spi;
 683
 684         s3c64xx_spi_unmap_mssg(sdd, msg);
 685
 686         msg->status = status;
 687
 688         if (msg->complete)
 689                 msg->complete(msg->context);
 690 }
 691
 692 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 693 {
 694         if (s3c2410_dma_request(sdd->rx_dmach,
 695                                         &s3c64xx_spi_dma_client, NULL) < 0) {
 696                 dev_err(&sdd->pdev->dev, "cannot get RxDMA\n");
 697                 return 0;
 698         }
 699         s3c2410_dma_set_buffdone_fn(sdd->rx_dmach, s3c64xx_spi_dma_rxcb);
 700         s3c2410_dma_devconfig(sdd->rx_dmach, S3C2410_DMASRC_HW,
 701                                         sdd->sfr_start + S3C64XX_SPI_RX_DATA);
 702
 703         if (s3c2410_dma_request(sdd->tx_dmach,
 704                                         &s3c64xx_spi_dma_client, NULL) < 0) {
 705                 dev_err(&sdd->pdev->dev, "cannot get TxDMA\n");
 706                 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
 707                 return 0;
 708         }
 709         s3c2410_dma_set_buffdone_fn(sdd->tx_dmach, s3c64xx_spi_dma_txcb);
 710         s3c2410_dma_devconfig(sdd->tx_dmach, S3C2410_DMASRC_MEM,
 711                                         sdd->sfr_start + S3C64XX_SPI_TX_DATA);
 712
 713         return 1;
 714 }
 715
 716 static void s3c64xx_spi_work(struct work_struct *work)
 717 {
 718         struct s3c64xx_spi_driver_data *sdd = container_of(work,
 719                                         struct s3c64xx_spi_driver_data, work);
 720         unsigned long flags;
 721
 722         /* Acquire DMA channels */
 723         while (!acquire_dma(sdd))
 724                 msleep(10);
 725
 726         spin_lock_irqsave(&sdd->lock, flags);
 727
 728         while (!list_empty(&sdd->queue)
 729                                 && !(sdd->state & SUSPND)) {
 730
 731                 struct spi_message *msg;
 732
 733                 msg = container_of(sdd->queue.next, struct spi_message, queue);
 734
 735                 list_del_init(&msg->queue);
 736
 737                 /* Set Xfer busy flag */
 738                 sdd->state |= SPIBUSY;
 739
 740                 spin_unlock_irqrestore(&sdd->lock, flags);
 741
 742                 handle_msg(sdd, msg);
 743
 744                 spin_lock_irqsave(&sdd->lock, flags);
 745
 746                 sdd->state &= ~SPIBUSY;
 747         }
 748
 749         spin_unlock_irqrestore(&sdd->lock, flags);
 750
 751         /* Free DMA channels */
 752         s3c2410_dma_free(sdd->tx_dmach, &s3c64xx_spi_dma_client);
 753         s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
 754 }
 755
 756 static int s3c64xx_spi_transfer(struct spi_device *spi,
 757                                                 struct spi_message *msg)
 758 {
 759         struct s3c64xx_spi_driver_data *sdd;
 760         unsigned long flags;
 761
 762         sdd = spi_master_get_devdata(spi->master);
 763
 764         spin_lock_irqsave(&sdd->lock, flags);
 765
 766         if (sdd->state & SUSPND) {
 767                 spin_unlock_irqrestore(&sdd->lock, flags);
 768                 return -ESHUTDOWN;
 769         }
 770
 771         msg->status = -EINPROGRESS;
 772         msg->actual_length = 0;
 773
 774         list_add_tail(&msg->queue, &sdd->queue);
 775
 776         queue_work(sdd->workqueue, &sdd->work);
 777
 778         spin_unlock_irqrestore(&sdd->lock, flags);
 779
 780         return 0;
 781 }
 782
 783 /*
 784  * Here we only check the validity of requested configuration
 785  * and save the configuration in a local data-structure.
 786  * The controller is actually configured only just before we
 787  * get a message to transfer.
 788  */
 789 static int s3c64xx_spi_setup(struct spi_device *spi)
 790 {
 791         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 792         struct s3c64xx_spi_driver_data *sdd;
 793         struct s3c64xx_spi_info *sci;
 794         struct spi_message *msg;
 795         u32 psr, speed;
 796         unsigned long flags;
 797         int err = 0;
 798
 799         if (cs == NULL || cs->set_level == NULL) {
 800                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 801                 return -ENODEV;
 802         }
 803
 804         sdd = spi_master_get_devdata(spi->master);
 805         sci = sdd->cntrlr_info;
 806
 807         spin_lock_irqsave(&sdd->lock, flags);
 808
 809         list_for_each_entry(msg, &sdd->queue, queue) {
 810                 /* Is some mssg is already queued for this device */
 811                 if (msg->spi == spi) {
 812                         dev_err(&spi->dev,
 813                                 "setup: attempt while mssg in queue!\n");
 814                         spin_unlock_irqrestore(&sdd->lock, flags);
 815                         return -EBUSY;
 816                 }
 817         }
 818
 819         if (sdd->state & SUSPND) {
 820                 spin_unlock_irqrestore(&sdd->lock, flags);
 821                 dev_err(&spi->dev,
 822                         "setup: SPI-%d not active!\n", spi->master->bus_num);
 823                 return -ESHUTDOWN;
 824         }
 825
 826         spin_unlock_irqrestore(&sdd->lock, flags);
 827
 828         if (spi->bits_per_word != 8
 829                         && spi->bits_per_word != 16
 830                         && spi->bits_per_word != 32) {
 831                 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
 832                                                         spi->bits_per_word);
 833                 err = -EINVAL;
 834                 goto setup_exit;
 835         }
 836
 837         /* Check if we can provide the requested rate */
 838         speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); /* Max possible */
 839
 840         if (spi->max_speed_hz > speed)
 841                 spi->max_speed_hz = speed;
 842
 843         psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 844         psr &= S3C64XX_SPI_PSR_MASK;
 845         if (psr == S3C64XX_SPI_PSR_MASK)
 846                 psr--;
 847
 848         speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 849         if (spi->max_speed_hz < speed) {
 850                 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 851                         psr++;
 852                 } else {
 853                         err = -EINVAL;
 854                         goto setup_exit;
 855                 }
 856         }
 857
 858         speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 859         if (spi->max_speed_hz >= speed)
 860                 spi->max_speed_hz = speed;
 861         else
 862                 err = -EINVAL;
 863
 864 setup_exit:
 865
 866         /* setup() returns with device de-selected */
 867         disable_cs(sdd, spi);
 868
 869         return err;
 870 }
 871
 872 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
 873 {
 874         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 875         void __iomem *regs = sdd->regs;
 876         unsigned int val;
 877
 878         sdd->cur_speed = 0;
 879
 880         S3C64XX_SPI_DEACT(sdd);
 881
 882         /* Disable Interrupts - we use Polling if not DMA mode */
 883         writel(0, regs + S3C64XX_SPI_INT_EN);
 884
 885         writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
 886                                 regs + S3C64XX_SPI_CLK_CFG);
 887         writel(0, regs + S3C64XX_SPI_MODE_CFG);
 888         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 889
 890         /* Clear any irq pending bits */
 891         writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
 892                                 regs + S3C64XX_SPI_PENDING_CLR);
 893
 894         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
 895
 896         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 897         val &= ~S3C64XX_SPI_MODE_4BURST;
 898         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 899         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 900         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 901
 902         flush_fifo(sdd);
 903 }
 904
 905 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
 906 {
 907         struct resource *mem_res, *dmatx_res, *dmarx_res;
 908         struct s3c64xx_spi_driver_data *sdd;
 909         struct s3c64xx_spi_info *sci;
 910         struct spi_master *master;
 911         int ret;
 912
 913         if (pdev->id < 0) {
 914                 dev_err(&pdev->dev,
 915                                 "Invalid platform device id-%d\n", pdev->id);
 916                 return -ENODEV;
 917         }
 918
 919         if (pdev->dev.platform_data == NULL) {
 920                 dev_err(&pdev->dev, "platform_data missing!\n");
 921                 return -ENODEV;
 922         }
 923
 924         sci = pdev->dev.platform_data;
 925         if (!sci->src_clk_name) {
 926                 dev_err(&pdev->dev,
 927                         "Board init must call s3c64xx_spi_set_info()\n");
 928                 return -EINVAL;
 929         }
 930
 931         /* Check for availability of necessary resource */
 932
 933         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 934         if (dmatx_res == NULL) {
 935                 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
 936                 return -ENXIO;
 937         }
 938
 939         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 940         if (dmarx_res == NULL) {
 941                 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
 942                 return -ENXIO;
 943         }
 944
 945         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 946         if (mem_res == NULL) {
 947                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
 948                 return -ENXIO;
 949         }
 950
 951         master = spi_alloc_master(&pdev->dev,
 952                                 sizeof(struct s3c64xx_spi_driver_data));
 953         if (master == NULL) {
 954                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
 955                 return -ENOMEM;
 956         }
 957
 958         platform_set_drvdata(pdev, master);
 959
 960         sdd = spi_master_get_devdata(master);
 961         sdd->master = master;
 962         sdd->cntrlr_info = sci;
 963         sdd->pdev = pdev;
 964         sdd->sfr_start = mem_res->start;
 965         sdd->tx_dmach = dmatx_res->start;
 966         sdd->rx_dmach = dmarx_res->start;
 967
 968         sdd->cur_bpw = 8;
 969
 970         master->bus_num = pdev->id;
 971         master->setup = s3c64xx_spi_setup;
 972         master->transfer = s3c64xx_spi_transfer;
 973         master->num_chipselect = sci->num_cs;
 974         master->dma_alignment = 8;
 975         /* the spi->mode bits understood by this driver: */
 976         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 977
 978         if (request_mem_region(mem_res->start,
 979                         resource_size(mem_res), pdev->name) == NULL) {
 980                 dev_err(&pdev->dev, "Req mem region failed\n");
 981                 ret = -ENXIO;
 982                 goto err0;
 983         }
 984
 985         sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
 986         if (sdd->regs == NULL) {
 987                 dev_err(&pdev->dev, "Unable to remap IO\n");
 988                 ret = -ENXIO;
 989                 goto err1;
 990         }
 991
 992         if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
 993                 dev_err(&pdev->dev, "Unable to config gpio\n");
 994                 ret = -EBUSY;
 995                 goto err2;
 996         }
 997
 998         /* Setup clocks */
 999         sdd->clk = clk_get(&pdev->dev, "spi");
1000         if (IS_ERR(sdd->clk)) {
1001                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1002                 ret = PTR_ERR(sdd->clk);
1003                 goto err3;
1004         }
1005
1006         if (clk_enable(sdd->clk)) {
1007                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1008                 ret = -EBUSY;
1009                 goto err4;
1010         }
1011
1012         sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name);
1013         if (IS_ERR(sdd->src_clk)) {
1014                 dev_err(&pdev->dev,
1015                         "Unable to acquire clock '%s'\n", sci->src_clk_name);
1016                 ret = PTR_ERR(sdd->src_clk);
1017                 goto err5;
1018         }
1019
1020         if (clk_enable(sdd->src_clk)) {
1021                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n",
1022                                                         sci->src_clk_name);
1023                 ret = -EBUSY;
1024                 goto err6;
1025         }
1026
1027         sdd->workqueue = create_singlethread_workqueue(
1028                                                 dev_name(master->dev.parent));
1029         if (sdd->workqueue == NULL) {
1030                 dev_err(&pdev->dev, "Unable to create workqueue\n");
1031                 ret = -ENOMEM;
1032                 goto err7;
1033         }
1034
1035         /* Setup Deufult Mode */
1036         s3c64xx_spi_hwinit(sdd, pdev->id);
1037
1038         spin_lock_init(&sdd->lock);
1039         init_completion(&sdd->xfer_completion);
1040         INIT_WORK(&sdd->work, s3c64xx_spi_work);
1041         INIT_LIST_HEAD(&sdd->queue);
1042
1043         if (spi_register_master(master)) {
1044                 dev_err(&pdev->dev, "cannot register SPI master\n");
1045                 ret = -EBUSY;
1046                 goto err8;
1047         }
1048
1049         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1050                                         "with %d Slaves attached\n",
1051                                         pdev->id, master->num_chipselect);
1052         dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1053                                         mem_res->end, mem_res->start,
1054                                         sdd->rx_dmach, sdd->tx_dmach);
1055
1056         return 0;
1057
1058 err8:
1059         destroy_workqueue(sdd->workqueue);
1060 err7:
1061         clk_disable(sdd->src_clk);
1062 err6:
1063         clk_put(sdd->src_clk);
1064 err5:
1065         clk_disable(sdd->clk);
1066 err4:
1067         clk_put(sdd->clk);
1068 err3:
1069 err2:
1070         iounmap((void *) sdd->regs);
1071 err1:
1072         release_mem_region(mem_res->start, resource_size(mem_res));
1073 err0:
1074         platform_set_drvdata(pdev, NULL);
1075         spi_master_put(master);
1076
1077         return ret;
1078 }
1079
1080 static int s3c64xx_spi_remove(struct platform_device *pdev)
1081 {
1082         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1083         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1084         struct resource *mem_res;
1085         unsigned long flags;
1086
1087         spin_lock_irqsave(&sdd->lock, flags);
1088         sdd->state |= SUSPND;
1089         spin_unlock_irqrestore(&sdd->lock, flags);
1090
1091         while (sdd->state & SPIBUSY)
1092                 msleep(10);
1093
1094         spi_unregister_master(master);
1095
1096         destroy_workqueue(sdd->workqueue);
1097
1098         clk_disable(sdd->src_clk);
1099         clk_put(sdd->src_clk);
1100
1101         clk_disable(sdd->clk);
1102         clk_put(sdd->clk);
1103
1104         iounmap((void *) sdd->regs);
1105
1106         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1107         if (mem_res != NULL)
1108                 release_mem_region(mem_res->start, resource_size(mem_res));
1109
1110         platform_set_drvdata(pdev, NULL);
1111         spi_master_put(master);
1112
1113         return 0;
1114 }
1115
1116 #ifdef CONFIG_PM
1117 static int s3c64xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1118 {
1119         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1120         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1121         unsigned long flags;
1122
1123         spin_lock_irqsave(&sdd->lock, flags);
1124         sdd->state |= SUSPND;
1125         spin_unlock_irqrestore(&sdd->lock, flags);
1126
1127         while (sdd->state & SPIBUSY)
1128                 msleep(10);
1129
1130         /* Disable the clock */
1131         clk_disable(sdd->src_clk);
1132         clk_disable(sdd->clk);
1133
1134         sdd->cur_speed = 0; /* Output Clock is stopped */
1135
1136         return 0;
1137 }
1138
1139 static int s3c64xx_spi_resume(struct platform_device *pdev)
1140 {
1141         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1142         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1143         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1144         unsigned long flags;
1145
1146         sci->cfg_gpio(pdev);
1147
1148         /* Enable the clock */
1149         clk_enable(sdd->src_clk);
1150         clk_enable(sdd->clk);
1151
1152         s3c64xx_spi_hwinit(sdd, pdev->id);
1153
1154         spin_lock_irqsave(&sdd->lock, flags);
1155         sdd->state &= ~SUSPND;
1156         spin_unlock_irqrestore(&sdd->lock, flags);
1157
1158         return 0;
1159 }
1160 #else
1161 #define s3c64xx_spi_suspend     NULL
1162 #define s3c64xx_spi_resume      NULL
1163 #endif /* CONFIG_PM */
1164
1165 static struct platform_driver s3c64xx_spi_driver = {
1166         .driver = {
1167                 .name   = "s3c64xx-spi",
1168                 .owner = THIS_MODULE,
1169         },
1170         .remove = s3c64xx_spi_remove,
1171         .suspend = s3c64xx_spi_suspend,
1172         .resume = s3c64xx_spi_resume,
1173 };
1174 MODULE_ALIAS("platform:s3c64xx-spi");
1175
1176 static int __init s3c64xx_spi_init(void)
1177 {
1178         return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1179 }
1180 subsys_initcall(s3c64xx_spi_init);
1181
1182 static void __exit s3c64xx_spi_exit(void)
1183 {
1184         platform_driver_unregister(&s3c64xx_spi_driver);
1185 }
1186 module_exit(s3c64xx_spi_exit);
1187
1188 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1189 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1190 MODULE_LICENSE("GPL");