2 * MPC8xxx SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
8 * CPM SPI and QE buffer descriptors mode support:
9 * Copyright (c) 2009 MontaVista Software, Inc.
10 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/bug.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
25 #include <linux/completion.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/irq.h>
29 #include <linux/device.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/platform_device.h>
33 #include <linux/fsl_devices.h>
34 #include <linux/dma-mapping.h>
36 #include <linux/mutex.h>
38 #include <linux/of_platform.h>
39 #include <linux/gpio.h>
40 #include <linux/of_gpio.h>
41 #include <linux/slab.h>
43 #include <sysdev/fsl_soc.h>
48 /* CPM1 and CPM2 are mutually exclusive. */
51 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
54 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
57 /* SPI Controller registers */
58 struct mpc8xxx_spi_reg {
68 /* SPI Controller mode register definitions */
69 #define SPMODE_LOOP (1 << 30)
70 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
71 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
72 #define SPMODE_DIV16 (1 << 27)
73 #define SPMODE_REV (1 << 26)
74 #define SPMODE_MS (1 << 25)
75 #define SPMODE_ENABLE (1 << 24)
76 #define SPMODE_LEN(x) ((x) << 20)
77 #define SPMODE_PM(x) ((x) << 16)
78 #define SPMODE_OP (1 << 14)
79 #define SPMODE_CG(x) ((x) << 7)
82 * Default for SPI Mode:
83 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
85 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
86 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
88 /* SPIE register values */
89 #define SPIE_NE 0x00000200 /* Not empty */
90 #define SPIE_NF 0x00000100 /* Not full */
92 /* SPIM register values */
93 #define SPIM_NE 0x00000200 /* Not empty */
94 #define SPIM_NF 0x00000100 /* Not full */
96 #define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
97 #define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
99 /* SPCOM register values */
100 #define SPCOM_STR (1 << 23) /* Start transmit */
102 #define SPI_PRAM_SIZE 0x100
103 #define SPI_MRBLR ((unsigned int)PAGE_SIZE)
105 /* SPI Controller driver's private data. */
108 struct mpc8xxx_spi_reg __iomem *base;
110 /* rx & tx bufs from the spi_transfer */
115 struct spi_pram __iomem *pram;
116 struct cpm_buf_desc __iomem *tx_bd;
117 struct cpm_buf_desc __iomem *rx_bd;
119 struct spi_transfer *xfer_in_progress;
121 /* dma addresses for CPM transfers */
127 dma_addr_t dma_dummy_tx;
128 dma_addr_t dma_dummy_rx;
130 /* functions to deal with different sized buffers */
131 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
132 u32(*get_tx) (struct mpc8xxx_spi *);
137 unsigned nsecs; /* (clock cycle time)/2 */
139 u32 spibrg; /* SPIBRG input clock */
140 u32 rx_shift; /* RX data reg shift when in qe mode */
141 u32 tx_shift; /* TX data reg shift when in qe mode */
145 struct workqueue_struct *workqueue;
146 struct work_struct work;
148 struct list_head queue;
151 struct completion done;
154 static void *mpc8xxx_dummy_rx;
155 static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
156 static int mpc8xxx_dummy_rx_refcnt;
158 struct spi_mpc8xxx_cs {
159 /* functions to deal with different sized buffers */
160 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
161 u32 (*get_tx) (struct mpc8xxx_spi *);
162 u32 rx_shift; /* RX data reg shift when in qe mode */
163 u32 tx_shift; /* TX data reg shift when in qe mode */
164 u32 hw_mode; /* Holds HW mode register settings */
167 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
172 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
177 #define MPC83XX_SPI_RX_BUF(type) \
179 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
181 type *rx = mpc8xxx_spi->rx; \
182 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
183 mpc8xxx_spi->rx = rx; \
186 #define MPC83XX_SPI_TX_BUF(type) \
188 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
191 const type *tx = mpc8xxx_spi->tx; \
194 data = *tx++ << mpc8xxx_spi->tx_shift; \
195 mpc8xxx_spi->tx = tx; \
199 MPC83XX_SPI_RX_BUF(u8)
200 MPC83XX_SPI_RX_BUF(u16)
201 MPC83XX_SPI_RX_BUF(u32)
202 MPC83XX_SPI_TX_BUF(u8)
203 MPC83XX_SPI_TX_BUF(u16)
204 MPC83XX_SPI_TX_BUF(u32)
206 static void mpc8xxx_spi_change_mode(struct spi_device *spi)
208 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
209 struct spi_mpc8xxx_cs *cs = spi->controller_state;
210 __be32 __iomem *mode = &mspi->base->mode;
213 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
216 /* Turn off IRQs locally to minimize time that SPI is disabled. */
217 local_irq_save(flags);
219 /* Turn off SPI unit prior changing mode */
220 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
222 /* When in CPM mode, we need to reinit tx and rx. */
223 if (mspi->flags & SPI_CPM_MODE) {
224 if (mspi->flags & SPI_QE) {
225 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
226 QE_CR_PROTOCOL_UNSPECIFIED, 0);
228 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
229 if (mspi->flags & SPI_CPM1) {
230 out_be16(&mspi->pram->rbptr,
231 in_be16(&mspi->pram->rbase));
232 out_be16(&mspi->pram->tbptr,
233 in_be16(&mspi->pram->tbase));
237 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
238 local_irq_restore(flags);
241 static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
243 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
244 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
245 bool pol = spi->mode & SPI_CS_HIGH;
246 struct spi_mpc8xxx_cs *cs = spi->controller_state;
248 if (value == BITBANG_CS_INACTIVE) {
249 if (pdata->cs_control)
250 pdata->cs_control(spi, !pol);
253 if (value == BITBANG_CS_ACTIVE) {
254 mpc8xxx_spi->rx_shift = cs->rx_shift;
255 mpc8xxx_spi->tx_shift = cs->tx_shift;
256 mpc8xxx_spi->get_rx = cs->get_rx;
257 mpc8xxx_spi->get_tx = cs->get_tx;
259 mpc8xxx_spi_change_mode(spi);
261 if (pdata->cs_control)
262 pdata->cs_control(spi, pol);
267 mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
268 struct spi_device *spi,
269 struct mpc8xxx_spi *mpc8xxx_spi,
274 if (bits_per_word <= 8) {
275 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
276 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
277 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
281 } else if (bits_per_word <= 16) {
282 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
283 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
284 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
288 } else if (bits_per_word <= 32) {
289 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
290 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
294 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
295 spi->mode & SPI_LSB_FIRST) {
297 if (bits_per_word <= 8)
302 mpc8xxx_spi->rx_shift = cs->rx_shift;
303 mpc8xxx_spi->tx_shift = cs->tx_shift;
304 mpc8xxx_spi->get_rx = cs->get_rx;
305 mpc8xxx_spi->get_tx = cs->get_tx;
307 return bits_per_word;
311 mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
312 struct spi_device *spi,
315 /* QE uses Little Endian for words > 8
316 * so transform all words > 8 into 8 bits
317 * Unfortnatly that doesn't work for LSB so
318 * reject these for now */
319 /* Note: 32 bits word, LSB works iff
320 * tfcr/rfcr is set to CPMFCR_GBL */
321 if (spi->mode & SPI_LSB_FIRST &&
324 if (bits_per_word > 8)
325 return 8; /* pretend its 8 bits */
326 return bits_per_word;
330 int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
332 struct mpc8xxx_spi *mpc8xxx_spi;
336 struct spi_mpc8xxx_cs *cs = spi->controller_state;
338 mpc8xxx_spi = spi_master_get_devdata(spi->master);
341 bits_per_word = t->bits_per_word;
348 /* spi_transfer level calls that work per-word */
350 bits_per_word = spi->bits_per_word;
352 /* Make sure its a bit width we support [4..16, 32] */
353 if ((bits_per_word < 4)
354 || ((bits_per_word > 16) && (bits_per_word != 32)))
358 hz = spi->max_speed_hz;
360 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
361 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
364 else if (mpc8xxx_spi->flags & SPI_QE)
365 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
368 if (bits_per_word < 0)
369 return bits_per_word;
371 if (bits_per_word == 32)
374 bits_per_word = bits_per_word - 1;
376 /* mask out bits we are going to set */
377 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
380 cs->hw_mode |= SPMODE_LEN(bits_per_word);
382 if ((mpc8xxx_spi->spibrg / hz) > 64) {
383 cs->hw_mode |= SPMODE_DIV16;
384 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
386 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
387 "Will use %d Hz instead.\n", dev_name(&spi->dev),
388 hz, mpc8xxx_spi->spibrg / 1024);
392 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
396 cs->hw_mode |= SPMODE_PM(pm);
398 mpc8xxx_spi_change_mode(spi);
402 static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
404 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
405 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
406 unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
407 unsigned int xfer_ofs;
409 xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
411 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
412 out_be16(&rx_bd->cbd_datlen, 0);
413 out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
415 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
416 out_be16(&tx_bd->cbd_datlen, xfer_len);
417 out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
421 mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
424 static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
425 struct spi_transfer *t, bool is_dma_mapped)
427 struct device *dev = mspi->dev;
430 mspi->map_tx_dma = 0;
431 mspi->map_rx_dma = 0;
433 mspi->map_tx_dma = 1;
434 mspi->map_rx_dma = 1;
438 mspi->tx_dma = mspi->dma_dummy_tx;
439 mspi->map_tx_dma = 0;
443 mspi->rx_dma = mspi->dma_dummy_rx;
444 mspi->map_rx_dma = 0;
447 if (mspi->map_tx_dma) {
448 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
450 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
452 if (dma_mapping_error(dev, mspi->tx_dma)) {
453 dev_err(dev, "unable to map tx dma\n");
456 } else if (t->tx_buf) {
457 mspi->tx_dma = t->tx_dma;
460 if (mspi->map_rx_dma) {
461 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
463 if (dma_mapping_error(dev, mspi->rx_dma)) {
464 dev_err(dev, "unable to map rx dma\n");
467 } else if (t->rx_buf) {
468 mspi->rx_dma = t->rx_dma;
472 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
474 mspi->xfer_in_progress = t;
475 mspi->count = t->len;
477 /* start CPM transfers */
478 mpc8xxx_spi_cpm_bufs_start(mspi);
483 if (mspi->map_tx_dma)
484 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
488 static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
490 struct device *dev = mspi->dev;
491 struct spi_transfer *t = mspi->xfer_in_progress;
493 if (mspi->map_tx_dma)
494 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
495 if (mspi->map_rx_dma)
496 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
497 mspi->xfer_in_progress = NULL;
500 static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
501 struct spi_transfer *t, unsigned int len)
508 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
511 word = mspi->get_tx(mspi);
512 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
517 static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
520 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
521 unsigned int len = t->len;
525 bits_per_word = spi->bits_per_word;
526 if (t->bits_per_word)
527 bits_per_word = t->bits_per_word;
529 if (bits_per_word > 8) {
530 /* invalid length? */
535 if (bits_per_word > 16) {
536 /* invalid length? */
542 mpc8xxx_spi->tx = t->tx_buf;
543 mpc8xxx_spi->rx = t->rx_buf;
545 INIT_COMPLETION(mpc8xxx_spi->done);
547 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
548 ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
550 ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
554 wait_for_completion(&mpc8xxx_spi->done);
556 /* disable rx ints */
557 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
559 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
560 mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
562 return mpc8xxx_spi->count;
565 static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
567 struct spi_device *spi = m->spi;
568 struct spi_transfer *t;
569 unsigned int cs_change;
570 const int nsecs = 50;
575 list_for_each_entry(t, &m->transfers, transfer_list) {
576 if (t->bits_per_word || t->speed_hz) {
577 /* Don't allow changes if CS is active */
581 status = mpc8xxx_spi_setup_transfer(spi, t);
587 mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
590 cs_change = t->cs_change;
592 status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
597 m->actual_length += t->len;
600 udelay(t->delay_usecs);
604 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
610 m->complete(m->context);
612 if (status || !cs_change) {
614 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
617 mpc8xxx_spi_setup_transfer(spi, NULL);
620 static void mpc8xxx_spi_work(struct work_struct *work)
622 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
625 spin_lock_irq(&mpc8xxx_spi->lock);
626 while (!list_empty(&mpc8xxx_spi->queue)) {
627 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
628 struct spi_message, queue);
630 list_del_init(&m->queue);
631 spin_unlock_irq(&mpc8xxx_spi->lock);
633 mpc8xxx_spi_do_one_msg(m);
635 spin_lock_irq(&mpc8xxx_spi->lock);
637 spin_unlock_irq(&mpc8xxx_spi->lock);
640 static int mpc8xxx_spi_setup(struct spi_device *spi)
642 struct mpc8xxx_spi *mpc8xxx_spi;
645 struct spi_mpc8xxx_cs *cs = spi->controller_state;
647 if (!spi->max_speed_hz)
651 cs = kzalloc(sizeof *cs, GFP_KERNEL);
654 spi->controller_state = cs;
656 mpc8xxx_spi = spi_master_get_devdata(spi->master);
658 hw_mode = cs->hw_mode; /* Save original settings */
659 cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
660 /* mask out bits we are going to set */
661 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
662 | SPMODE_REV | SPMODE_LOOP);
664 if (spi->mode & SPI_CPHA)
665 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
666 if (spi->mode & SPI_CPOL)
667 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
668 if (!(spi->mode & SPI_LSB_FIRST))
669 cs->hw_mode |= SPMODE_REV;
670 if (spi->mode & SPI_LOOP)
671 cs->hw_mode |= SPMODE_LOOP;
673 retval = mpc8xxx_spi_setup_transfer(spi, NULL);
675 cs->hw_mode = hw_mode; /* Restore settings */
681 static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
685 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
686 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
688 len = in_be16(&mspi->rx_bd->cbd_datlen);
689 if (len > mspi->count) {
694 /* Clear the events */
695 mpc8xxx_spi_write_reg(&mspi->base->event, events);
699 mpc8xxx_spi_cpm_bufs_start(mspi);
701 complete(&mspi->done);
704 static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
706 /* We need handle RX first */
707 if (events & SPIE_NE) {
708 u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
711 mspi->get_rx(rx_data, mspi);
714 if ((events & SPIE_NF) == 0)
715 /* spin until TX is done */
717 mpc8xxx_spi_read_reg(&mspi->base->event)) &
721 /* Clear the events */
722 mpc8xxx_spi_write_reg(&mspi->base->event, events);
726 u32 word = mspi->get_tx(mspi);
728 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
730 complete(&mspi->done);
734 static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
736 struct mpc8xxx_spi *mspi = context_data;
737 irqreturn_t ret = IRQ_NONE;
740 /* Get interrupt events(tx/rx) */
741 events = mpc8xxx_spi_read_reg(&mspi->base->event);
745 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
747 if (mspi->flags & SPI_CPM_MODE)
748 mpc8xxx_spi_cpm_irq(mspi, events);
750 mpc8xxx_spi_cpu_irq(mspi, events);
755 static int mpc8xxx_spi_transfer(struct spi_device *spi,
756 struct spi_message *m)
758 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
761 m->actual_length = 0;
762 m->status = -EINPROGRESS;
764 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
765 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
766 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
767 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
773 static void mpc8xxx_spi_cleanup(struct spi_device *spi)
775 kfree(spi->controller_state);
778 static void *mpc8xxx_spi_alloc_dummy_rx(void)
780 mutex_lock(&mpc8xxx_dummy_rx_lock);
782 if (!mpc8xxx_dummy_rx)
783 mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
784 if (mpc8xxx_dummy_rx)
785 mpc8xxx_dummy_rx_refcnt++;
787 mutex_unlock(&mpc8xxx_dummy_rx_lock);
789 return mpc8xxx_dummy_rx;
792 static void mpc8xxx_spi_free_dummy_rx(void)
794 mutex_lock(&mpc8xxx_dummy_rx_lock);
796 switch (mpc8xxx_dummy_rx_refcnt) {
801 kfree(mpc8xxx_dummy_rx);
802 mpc8xxx_dummy_rx = NULL;
805 mpc8xxx_dummy_rx_refcnt--;
809 mutex_unlock(&mpc8xxx_dummy_rx_lock);
812 static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
814 struct device *dev = mspi->dev;
815 struct device_node *np = dev->of_node;
818 unsigned long spi_base_ofs;
819 unsigned long pram_ofs = -ENOMEM;
821 /* Can't use of_address_to_resource(), QE muram isn't at 0. */
822 iprop = of_get_property(np, "reg", &size);
824 /* QE with a fixed pram location? */
825 if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
826 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
828 /* QE but with a dynamic pram location? */
829 if (mspi->flags & SPI_QE) {
830 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
831 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
832 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
836 /* CPM1 and CPM2 pram must be at a fixed addr. */
837 if (!iprop || size != sizeof(*iprop) * 4)
840 spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
841 if (IS_ERR_VALUE(spi_base_ofs))
844 if (mspi->flags & SPI_CPM2) {
845 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
846 if (!IS_ERR_VALUE(pram_ofs)) {
847 u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
849 out_be16(spi_base, pram_ofs);
852 struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
853 u16 rpbase = in_be16(&pram->rpbase);
855 /* Microcode relocation patch applied? */
862 cpm_muram_free(spi_base_ofs);
866 static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
868 struct device *dev = mspi->dev;
869 struct device_node *np = dev->of_node;
872 unsigned long pram_ofs;
873 unsigned long bds_ofs;
875 if (!(mspi->flags & SPI_CPM_MODE))
878 if (!mpc8xxx_spi_alloc_dummy_rx())
881 if (mspi->flags & SPI_QE) {
882 iprop = of_get_property(np, "cell-index", &size);
883 if (iprop && size == sizeof(*iprop))
884 mspi->subblock = *iprop;
886 switch (mspi->subblock) {
888 dev_warn(dev, "cell-index unspecified, assuming SPI1");
891 mspi->subblock = QE_CR_SUBBLOCK_SPI1;
894 mspi->subblock = QE_CR_SUBBLOCK_SPI2;
899 pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
900 if (IS_ERR_VALUE(pram_ofs)) {
901 dev_err(dev, "can't allocate spi parameter ram\n");
905 bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
906 sizeof(*mspi->rx_bd), 8);
907 if (IS_ERR_VALUE(bds_ofs)) {
908 dev_err(dev, "can't allocate bds\n");
912 mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
914 if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
915 dev_err(dev, "unable to map dummy tx buffer\n");
919 mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
921 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
922 dev_err(dev, "unable to map dummy rx buffer\n");
926 mspi->pram = cpm_muram_addr(pram_ofs);
928 mspi->tx_bd = cpm_muram_addr(bds_ofs);
929 mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
931 /* Initialize parameter ram. */
932 out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
933 out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
934 out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
935 out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
936 out_be16(&mspi->pram->mrblr, SPI_MRBLR);
937 out_be32(&mspi->pram->rstate, 0);
938 out_be32(&mspi->pram->rdp, 0);
939 out_be16(&mspi->pram->rbptr, 0);
940 out_be16(&mspi->pram->rbc, 0);
941 out_be32(&mspi->pram->rxtmp, 0);
942 out_be32(&mspi->pram->tstate, 0);
943 out_be32(&mspi->pram->tdp, 0);
944 out_be16(&mspi->pram->tbptr, 0);
945 out_be16(&mspi->pram->tbc, 0);
946 out_be32(&mspi->pram->txtmp, 0);
951 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
953 cpm_muram_free(bds_ofs);
955 cpm_muram_free(pram_ofs);
957 mpc8xxx_spi_free_dummy_rx();
961 static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
963 struct device *dev = mspi->dev;
965 dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
966 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
967 cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
968 cpm_muram_free(cpm_muram_offset(mspi->pram));
969 mpc8xxx_spi_free_dummy_rx();
972 static const char *mpc8xxx_spi_strmode(unsigned int flags)
974 if (flags & SPI_QE_CPU_MODE) {
976 } else if (flags & SPI_CPM_MODE) {
979 else if (flags & SPI_CPM2)
987 static struct spi_master * __devinit
988 mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
990 struct fsl_spi_platform_data *pdata = dev->platform_data;
991 struct spi_master *master;
992 struct mpc8xxx_spi *mpc8xxx_spi;
996 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
997 if (master == NULL) {
1002 dev_set_drvdata(dev, master);
1004 /* the spi->mode bits understood by this driver: */
1005 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
1006 | SPI_LSB_FIRST | SPI_LOOP;
1008 master->setup = mpc8xxx_spi_setup;
1009 master->transfer = mpc8xxx_spi_transfer;
1010 master->cleanup = mpc8xxx_spi_cleanup;
1011 master->dev.of_node = dev->of_node;
1013 mpc8xxx_spi = spi_master_get_devdata(master);
1014 mpc8xxx_spi->dev = dev;
1015 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
1016 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
1017 mpc8xxx_spi->flags = pdata->flags;
1018 mpc8xxx_spi->spibrg = pdata->sysclk;
1020 ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
1024 mpc8xxx_spi->rx_shift = 0;
1025 mpc8xxx_spi->tx_shift = 0;
1026 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
1027 mpc8xxx_spi->rx_shift = 16;
1028 mpc8xxx_spi->tx_shift = 24;
1031 init_completion(&mpc8xxx_spi->done);
1033 mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
1034 if (mpc8xxx_spi->base == NULL) {
1039 mpc8xxx_spi->irq = irq;
1041 /* Register for SPI Interrupt */
1042 ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
1043 0, "mpc8xxx_spi", mpc8xxx_spi);
1048 master->bus_num = pdata->bus_num;
1049 master->num_chipselect = pdata->max_chipselect;
1051 /* SPI controller initializations */
1052 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
1053 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
1054 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
1055 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
1057 /* Enable SPI interface */
1058 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
1059 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
1060 regval |= SPMODE_OP;
1062 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
1063 spin_lock_init(&mpc8xxx_spi->lock);
1064 init_completion(&mpc8xxx_spi->done);
1065 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
1066 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
1068 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
1069 dev_name(master->dev.parent));
1070 if (mpc8xxx_spi->workqueue == NULL) {
1075 ret = spi_register_master(master);
1079 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
1080 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
1085 destroy_workqueue(mpc8xxx_spi->workqueue);
1087 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1089 iounmap(mpc8xxx_spi->base);
1091 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1093 spi_master_put(master);
1095 return ERR_PTR(ret);
1098 static int __devexit mpc8xxx_spi_remove(struct device *dev)
1100 struct mpc8xxx_spi *mpc8xxx_spi;
1101 struct spi_master *master;
1103 master = dev_get_drvdata(dev);
1104 mpc8xxx_spi = spi_master_get_devdata(master);
1106 flush_workqueue(mpc8xxx_spi->workqueue);
1107 destroy_workqueue(mpc8xxx_spi->workqueue);
1108 spi_unregister_master(master);
1110 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1111 iounmap(mpc8xxx_spi->base);
1112 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1117 struct mpc8xxx_spi_probe_info {
1118 struct fsl_spi_platform_data pdata;
1123 static struct mpc8xxx_spi_probe_info *
1124 to_of_pinfo(struct fsl_spi_platform_data *pdata)
1126 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
1129 static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
1131 struct device *dev = spi->dev.parent;
1132 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
1133 u16 cs = spi->chip_select;
1134 int gpio = pinfo->gpios[cs];
1135 bool alow = pinfo->alow_flags[cs];
1137 gpio_set_value(gpio, on ^ alow);
1140 static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
1142 struct device_node *np = dev->of_node;
1143 struct fsl_spi_platform_data *pdata = dev->platform_data;
1144 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1145 unsigned int ngpios;
1149 ngpios = of_gpio_count(np);
1152 * SPI w/o chip-select line. One SPI device is still permitted
1155 pdata->max_chipselect = 1;
1159 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
1162 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
1164 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
1166 if (!pinfo->alow_flags) {
1168 goto err_alloc_flags;
1171 for (; i < ngpios; i++) {
1173 enum of_gpio_flags flags;
1175 gpio = of_get_gpio_flags(np, i, &flags);
1176 if (!gpio_is_valid(gpio)) {
1177 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
1182 ret = gpio_request(gpio, dev_name(dev));
1184 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
1188 pinfo->gpios[i] = gpio;
1189 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
1191 ret = gpio_direction_output(pinfo->gpios[i],
1192 pinfo->alow_flags[i]);
1194 dev_err(dev, "can't set output direction for gpio "
1195 "#%d: %d\n", i, ret);
1200 pdata->max_chipselect = ngpios;
1201 pdata->cs_control = mpc8xxx_spi_cs_control;
1207 if (gpio_is_valid(pinfo->gpios[i]))
1208 gpio_free(pinfo->gpios[i]);
1212 kfree(pinfo->alow_flags);
1213 pinfo->alow_flags = NULL;
1215 kfree(pinfo->gpios);
1216 pinfo->gpios = NULL;
1220 static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
1222 struct fsl_spi_platform_data *pdata = dev->platform_data;
1223 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1229 for (i = 0; i < pdata->max_chipselect; i++) {
1230 if (gpio_is_valid(pinfo->gpios[i]))
1231 gpio_free(pinfo->gpios[i]);
1234 kfree(pinfo->gpios);
1235 kfree(pinfo->alow_flags);
1239 static int __devinit of_mpc8xxx_spi_probe(struct platform_device *ofdev,
1240 const struct of_device_id *ofid)
1242 struct device *dev = &ofdev->dev;
1243 struct device_node *np = ofdev->dev.of_node;
1244 struct mpc8xxx_spi_probe_info *pinfo;
1245 struct fsl_spi_platform_data *pdata;
1246 struct spi_master *master;
1247 struct resource mem;
1248 struct resource irq;
1252 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
1256 pdata = &pinfo->pdata;
1257 dev->platform_data = pdata;
1259 /* Allocate bus num dynamically. */
1260 pdata->bus_num = -1;
1262 /* SPI controller is either clocked from QE or SoC clock. */
1263 pdata->sysclk = get_brgfreq();
1264 if (pdata->sysclk == -1) {
1265 pdata->sysclk = fsl_get_sys_freq();
1266 if (pdata->sysclk == -1) {
1272 prop = of_get_property(np, "mode", NULL);
1273 if (prop && !strcmp(prop, "cpu-qe"))
1274 pdata->flags = SPI_QE_CPU_MODE;
1275 else if (prop && !strcmp(prop, "qe"))
1276 pdata->flags = SPI_CPM_MODE | SPI_QE;
1277 else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1278 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1279 else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1280 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
1282 ret = of_mpc8xxx_spi_get_chipselects(dev);
1286 ret = of_address_to_resource(np, 0, &mem);
1290 ret = of_irq_to_resource(np, 0, &irq);
1296 master = mpc8xxx_spi_probe(dev, &mem, irq.start);
1297 if (IS_ERR(master)) {
1298 ret = PTR_ERR(master);
1305 of_mpc8xxx_spi_free_chipselects(dev);
1311 static int __devexit of_mpc8xxx_spi_remove(struct platform_device *ofdev)
1315 ret = mpc8xxx_spi_remove(&ofdev->dev);
1318 of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
1322 static const struct of_device_id of_mpc8xxx_spi_match[] = {
1323 { .compatible = "fsl,spi" },
1326 MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
1328 static struct of_platform_driver of_mpc8xxx_spi_driver = {
1330 .name = "mpc8xxx_spi",
1331 .owner = THIS_MODULE,
1332 .of_match_table = of_mpc8xxx_spi_match,
1334 .probe = of_mpc8xxx_spi_probe,
1335 .remove = __devexit_p(of_mpc8xxx_spi_remove),
1338 #ifdef CONFIG_MPC832x_RDB
1341 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1342 * only. The driver should go away soon, since newer MPC8323E-RDB's device
1343 * tree can work with OpenFirmware driver. But for now we support old trees
1346 static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
1348 struct resource *mem;
1350 struct spi_master *master;
1352 if (!pdev->dev.platform_data)
1355 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1359 irq = platform_get_irq(pdev, 0);
1363 master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
1365 return PTR_ERR(master);
1369 static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
1371 return mpc8xxx_spi_remove(&pdev->dev);
1374 MODULE_ALIAS("platform:mpc8xxx_spi");
1375 static struct platform_driver mpc8xxx_spi_driver = {
1376 .probe = plat_mpc8xxx_spi_probe,
1377 .remove = __devexit_p(plat_mpc8xxx_spi_remove),
1379 .name = "mpc8xxx_spi",
1380 .owner = THIS_MODULE,
1384 static bool legacy_driver_failed;
1386 static void __init legacy_driver_register(void)
1388 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
1391 static void __exit legacy_driver_unregister(void)
1393 if (legacy_driver_failed)
1395 platform_driver_unregister(&mpc8xxx_spi_driver);
1398 static void __init legacy_driver_register(void) {}
1399 static void __exit legacy_driver_unregister(void) {}
1400 #endif /* CONFIG_MPC832x_RDB */
1402 static int __init mpc8xxx_spi_init(void)
1404 legacy_driver_register();
1405 return of_register_platform_driver(&of_mpc8xxx_spi_driver);
1408 static void __exit mpc8xxx_spi_exit(void)
1410 of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
1411 legacy_driver_unregister();
1414 module_init(mpc8xxx_spi_init);
1415 module_exit(mpc8xxx_spi_exit);
1417 MODULE_AUTHOR("Kumar Gala");
1418 MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
1419 MODULE_LICENSE("GPL");