2 * SPI driver for Nvidia's Tegra20 Serial Flash Controller.
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36 #include <linux/spi/spi.h>
38 #define SPI_COMMAND 0x000
39 #define SPI_GO BIT(30)
40 #define SPI_M_S BIT(28)
41 #define SPI_ACTIVE_SCLK_MASK (0x3 << 26)
42 #define SPI_ACTIVE_SCLK_DRIVE_LOW (0 << 26)
43 #define SPI_ACTIVE_SCLK_DRIVE_HIGH (1 << 26)
44 #define SPI_ACTIVE_SCLK_PULL_LOW (2 << 26)
45 #define SPI_ACTIVE_SCLK_PULL_HIGH (3 << 26)
47 #define SPI_CK_SDA_FALLING (1 << 21)
48 #define SPI_CK_SDA_RISING (0 << 21)
49 #define SPI_CK_SDA_MASK (1 << 21)
50 #define SPI_ACTIVE_SDA (0x3 << 18)
51 #define SPI_ACTIVE_SDA_DRIVE_LOW (0 << 18)
52 #define SPI_ACTIVE_SDA_DRIVE_HIGH (1 << 18)
53 #define SPI_ACTIVE_SDA_PULL_LOW (2 << 18)
54 #define SPI_ACTIVE_SDA_PULL_HIGH (3 << 18)
56 #define SPI_CS_POL_INVERT BIT(16)
57 #define SPI_TX_EN BIT(15)
58 #define SPI_RX_EN BIT(14)
59 #define SPI_CS_VAL_HIGH BIT(13)
60 #define SPI_CS_VAL_LOW 0x0
61 #define SPI_CS_SW BIT(12)
63 #define SPI_CS_DELAY_MASK (7 << 9)
64 #define SPI_CS3_EN BIT(8)
65 #define SPI_CS2_EN BIT(7)
66 #define SPI_CS1_EN BIT(6)
67 #define SPI_CS0_EN BIT(5)
69 #define SPI_CS_MASK (SPI_CS3_EN | SPI_CS2_EN | \
70 SPI_CS1_EN | SPI_CS0_EN)
71 #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
73 #define SPI_MODES (SPI_ACTIVE_SCLK_MASK | SPI_CK_SDA_MASK)
75 #define SPI_STATUS 0x004
76 #define SPI_BSY BIT(31)
77 #define SPI_RDY BIT(30)
78 #define SPI_TXF_FLUSH BIT(29)
79 #define SPI_RXF_FLUSH BIT(28)
80 #define SPI_RX_UNF BIT(27)
81 #define SPI_TX_OVF BIT(26)
82 #define SPI_RXF_EMPTY BIT(25)
83 #define SPI_RXF_FULL BIT(24)
84 #define SPI_TXF_EMPTY BIT(23)
85 #define SPI_TXF_FULL BIT(22)
86 #define SPI_BLK_CNT(count) (((count) & 0xffff) + 1)
88 #define SPI_FIFO_ERROR (SPI_RX_UNF | SPI_TX_OVF)
89 #define SPI_FIFO_EMPTY (SPI_TX_EMPTY | SPI_RX_EMPTY)
91 #define SPI_RX_CMP 0x8
92 #define SPI_DMA_CTL 0x0C
93 #define SPI_DMA_EN BIT(31)
94 #define SPI_IE_RXC BIT(27)
95 #define SPI_IE_TXC BIT(26)
96 #define SPI_PACKED BIT(20)
97 #define SPI_RX_TRIG_MASK (0x3 << 18)
98 #define SPI_RX_TRIG_1W (0x0 << 18)
99 #define SPI_RX_TRIG_4W (0x1 << 18)
100 #define SPI_TX_TRIG_MASK (0x3 << 16)
101 #define SPI_TX_TRIG_1W (0x0 << 16)
102 #define SPI_TX_TRIG_4W (0x1 << 16)
103 #define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF);
105 #define SPI_TX_FIFO 0x10
106 #define SPI_RX_FIFO 0x20
108 #define DATA_DIR_TX (1 << 0)
109 #define DATA_DIR_RX (1 << 1)
111 #define MAX_CHIP_SELECT 4
112 #define SPI_FIFO_DEPTH 4
113 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
115 struct tegra_sflash_data {
117 struct spi_master *master;
121 struct reset_control *rst;
124 u32 spi_max_frequency;
127 struct spi_device *cur_spi;
130 unsigned bytes_per_word;
131 unsigned cur_direction;
132 unsigned curr_xfer_words;
145 struct completion xfer_completion;
146 struct spi_transfer *curr_xfer;
149 static int tegra_sflash_runtime_suspend(struct device *dev);
150 static int tegra_sflash_runtime_resume(struct device *dev);
152 static inline unsigned long tegra_sflash_readl(struct tegra_sflash_data *tsd,
155 return readl(tsd->base + reg);
158 static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,
159 unsigned long val, unsigned long reg)
161 writel(val, tsd->base + reg);
164 static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd)
166 /* Write 1 to clear status register */
167 tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS);
170 static unsigned tegra_sflash_calculate_curr_xfer_param(
171 struct spi_device *spi, struct tegra_sflash_data *tsd,
172 struct spi_transfer *t)
174 unsigned remain_len = t->len - tsd->cur_pos;
177 tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
178 max_word = remain_len / tsd->bytes_per_word;
179 if (max_word > SPI_FIFO_DEPTH)
180 max_word = SPI_FIFO_DEPTH;
181 tsd->curr_xfer_words = max_word;
185 static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
186 struct tegra_sflash_data *tsd, struct spi_transfer *t)
189 unsigned long status;
190 unsigned max_n_32bit = tsd->curr_xfer_words;
191 u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;
193 if (max_n_32bit > SPI_FIFO_DEPTH)
194 max_n_32bit = SPI_FIFO_DEPTH;
195 nbytes = max_n_32bit * tsd->bytes_per_word;
197 status = tegra_sflash_readl(tsd, SPI_STATUS);
198 while (!(status & SPI_TXF_FULL)) {
202 for (i = 0; nbytes && (i < tsd->bytes_per_word);
204 x |= ((*tx_buf++) << i*8);
205 tegra_sflash_writel(tsd, x, SPI_TX_FIFO);
209 status = tegra_sflash_readl(tsd, SPI_STATUS);
211 tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word;
215 static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
216 struct tegra_sflash_data *tsd, struct spi_transfer *t)
218 unsigned long status;
219 unsigned int read_words = 0;
220 u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;
222 status = tegra_sflash_readl(tsd, SPI_STATUS);
223 while (!(status & SPI_RXF_EMPTY)) {
227 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
228 for (i = 0; (i < tsd->bytes_per_word); i++)
229 *rx_buf++ = (x >> (i*8)) & 0xFF;
231 status = tegra_sflash_readl(tsd, SPI_STATUS);
233 tsd->cur_rx_pos += read_words * tsd->bytes_per_word;
237 static int tegra_sflash_start_cpu_based_transfer(
238 struct tegra_sflash_data *tsd, struct spi_transfer *t)
240 unsigned long val = 0;
243 if (tsd->cur_direction & DATA_DIR_TX)
246 if (tsd->cur_direction & DATA_DIR_RX)
249 tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
250 tsd->dma_control_reg = val;
252 if (tsd->cur_direction & DATA_DIR_TX)
253 cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t);
255 cur_words = tsd->curr_xfer_words;
256 val |= SPI_DMA_BLK_COUNT(cur_words);
257 tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
258 tsd->dma_control_reg = val;
260 tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
264 static int tegra_sflash_start_transfer_one(struct spi_device *spi,
265 struct spi_transfer *t, bool is_first_of_msg,
268 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
270 unsigned long command;
273 if (speed != tsd->cur_speed) {
274 clk_set_rate(tsd->clk, speed);
275 tsd->cur_speed = speed;
283 tegra_sflash_calculate_curr_xfer_param(spi, tsd, t);
284 if (is_first_of_msg) {
285 command = tsd->def_command_reg;
286 command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
287 command |= SPI_CS_VAL_HIGH;
289 command &= ~SPI_MODES;
290 if (spi->mode & SPI_CPHA)
291 command |= SPI_CK_SDA_FALLING;
293 if (spi->mode & SPI_CPOL)
294 command |= SPI_ACTIVE_SCLK_DRIVE_HIGH;
296 command |= SPI_ACTIVE_SCLK_DRIVE_LOW;
297 command |= SPI_CS0_EN << spi->chip_select;
299 command = tsd->command_reg;
300 command &= ~SPI_BIT_LENGTH(~0);
301 command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
302 command &= ~(SPI_RX_EN | SPI_TX_EN);
305 tsd->cur_direction = 0;
307 command |= SPI_RX_EN;
308 tsd->cur_direction |= DATA_DIR_RX;
311 command |= SPI_TX_EN;
312 tsd->cur_direction |= DATA_DIR_TX;
314 tegra_sflash_writel(tsd, command, SPI_COMMAND);
315 tsd->command_reg = command;
317 return tegra_sflash_start_cpu_based_transfer(tsd, t);
320 static int tegra_sflash_setup(struct spi_device *spi)
322 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
324 /* Set speed to the spi max fequency if spi device has not set */
325 spi->max_speed_hz = spi->max_speed_hz ? : tsd->spi_max_frequency;
329 static int tegra_sflash_transfer_one_message(struct spi_master *master,
330 struct spi_message *msg)
332 bool is_first_msg = true;
334 struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
335 struct spi_transfer *xfer;
336 struct spi_device *spi = msg->spi;
340 msg->actual_length = 0;
341 single_xfer = list_is_singular(&msg->transfers);
342 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
343 reinit_completion(&tsd->xfer_completion);
344 ret = tegra_sflash_start_transfer_one(spi, xfer,
345 is_first_msg, single_xfer);
348 "spi can not start transfer, err %d\n", ret);
351 is_first_msg = false;
352 ret = wait_for_completion_timeout(&tsd->xfer_completion,
354 if (WARN_ON(ret == 0)) {
356 "spi trasfer timeout, err %d\n", ret);
361 if (tsd->tx_status || tsd->rx_status) {
362 dev_err(tsd->dev, "Error in Transfer\n");
366 msg->actual_length += xfer->len;
367 if (xfer->cs_change && xfer->delay_usecs) {
368 tegra_sflash_writel(tsd, tsd->def_command_reg,
370 udelay(xfer->delay_usecs);
375 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
377 spi_finalize_current_message(master);
381 static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
383 struct spi_transfer *t = tsd->curr_xfer;
386 spin_lock_irqsave(&tsd->lock, flags);
387 if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) {
389 "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg);
391 "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
392 tsd->dma_control_reg);
393 reset_control_assert(tsd->rst);
395 reset_control_deassert(tsd->rst);
396 complete(&tsd->xfer_completion);
400 if (tsd->cur_direction & DATA_DIR_RX)
401 tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t);
403 if (tsd->cur_direction & DATA_DIR_TX)
404 tsd->cur_pos = tsd->cur_tx_pos;
406 tsd->cur_pos = tsd->cur_rx_pos;
408 if (tsd->cur_pos == t->len) {
409 complete(&tsd->xfer_completion);
413 tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t);
414 tegra_sflash_start_cpu_based_transfer(tsd, t);
416 spin_unlock_irqrestore(&tsd->lock, flags);
420 static irqreturn_t tegra_sflash_isr(int irq, void *context_data)
422 struct tegra_sflash_data *tsd = context_data;
424 tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS);
425 if (tsd->cur_direction & DATA_DIR_TX)
426 tsd->tx_status = tsd->status_reg & SPI_TX_OVF;
428 if (tsd->cur_direction & DATA_DIR_RX)
429 tsd->rx_status = tsd->status_reg & SPI_RX_UNF;
430 tegra_sflash_clear_status(tsd);
432 return handle_cpu_based_xfer(tsd);
435 static void tegra_sflash_parse_dt(struct tegra_sflash_data *tsd)
437 struct device_node *np = tsd->dev->of_node;
439 if (of_property_read_u32(np, "spi-max-frequency",
440 &tsd->spi_max_frequency))
441 tsd->spi_max_frequency = 25000000; /* 25MHz */
444 static struct of_device_id tegra_sflash_of_match[] = {
445 { .compatible = "nvidia,tegra20-sflash", },
448 MODULE_DEVICE_TABLE(of, tegra_sflash_of_match);
450 static int tegra_sflash_probe(struct platform_device *pdev)
452 struct spi_master *master;
453 struct tegra_sflash_data *tsd;
456 const struct of_device_id *match;
458 match = of_match_device(tegra_sflash_of_match, &pdev->dev);
460 dev_err(&pdev->dev, "Error: No device match found\n");
464 master = spi_alloc_master(&pdev->dev, sizeof(*tsd));
466 dev_err(&pdev->dev, "master allocation failed\n");
470 /* the spi->mode bits understood by this driver: */
471 master->mode_bits = SPI_CPOL | SPI_CPHA;
472 master->setup = tegra_sflash_setup;
473 master->transfer_one_message = tegra_sflash_transfer_one_message;
474 master->auto_runtime_pm = true;
475 master->num_chipselect = MAX_CHIP_SELECT;
476 master->bus_num = -1;
478 platform_set_drvdata(pdev, master);
479 tsd = spi_master_get_devdata(master);
480 tsd->master = master;
481 tsd->dev = &pdev->dev;
482 spin_lock_init(&tsd->lock);
484 tegra_sflash_parse_dt(tsd);
486 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
487 tsd->base = devm_ioremap_resource(&pdev->dev, r);
488 if (IS_ERR(tsd->base)) {
489 ret = PTR_ERR(tsd->base);
490 goto exit_free_master;
493 tsd->irq = platform_get_irq(pdev, 0);
494 ret = request_irq(tsd->irq, tegra_sflash_isr, 0,
495 dev_name(&pdev->dev), tsd);
497 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
499 goto exit_free_master;
502 tsd->clk = devm_clk_get(&pdev->dev, NULL);
503 if (IS_ERR(tsd->clk)) {
504 dev_err(&pdev->dev, "can not get clock\n");
505 ret = PTR_ERR(tsd->clk);
509 tsd->rst = devm_reset_control_get(&pdev->dev, "spi");
510 if (IS_ERR(tsd->rst)) {
511 dev_err(&pdev->dev, "can not get reset\n");
512 ret = PTR_ERR(tsd->rst);
516 init_completion(&tsd->xfer_completion);
517 pm_runtime_enable(&pdev->dev);
518 if (!pm_runtime_enabled(&pdev->dev)) {
519 ret = tegra_sflash_runtime_resume(&pdev->dev);
521 goto exit_pm_disable;
524 ret = pm_runtime_get_sync(&pdev->dev);
526 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
527 goto exit_pm_disable;
530 /* Reset controller */
531 reset_control_assert(tsd->rst);
533 reset_control_deassert(tsd->rst);
535 tsd->def_command_reg = SPI_M_S | SPI_CS_SW;
536 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
537 pm_runtime_put(&pdev->dev);
539 master->dev.of_node = pdev->dev.of_node;
540 ret = devm_spi_register_master(&pdev->dev, master);
542 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
543 goto exit_pm_disable;
548 pm_runtime_disable(&pdev->dev);
549 if (!pm_runtime_status_suspended(&pdev->dev))
550 tegra_sflash_runtime_suspend(&pdev->dev);
552 free_irq(tsd->irq, tsd);
554 spi_master_put(master);
558 static int tegra_sflash_remove(struct platform_device *pdev)
560 struct spi_master *master = platform_get_drvdata(pdev);
561 struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
563 free_irq(tsd->irq, tsd);
565 pm_runtime_disable(&pdev->dev);
566 if (!pm_runtime_status_suspended(&pdev->dev))
567 tegra_sflash_runtime_suspend(&pdev->dev);
572 #ifdef CONFIG_PM_SLEEP
573 static int tegra_sflash_suspend(struct device *dev)
575 struct spi_master *master = dev_get_drvdata(dev);
577 return spi_master_suspend(master);
580 static int tegra_sflash_resume(struct device *dev)
582 struct spi_master *master = dev_get_drvdata(dev);
583 struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
586 ret = pm_runtime_get_sync(dev);
588 dev_err(dev, "pm runtime failed, e = %d\n", ret);
591 tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND);
594 return spi_master_resume(master);
598 static int tegra_sflash_runtime_suspend(struct device *dev)
600 struct spi_master *master = dev_get_drvdata(dev);
601 struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
603 /* Flush all write which are in PPSB queue by reading back */
604 tegra_sflash_readl(tsd, SPI_COMMAND);
606 clk_disable_unprepare(tsd->clk);
610 static int tegra_sflash_runtime_resume(struct device *dev)
612 struct spi_master *master = dev_get_drvdata(dev);
613 struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
616 ret = clk_prepare_enable(tsd->clk);
618 dev_err(tsd->dev, "clk_prepare failed: %d\n", ret);
624 static const struct dev_pm_ops slink_pm_ops = {
625 SET_RUNTIME_PM_OPS(tegra_sflash_runtime_suspend,
626 tegra_sflash_runtime_resume, NULL)
627 SET_SYSTEM_SLEEP_PM_OPS(tegra_sflash_suspend, tegra_sflash_resume)
629 static struct platform_driver tegra_sflash_driver = {
631 .name = "spi-tegra-sflash",
632 .owner = THIS_MODULE,
634 .of_match_table = tegra_sflash_of_match,
636 .probe = tegra_sflash_probe,
637 .remove = tegra_sflash_remove,
639 module_platform_driver(tegra_sflash_driver);
641 MODULE_ALIAS("platform:spi-tegra-sflash");
642 MODULE_DESCRIPTION("NVIDIA Tegra20 Serial Flash Controller Driver");
643 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
644 MODULE_LICENSE("GPL v2");