drivers/spi/spi-tegra114.c

   1 /*
   2  * SPI driver for NVIDIA's Tegra114 SPI Controller.
   3  *
   4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/delay.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/dmapool.h>
  25 #include <linux/err.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kernel.h>
  30 #include <linux/kthread.h>
  31 #include <linux/module.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36 #include <linux/reset.h>
  37 #include <linux/spi/spi.h>
  38
  39 #define SPI_COMMAND1                            0x000
  40 #define SPI_BIT_LENGTH(x)                       (((x) & 0x1f) << 0)
  41 #define SPI_PACKED                              (1 << 5)
  42 #define SPI_TX_EN                               (1 << 11)
  43 #define SPI_RX_EN                               (1 << 12)
  44 #define SPI_BOTH_EN_BYTE                        (1 << 13)
  45 #define SPI_BOTH_EN_BIT                         (1 << 14)
  46 #define SPI_LSBYTE_FE                           (1 << 15)
  47 #define SPI_LSBIT_FE                            (1 << 16)
  48 #define SPI_BIDIROE                             (1 << 17)
  49 #define SPI_IDLE_SDA_DRIVE_LOW                  (0 << 18)
  50 #define SPI_IDLE_SDA_DRIVE_HIGH                 (1 << 18)
  51 #define SPI_IDLE_SDA_PULL_LOW                   (2 << 18)
  52 #define SPI_IDLE_SDA_PULL_HIGH                  (3 << 18)
  53 #define SPI_IDLE_SDA_MASK                       (3 << 18)
  54 #define SPI_CS_SS_VAL                           (1 << 20)
  55 #define SPI_CS_SW_HW                            (1 << 21)
  56 /* SPI_CS_POL_INACTIVE bits are default high */
  57                                                 /* n from 0 to 3 */
  58 #define SPI_CS_POL_INACTIVE(n)                  (1 << (22 + (n)))
  59 #define SPI_CS_POL_INACTIVE_MASK                (0xF << 22)
  60
  61 #define SPI_CS_SEL_0                            (0 << 26)
  62 #define SPI_CS_SEL_1                            (1 << 26)
  63 #define SPI_CS_SEL_2                            (2 << 26)
  64 #define SPI_CS_SEL_3                            (3 << 26)
  65 #define SPI_CS_SEL_MASK                         (3 << 26)
  66 #define SPI_CS_SEL(x)                           (((x) & 0x3) << 26)
  67 #define SPI_CONTROL_MODE_0                      (0 << 28)
  68 #define SPI_CONTROL_MODE_1                      (1 << 28)
  69 #define SPI_CONTROL_MODE_2                      (2 << 28)
  70 #define SPI_CONTROL_MODE_3                      (3 << 28)
  71 #define SPI_CONTROL_MODE_MASK                   (3 << 28)
  72 #define SPI_MODE_SEL(x)                         (((x) & 0x3) << 28)
  73 #define SPI_M_S                                 (1 << 30)
  74 #define SPI_PIO                                 (1 << 31)
  75
  76 #define SPI_COMMAND2                            0x004
  77 #define SPI_TX_TAP_DELAY(x)                     (((x) & 0x3F) << 6)
  78 #define SPI_RX_TAP_DELAY(x)                     (((x) & 0x3F) << 0)
  79
  80 #define SPI_CS_TIMING1                          0x008
  81 #define SPI_SETUP_HOLD(setup, hold)             (((setup) << 4) | (hold))
  82 #define SPI_CS_SETUP_HOLD(reg, cs, val)                 \
  83                 ((((val) & 0xFFu) << ((cs) * 8)) |      \
  84                 ((reg) & ~(0xFFu << ((cs) * 8))))
  85
  86 #define SPI_CS_TIMING2                          0x00C
  87 #define CYCLES_BETWEEN_PACKETS_0(x)             (((x) & 0x1F) << 0)
  88 #define CS_ACTIVE_BETWEEN_PACKETS_0             (1 << 5)
  89 #define CYCLES_BETWEEN_PACKETS_1(x)             (((x) & 0x1F) << 8)
  90 #define CS_ACTIVE_BETWEEN_PACKETS_1             (1 << 13)
  91 #define CYCLES_BETWEEN_PACKETS_2(x)             (((x) & 0x1F) << 16)
  92 #define CS_ACTIVE_BETWEEN_PACKETS_2             (1 << 21)
  93 #define CYCLES_BETWEEN_PACKETS_3(x)             (((x) & 0x1F) << 24)
  94 #define CS_ACTIVE_BETWEEN_PACKETS_3             (1 << 29)
  95 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val)         \
  96                 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) |      \
  97                         ((reg) & ~(1 << ((cs) * 8 + 5))))
  98 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)            \
  99                 (reg = (((val) & 0xF) << ((cs) * 8)) |          \
 100                         ((reg) & ~(0xF << ((cs) * 8))))
 101
 102 #define SPI_TRANS_STATUS                        0x010
 103 #define SPI_BLK_CNT(val)                        (((val) >> 0) & 0xFFFF)
 104 #define SPI_SLV_IDLE_COUNT(val)                 (((val) >> 16) & 0xFF)
 105 #define SPI_RDY                                 (1 << 30)
 106
 107 #define SPI_FIFO_STATUS                         0x014
 108 #define SPI_RX_FIFO_EMPTY                       (1 << 0)
 109 #define SPI_RX_FIFO_FULL                        (1 << 1)
 110 #define SPI_TX_FIFO_EMPTY                       (1 << 2)
 111 #define SPI_TX_FIFO_FULL                        (1 << 3)
 112 #define SPI_RX_FIFO_UNF                         (1 << 4)
 113 #define SPI_RX_FIFO_OVF                         (1 << 5)
 114 #define SPI_TX_FIFO_UNF                         (1 << 6)
 115 #define SPI_TX_FIFO_OVF                         (1 << 7)
 116 #define SPI_ERR                                 (1 << 8)
 117 #define SPI_TX_FIFO_FLUSH                       (1 << 14)
 118 #define SPI_RX_FIFO_FLUSH                       (1 << 15)
 119 #define SPI_TX_FIFO_EMPTY_COUNT(val)            (((val) >> 16) & 0x7F)
 120 #define SPI_RX_FIFO_FULL_COUNT(val)             (((val) >> 23) & 0x7F)
 121 #define SPI_FRAME_END                           (1 << 30)
 122 #define SPI_CS_INACTIVE                         (1 << 31)
 123
 124 #define SPI_FIFO_ERROR                          (SPI_RX_FIFO_UNF | \
 125                         SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
 126 #define SPI_FIFO_EMPTY                  (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
 127
 128 #define SPI_TX_DATA                             0x018
 129 #define SPI_RX_DATA                             0x01C
 130
 131 #define SPI_DMA_CTL                             0x020
 132 #define SPI_TX_TRIG_1                           (0 << 15)
 133 #define SPI_TX_TRIG_4                           (1 << 15)
 134 #define SPI_TX_TRIG_8                           (2 << 15)
 135 #define SPI_TX_TRIG_16                          (3 << 15)
 136 #define SPI_TX_TRIG_MASK                        (3 << 15)
 137 #define SPI_RX_TRIG_1                           (0 << 19)
 138 #define SPI_RX_TRIG_4                           (1 << 19)
 139 #define SPI_RX_TRIG_8                           (2 << 19)
 140 #define SPI_RX_TRIG_16                          (3 << 19)
 141 #define SPI_RX_TRIG_MASK                        (3 << 19)
 142 #define SPI_IE_TX                               (1 << 28)
 143 #define SPI_IE_RX                               (1 << 29)
 144 #define SPI_CONT                                (1 << 30)
 145 #define SPI_DMA                                 (1 << 31)
 146 #define SPI_DMA_EN                              SPI_DMA
 147
 148 #define SPI_DMA_BLK                             0x024
 149 #define SPI_DMA_BLK_SET(x)                      (((x) & 0xFFFF) << 0)
 150
 151 #define SPI_TX_FIFO                             0x108
 152 #define SPI_RX_FIFO                             0x188
 153 #define MAX_CHIP_SELECT                         4
 154 #define SPI_FIFO_DEPTH                          64
 155 #define DATA_DIR_TX                             (1 << 0)
 156 #define DATA_DIR_RX                             (1 << 1)
 157
 158 #define SPI_DMA_TIMEOUT                         (msecs_to_jiffies(1000))
 159 #define DEFAULT_SPI_DMA_BUF_LEN                 (16*1024)
 160 #define TX_FIFO_EMPTY_COUNT_MAX                 SPI_TX_FIFO_EMPTY_COUNT(0x40)
 161 #define RX_FIFO_FULL_COUNT_ZERO                 SPI_RX_FIFO_FULL_COUNT(0)
 162 #define MAX_HOLD_CYCLES                         16
 163 #define SPI_DEFAULT_SPEED                       25000000
 164
 165 struct tegra_spi_data {
 166         struct device                           *dev;
 167         struct spi_master                       *master;
 168         spinlock_t                              lock;
 169
 170         struct clk                              *clk;
 171         struct reset_control                    *rst;
 172         void __iomem                            *base;
 173         phys_addr_t                             phys;
 174         unsigned                                irq;
 175         u32                                     cur_speed;
 176
 177         struct spi_device                       *cur_spi;
 178         struct spi_device                       *cs_control;
 179         unsigned                                cur_pos;
 180         unsigned                                words_per_32bit;
 181         unsigned                                bytes_per_word;
 182         unsigned                                curr_dma_words;
 183         unsigned                                cur_direction;
 184
 185         unsigned                                cur_rx_pos;
 186         unsigned                                cur_tx_pos;
 187
 188         unsigned                                dma_buf_size;
 189         unsigned                                max_buf_size;
 190         bool                                    is_curr_dma_xfer;
 191
 192         struct completion                       rx_dma_complete;
 193         struct completion                       tx_dma_complete;
 194
 195         u32                                     tx_status;
 196         u32                                     rx_status;
 197         u32                                     status_reg;
 198         bool                                    is_packed;
 199
 200         u32                                     command1_reg;
 201         u32                                     dma_control_reg;
 202         u32                                     def_command1_reg;
 203
 204         struct completion                       xfer_completion;
 205         struct spi_transfer                     *curr_xfer;
 206         struct dma_chan                         *rx_dma_chan;
 207         u32                                     *rx_dma_buf;
 208         dma_addr_t                              rx_dma_phys;
 209         struct dma_async_tx_descriptor          *rx_dma_desc;
 210
 211         struct dma_chan                         *tx_dma_chan;
 212         u32                                     *tx_dma_buf;
 213         dma_addr_t                              tx_dma_phys;
 214         struct dma_async_tx_descriptor          *tx_dma_desc;
 215 };
 216
 217 static int tegra_spi_runtime_suspend(struct device *dev);
 218 static int tegra_spi_runtime_resume(struct device *dev);
 219
 220 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
 221                 unsigned long reg)
 222 {
 223         return readl(tspi->base + reg);
 224 }
 225
 226 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
 227                 u32 val, unsigned long reg)
 228 {
 229         writel(val, tspi->base + reg);
 230
 231         /* Read back register to make sure that register writes completed */
 232         if (reg != SPI_TX_FIFO)
 233                 readl(tspi->base + SPI_COMMAND1);
 234 }
 235
 236 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
 237 {
 238         u32 val;
 239
 240         /* Write 1 to clear status register */
 241         val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
 242         tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
 243
 244         /* Clear fifo status error if any */
 245         val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 246         if (val & SPI_ERR)
 247                 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
 248                                 SPI_FIFO_STATUS);
 249 }
 250
 251 static unsigned tegra_spi_calculate_curr_xfer_param(
 252         struct spi_device *spi, struct tegra_spi_data *tspi,
 253         struct spi_transfer *t)
 254 {
 255         unsigned remain_len = t->len - tspi->cur_pos;
 256         unsigned max_word;
 257         unsigned bits_per_word = t->bits_per_word;
 258         unsigned max_len;
 259         unsigned total_fifo_words;
 260
 261         tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
 262
 263         if (bits_per_word == 8 || bits_per_word == 16) {
 264                 tspi->is_packed = 1;
 265                 tspi->words_per_32bit = 32/bits_per_word;
 266         } else {
 267                 tspi->is_packed = 0;
 268                 tspi->words_per_32bit = 1;
 269         }
 270
 271         if (tspi->is_packed) {
 272                 max_len = min(remain_len, tspi->max_buf_size);
 273                 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
 274                 total_fifo_words = (max_len + 3) / 4;
 275         } else {
 276                 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
 277                 max_word = min(max_word, tspi->max_buf_size/4);
 278                 tspi->curr_dma_words = max_word;
 279                 total_fifo_words = max_word;
 280         }
 281         return total_fifo_words;
 282 }
 283
 284 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
 285         struct tegra_spi_data *tspi, struct spi_transfer *t)
 286 {
 287         unsigned nbytes;
 288         unsigned tx_empty_count;
 289         u32 fifo_status;
 290         unsigned max_n_32bit;
 291         unsigned i, count;
 292         unsigned int written_words;
 293         unsigned fifo_words_left;
 294         u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 295
 296         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 297         tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
 298
 299         if (tspi->is_packed) {
 300                 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
 301                 written_words = min(fifo_words_left, tspi->curr_dma_words);
 302                 nbytes = written_words * tspi->bytes_per_word;
 303                 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
 304                 for (count = 0; count < max_n_32bit; count++) {
 305                         u32 x = 0;
 306                         for (i = 0; (i < 4) && nbytes; i++, nbytes--)
 307                                 x |= (u32)(*tx_buf++) << (i * 8);
 308                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 309                 }
 310         } else {
 311                 max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
 312                 written_words = max_n_32bit;
 313                 nbytes = written_words * tspi->bytes_per_word;
 314                 for (count = 0; count < max_n_32bit; count++) {
 315                         u32 x = 0;
 316                         for (i = 0; nbytes && (i < tspi->bytes_per_word);
 317                                                         i++, nbytes--)
 318                                 x |= (u32)(*tx_buf++) << (i * 8);
 319                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 320                 }
 321         }
 322         tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
 323         return written_words;
 324 }
 325
 326 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
 327                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 328 {
 329         unsigned rx_full_count;
 330         u32 fifo_status;
 331         unsigned i, count;
 332         unsigned int read_words = 0;
 333         unsigned len;
 334         u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
 335
 336         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 337         rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
 338         if (tspi->is_packed) {
 339                 len = tspi->curr_dma_words * tspi->bytes_per_word;
 340                 for (count = 0; count < rx_full_count; count++) {
 341                         u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
 342                         for (i = 0; len && (i < 4); i++, len--)
 343                                 *rx_buf++ = (x >> i*8) & 0xFF;
 344                 }
 345                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 346                 read_words += tspi->curr_dma_words;
 347         } else {
 348                 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
 349                 for (count = 0; count < rx_full_count; count++) {
 350                         u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
 351                         for (i = 0; (i < tspi->bytes_per_word); i++)
 352                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
 353                 }
 354                 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
 355                 read_words += rx_full_count;
 356         }
 357         return read_words;
 358 }
 359
 360 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
 361                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 362 {
 363         /* Make the dma buffer to read by cpu */
 364         dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
 365                                 tspi->dma_buf_size, DMA_TO_DEVICE);
 366
 367         if (tspi->is_packed) {
 368                 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
 369                 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
 370         } else {
 371                 unsigned int i;
 372                 unsigned int count;
 373                 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 374                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
 375
 376                 for (count = 0; count < tspi->curr_dma_words; count++) {
 377                         u32 x = 0;
 378                         for (i = 0; consume && (i < tspi->bytes_per_word);
 379                                                         i++, consume--)
 380                                 x |= (u32)(*tx_buf++) << (i * 8);
 381                         tspi->tx_dma_buf[count] = x;
 382                 }
 383         }
 384         tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 385
 386         /* Make the dma buffer to read by dma */
 387         dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
 388                                 tspi->dma_buf_size, DMA_TO_DEVICE);
 389 }
 390
 391 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
 392                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 393 {
 394         /* Make the dma buffer to read by cpu */
 395         dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
 396                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 397
 398         if (tspi->is_packed) {
 399                 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
 400                 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
 401         } else {
 402                 unsigned int i;
 403                 unsigned int count;
 404                 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
 405                 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
 406
 407                 for (count = 0; count < tspi->curr_dma_words; count++) {
 408                         u32 x = tspi->rx_dma_buf[count] & rx_mask;
 409                         for (i = 0; (i < tspi->bytes_per_word); i++)
 410                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
 411                 }
 412         }
 413         tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 414
 415         /* Make the dma buffer to read by dma */
 416         dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 417                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 418 }
 419
 420 static void tegra_spi_dma_complete(void *args)
 421 {
 422         struct completion *dma_complete = args;
 423
 424         complete(dma_complete);
 425 }
 426
 427 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
 428 {
 429         reinit_completion(&tspi->tx_dma_complete);
 430         tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
 431                                 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
 432                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 433         if (!tspi->tx_dma_desc) {
 434                 dev_err(tspi->dev, "Not able to get desc for Tx\n");
 435                 return -EIO;
 436         }
 437
 438         tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
 439         tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
 440
 441         dmaengine_submit(tspi->tx_dma_desc);
 442         dma_async_issue_pending(tspi->tx_dma_chan);
 443         return 0;
 444 }
 445
 446 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
 447 {
 448         reinit_completion(&tspi->rx_dma_complete);
 449         tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
 450                                 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
 451                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 452         if (!tspi->rx_dma_desc) {
 453                 dev_err(tspi->dev, "Not able to get desc for Rx\n");
 454                 return -EIO;
 455         }
 456
 457         tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
 458         tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
 459
 460         dmaengine_submit(tspi->rx_dma_desc);
 461         dma_async_issue_pending(tspi->rx_dma_chan);
 462         return 0;
 463 }
 464
 465 static int tegra_spi_start_dma_based_transfer(
 466                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 467 {
 468         u32 val;
 469         unsigned int len;
 470         int ret = 0;
 471         u32 status;
 472
 473         /* Make sure that Rx and Tx fifo are empty */
 474         status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 475         if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
 476                 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
 477                         (unsigned)status);
 478                 return -EIO;
 479         }
 480
 481         val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
 482         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 483
 484         if (tspi->is_packed)
 485                 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
 486                                         4) * 4;
 487         else
 488                 len = tspi->curr_dma_words * 4;
 489
 490         /* Set attention level based on length of transfer */
 491         if (len & 0xF)
 492                 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
 493         else if (((len) >> 4) & 0x1)
 494                 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
 495         else
 496                 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
 497
 498         if (tspi->cur_direction & DATA_DIR_TX)
 499                 val |= SPI_IE_TX;
 500
 501         if (tspi->cur_direction & DATA_DIR_RX)
 502                 val |= SPI_IE_RX;
 503
 504         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 505         tspi->dma_control_reg = val;
 506
 507         if (tspi->cur_direction & DATA_DIR_TX) {
 508                 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
 509                 ret = tegra_spi_start_tx_dma(tspi, len);
 510                 if (ret < 0) {
 511                         dev_err(tspi->dev,
 512                                 "Starting tx dma failed, err %d\n", ret);
 513                         return ret;
 514                 }
 515         }
 516
 517         if (tspi->cur_direction & DATA_DIR_RX) {
 518                 /* Make the dma buffer to read by dma */
 519                 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 520                                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 521
 522                 ret = tegra_spi_start_rx_dma(tspi, len);
 523                 if (ret < 0) {
 524                         dev_err(tspi->dev,
 525                                 "Starting rx dma failed, err %d\n", ret);
 526                         if (tspi->cur_direction & DATA_DIR_TX)
 527                                 dmaengine_terminate_all(tspi->tx_dma_chan);
 528                         return ret;
 529                 }
 530         }
 531         tspi->is_curr_dma_xfer = true;
 532         tspi->dma_control_reg = val;
 533
 534         val |= SPI_DMA_EN;
 535         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 536         return ret;
 537 }
 538
 539 static int tegra_spi_start_cpu_based_transfer(
 540                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 541 {
 542         u32 val;
 543         unsigned cur_words;
 544
 545         if (tspi->cur_direction & DATA_DIR_TX)
 546                 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
 547         else
 548                 cur_words = tspi->curr_dma_words;
 549
 550         val = SPI_DMA_BLK_SET(cur_words - 1);
 551         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 552
 553         val = 0;
 554         if (tspi->cur_direction & DATA_DIR_TX)
 555                 val |= SPI_IE_TX;
 556
 557         if (tspi->cur_direction & DATA_DIR_RX)
 558                 val |= SPI_IE_RX;
 559
 560         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 561         tspi->dma_control_reg = val;
 562
 563         tspi->is_curr_dma_xfer = false;
 564
 565         val |= SPI_DMA_EN;
 566         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 567         return 0;
 568 }
 569
 570 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
 571                         bool dma_to_memory)
 572 {
 573         struct dma_chan *dma_chan;
 574         u32 *dma_buf;
 575         dma_addr_t dma_phys;
 576         int ret;
 577         struct dma_slave_config dma_sconfig;
 578
 579         dma_chan = dma_request_slave_channel_reason(tspi->dev,
 580                                         dma_to_memory ? "rx" : "tx");
 581         if (IS_ERR(dma_chan)) {
 582                 ret = PTR_ERR(dma_chan);
 583                 if (ret != -EPROBE_DEFER)
 584                         dev_err(tspi->dev,
 585                                 "Dma channel is not available: %d\n", ret);
 586                 return ret;
 587         }
 588
 589         dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
 590                                 &dma_phys, GFP_KERNEL);
 591         if (!dma_buf) {
 592                 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
 593                 dma_release_channel(dma_chan);
 594                 return -ENOMEM;
 595         }
 596
 597         if (dma_to_memory) {
 598                 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
 599                 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 600                 dma_sconfig.src_maxburst = 0;
 601         } else {
 602                 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
 603                 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 604                 dma_sconfig.dst_maxburst = 0;
 605         }
 606
 607         ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
 608         if (ret)
 609                 goto scrub;
 610         if (dma_to_memory) {
 611                 tspi->rx_dma_chan = dma_chan;
 612                 tspi->rx_dma_buf = dma_buf;
 613                 tspi->rx_dma_phys = dma_phys;
 614         } else {
 615                 tspi->tx_dma_chan = dma_chan;
 616                 tspi->tx_dma_buf = dma_buf;
 617                 tspi->tx_dma_phys = dma_phys;
 618         }
 619         return 0;
 620
 621 scrub:
 622         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 623         dma_release_channel(dma_chan);
 624         return ret;
 625 }
 626
 627 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 628         bool dma_to_memory)
 629 {
 630         u32 *dma_buf;
 631         dma_addr_t dma_phys;
 632         struct dma_chan *dma_chan;
 633
 634         if (dma_to_memory) {
 635                 dma_buf = tspi->rx_dma_buf;
 636                 dma_chan = tspi->rx_dma_chan;
 637                 dma_phys = tspi->rx_dma_phys;
 638                 tspi->rx_dma_chan = NULL;
 639                 tspi->rx_dma_buf = NULL;
 640         } else {
 641                 dma_buf = tspi->tx_dma_buf;
 642                 dma_chan = tspi->tx_dma_chan;
 643                 dma_phys = tspi->tx_dma_phys;
 644                 tspi->tx_dma_buf = NULL;
 645                 tspi->tx_dma_chan = NULL;
 646         }
 647         if (!dma_chan)
 648                 return;
 649
 650         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 651         dma_release_channel(dma_chan);
 652 }
 653
 654 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 655                 struct spi_transfer *t, bool is_first_of_msg)
 656 {
 657         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 658         u32 speed = t->speed_hz;
 659         u8 bits_per_word = t->bits_per_word;
 660         u32 command1;
 661         int req_mode;
 662
 663         if (speed != tspi->cur_speed) {
 664                 clk_set_rate(tspi->clk, speed);
 665                 tspi->cur_speed = speed;
 666         }
 667
 668         tspi->cur_spi = spi;
 669         tspi->cur_pos = 0;
 670         tspi->cur_rx_pos = 0;
 671         tspi->cur_tx_pos = 0;
 672         tspi->curr_xfer = t;
 673
 674         if (is_first_of_msg) {
 675                 tegra_spi_clear_status(tspi);
 676
 677                 command1 = tspi->def_command1_reg;
 678                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 679
 680                 command1 &= ~SPI_CONTROL_MODE_MASK;
 681                 req_mode = spi->mode & 0x3;
 682                 if (req_mode == SPI_MODE_0)
 683                         command1 |= SPI_CONTROL_MODE_0;
 684                 else if (req_mode == SPI_MODE_1)
 685                         command1 |= SPI_CONTROL_MODE_1;
 686                 else if (req_mode == SPI_MODE_2)
 687                         command1 |= SPI_CONTROL_MODE_2;
 688                 else if (req_mode == SPI_MODE_3)
 689                         command1 |= SPI_CONTROL_MODE_3;
 690
 691                 if (tspi->cs_control) {
 692                         if (tspi->cs_control != spi)
 693                                 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 694                         tspi->cs_control = NULL;
 695                 } else
 696                         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 697
 698                 command1 |= SPI_CS_SW_HW;
 699                 if (spi->mode & SPI_CS_HIGH)
 700                         command1 |= SPI_CS_SS_VAL;
 701                 else
 702                         command1 &= ~SPI_CS_SS_VAL;
 703
 704                 tegra_spi_writel(tspi, 0, SPI_COMMAND2);
 705         } else {
 706                 command1 = tspi->command1_reg;
 707                 command1 &= ~SPI_BIT_LENGTH(~0);
 708                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 709         }
 710
 711         return command1;
 712 }
 713
 714 static int tegra_spi_start_transfer_one(struct spi_device *spi,
 715                 struct spi_transfer *t, u32 command1)
 716 {
 717         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 718         unsigned total_fifo_words;
 719         int ret;
 720
 721         total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
 722
 723         if (tspi->is_packed)
 724                 command1 |= SPI_PACKED;
 725
 726         command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
 727         tspi->cur_direction = 0;
 728         if (t->rx_buf) {
 729                 command1 |= SPI_RX_EN;
 730                 tspi->cur_direction |= DATA_DIR_RX;
 731         }
 732         if (t->tx_buf) {
 733                 command1 |= SPI_TX_EN;
 734                 tspi->cur_direction |= DATA_DIR_TX;
 735         }
 736         command1 |= SPI_CS_SEL(spi->chip_select);
 737         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 738         tspi->command1_reg = command1;
 739
 740         dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
 741                 tspi->def_command1_reg, (unsigned)command1);
 742
 743         if (total_fifo_words > SPI_FIFO_DEPTH)
 744                 ret = tegra_spi_start_dma_based_transfer(tspi, t);
 745         else
 746                 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
 747         return ret;
 748 }
 749
 750 static int tegra_spi_setup(struct spi_device *spi)
 751 {
 752         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 753         u32 val;
 754         unsigned long flags;
 755         int ret;
 756
 757         dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
 758                 spi->bits_per_word,
 759                 spi->mode & SPI_CPOL ? "" : "~",
 760                 spi->mode & SPI_CPHA ? "" : "~",
 761                 spi->max_speed_hz);
 762
 763         ret = pm_runtime_get_sync(tspi->dev);
 764         if (ret < 0) {
 765                 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
 766                 return ret;
 767         }
 768
 769         spin_lock_irqsave(&tspi->lock, flags);
 770         val = tspi->def_command1_reg;
 771         if (spi->mode & SPI_CS_HIGH)
 772                 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
 773         else
 774                 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
 775         tspi->def_command1_reg = val;
 776         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 777         spin_unlock_irqrestore(&tspi->lock, flags);
 778
 779         pm_runtime_put(tspi->dev);
 780         return 0;
 781 }
 782
 783 static void tegra_spi_transfer_delay(int delay)
 784 {
 785         if (!delay)
 786                 return;
 787
 788         if (delay >= 1000)
 789                 mdelay(delay / 1000);
 790
 791         udelay(delay % 1000);
 792 }
 793
 794 static int tegra_spi_transfer_one_message(struct spi_master *master,
 795                         struct spi_message *msg)
 796 {
 797         bool is_first_msg = true;
 798         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
 799         struct spi_transfer *xfer;
 800         struct spi_device *spi = msg->spi;
 801         int ret;
 802         bool skip = false;
 803
 804         msg->status = 0;
 805         msg->actual_length = 0;
 806
 807         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 808                 u32 cmd1;
 809
 810                 reinit_completion(&tspi->xfer_completion);
 811
 812                 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
 813
 814                 if (!xfer->len) {
 815                         ret = 0;
 816                         skip = true;
 817                         goto complete_xfer;
 818                 }
 819
 820                 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
 821                 if (ret < 0) {
 822                         dev_err(tspi->dev,
 823                                 "spi can not start transfer, err %d\n", ret);
 824                         goto complete_xfer;
 825                 }
 826
 827                 is_first_msg = false;
 828                 ret = wait_for_completion_timeout(&tspi->xfer_completion,
 829                                                 SPI_DMA_TIMEOUT);
 830                 if (WARN_ON(ret == 0)) {
 831                         dev_err(tspi->dev,
 832                                 "spi trasfer timeout, err %d\n", ret);
 833                         ret = -EIO;
 834                         goto complete_xfer;
 835                 }
 836
 837                 if (tspi->tx_status ||  tspi->rx_status) {
 838                         dev_err(tspi->dev, "Error in Transfer\n");
 839                         ret = -EIO;
 840                         goto complete_xfer;
 841                 }
 842                 msg->actual_length += xfer->len;
 843
 844 complete_xfer:
 845                 if (ret < 0 || skip) {
 846                         tegra_spi_writel(tspi, tspi->def_command1_reg,
 847                                         SPI_COMMAND1);
 848                         tegra_spi_transfer_delay(xfer->delay_usecs);
 849                         goto exit;
 850                 } else if (msg->transfers.prev == &xfer->transfer_list) {
 851                         /* This is the last transfer in message */
 852                         if (xfer->cs_change)
 853                                 tspi->cs_control = spi;
 854                         else {
 855                                 tegra_spi_writel(tspi, tspi->def_command1_reg,
 856                                                 SPI_COMMAND1);
 857                                 tegra_spi_transfer_delay(xfer->delay_usecs);
 858                         }
 859                 } else if (xfer->cs_change) {
 860                         tegra_spi_writel(tspi, tspi->def_command1_reg,
 861                                         SPI_COMMAND1);
 862                         tegra_spi_transfer_delay(xfer->delay_usecs);
 863                 }
 864
 865         }
 866         ret = 0;
 867 exit:
 868         msg->status = ret;
 869         spi_finalize_current_message(master);
 870         return ret;
 871 }
 872
 873 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
 874 {
 875         struct spi_transfer *t = tspi->curr_xfer;
 876         unsigned long flags;
 877
 878         spin_lock_irqsave(&tspi->lock, flags);
 879         if (tspi->tx_status ||  tspi->rx_status) {
 880                 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
 881                         tspi->status_reg);
 882                 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
 883                         tspi->command1_reg, tspi->dma_control_reg);
 884                 reset_control_assert(tspi->rst);
 885                 udelay(2);
 886                 reset_control_deassert(tspi->rst);
 887                 complete(&tspi->xfer_completion);
 888                 goto exit;
 889         }
 890
 891         if (tspi->cur_direction & DATA_DIR_RX)
 892                 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
 893
 894         if (tspi->cur_direction & DATA_DIR_TX)
 895                 tspi->cur_pos = tspi->cur_tx_pos;
 896         else
 897                 tspi->cur_pos = tspi->cur_rx_pos;
 898
 899         if (tspi->cur_pos == t->len) {
 900                 complete(&tspi->xfer_completion);
 901                 goto exit;
 902         }
 903
 904         tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
 905         tegra_spi_start_cpu_based_transfer(tspi, t);
 906 exit:
 907         spin_unlock_irqrestore(&tspi->lock, flags);
 908         return IRQ_HANDLED;
 909 }
 910
 911 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
 912 {
 913         struct spi_transfer *t = tspi->curr_xfer;
 914         long wait_status;
 915         int err = 0;
 916         unsigned total_fifo_words;
 917         unsigned long flags;
 918
 919         /* Abort dmas if any error */
 920         if (tspi->cur_direction & DATA_DIR_TX) {
 921                 if (tspi->tx_status) {
 922                         dmaengine_terminate_all(tspi->tx_dma_chan);
 923                         err += 1;
 924                 } else {
 925                         wait_status = wait_for_completion_interruptible_timeout(
 926                                 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
 927                         if (wait_status <= 0) {
 928                                 dmaengine_terminate_all(tspi->tx_dma_chan);
 929                                 dev_err(tspi->dev, "TxDma Xfer failed\n");
 930                                 err += 1;
 931                         }
 932                 }
 933         }
 934
 935         if (tspi->cur_direction & DATA_DIR_RX) {
 936                 if (tspi->rx_status) {
 937                         dmaengine_terminate_all(tspi->rx_dma_chan);
 938                         err += 2;
 939                 } else {
 940                         wait_status = wait_for_completion_interruptible_timeout(
 941                                 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
 942                         if (wait_status <= 0) {
 943                                 dmaengine_terminate_all(tspi->rx_dma_chan);
 944                                 dev_err(tspi->dev, "RxDma Xfer failed\n");
 945                                 err += 2;
 946                         }
 947                 }
 948         }
 949
 950         spin_lock_irqsave(&tspi->lock, flags);
 951         if (err) {
 952                 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
 953                         tspi->status_reg);
 954                 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
 955                         tspi->command1_reg, tspi->dma_control_reg);
 956                 reset_control_assert(tspi->rst);
 957                 udelay(2);
 958                 reset_control_deassert(tspi->rst);
 959                 complete(&tspi->xfer_completion);
 960                 spin_unlock_irqrestore(&tspi->lock, flags);
 961                 return IRQ_HANDLED;
 962         }
 963
 964         if (tspi->cur_direction & DATA_DIR_RX)
 965                 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
 966
 967         if (tspi->cur_direction & DATA_DIR_TX)
 968                 tspi->cur_pos = tspi->cur_tx_pos;
 969         else
 970                 tspi->cur_pos = tspi->cur_rx_pos;
 971
 972         if (tspi->cur_pos == t->len) {
 973                 complete(&tspi->xfer_completion);
 974                 goto exit;
 975         }
 976
 977         /* Continue transfer in current message */
 978         total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
 979                                                         tspi, t);
 980         if (total_fifo_words > SPI_FIFO_DEPTH)
 981                 err = tegra_spi_start_dma_based_transfer(tspi, t);
 982         else
 983                 err = tegra_spi_start_cpu_based_transfer(tspi, t);
 984
 985 exit:
 986         spin_unlock_irqrestore(&tspi->lock, flags);
 987         return IRQ_HANDLED;
 988 }
 989
 990 static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
 991 {
 992         struct tegra_spi_data *tspi = context_data;
 993
 994         if (!tspi->is_curr_dma_xfer)
 995                 return handle_cpu_based_xfer(tspi);
 996         return handle_dma_based_xfer(tspi);
 997 }
 998
 999 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1000 {
1001         struct tegra_spi_data *tspi = context_data;
1002
1003         tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1004         if (tspi->cur_direction & DATA_DIR_TX)
1005                 tspi->tx_status = tspi->status_reg &
1006                                         (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1007
1008         if (tspi->cur_direction & DATA_DIR_RX)
1009                 tspi->rx_status = tspi->status_reg &
1010                                         (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1011         tegra_spi_clear_status(tspi);
1012
1013         return IRQ_WAKE_THREAD;
1014 }
1015
1016 static struct of_device_id tegra_spi_of_match[] = {
1017         { .compatible = "nvidia,tegra114-spi", },
1018         {}
1019 };
1020 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1021
1022 static int tegra_spi_probe(struct platform_device *pdev)
1023 {
1024         struct spi_master       *master;
1025         struct tegra_spi_data   *tspi;
1026         struct resource         *r;
1027         int ret, spi_irq;
1028
1029         master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1030         if (!master) {
1031                 dev_err(&pdev->dev, "master allocation failed\n");
1032                 return -ENOMEM;
1033         }
1034         platform_set_drvdata(pdev, master);
1035         tspi = spi_master_get_devdata(master);
1036
1037         if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1038                                  &master->max_speed_hz))
1039                 master->max_speed_hz = 25000000; /* 25MHz */
1040
1041         /* the spi->mode bits understood by this driver: */
1042         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1043         master->setup = tegra_spi_setup;
1044         master->transfer_one_message = tegra_spi_transfer_one_message;
1045         master->num_chipselect = MAX_CHIP_SELECT;
1046         master->auto_runtime_pm = true;
1047
1048         tspi->master = master;
1049         tspi->dev = &pdev->dev;
1050         spin_lock_init(&tspi->lock);
1051
1052         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1053         tspi->base = devm_ioremap_resource(&pdev->dev, r);
1054         if (IS_ERR(tspi->base)) {
1055                 ret = PTR_ERR(tspi->base);
1056                 goto exit_free_master;
1057         }
1058         tspi->phys = r->start;
1059
1060         spi_irq = platform_get_irq(pdev, 0);
1061         tspi->irq = spi_irq;
1062         ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1063                         tegra_spi_isr_thread, IRQF_ONESHOT,
1064                         dev_name(&pdev->dev), tspi);
1065         if (ret < 0) {
1066                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1067                                         tspi->irq);
1068                 goto exit_free_master;
1069         }
1070
1071         tspi->clk = devm_clk_get(&pdev->dev, "spi");
1072         if (IS_ERR(tspi->clk)) {
1073                 dev_err(&pdev->dev, "can not get clock\n");
1074                 ret = PTR_ERR(tspi->clk);
1075                 goto exit_free_irq;
1076         }
1077
1078         tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
1079         if (IS_ERR(tspi->rst)) {
1080                 dev_err(&pdev->dev, "can not get reset\n");
1081                 ret = PTR_ERR(tspi->rst);
1082                 goto exit_free_irq;
1083         }
1084
1085         tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1086         tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1087
1088         ret = tegra_spi_init_dma_param(tspi, true);
1089         if (ret < 0)
1090                 goto exit_free_irq;
1091         ret = tegra_spi_init_dma_param(tspi, false);
1092         if (ret < 0)
1093                 goto exit_rx_dma_free;
1094         tspi->max_buf_size = tspi->dma_buf_size;
1095         init_completion(&tspi->tx_dma_complete);
1096         init_completion(&tspi->rx_dma_complete);
1097
1098         init_completion(&tspi->xfer_completion);
1099
1100         pm_runtime_enable(&pdev->dev);
1101         if (!pm_runtime_enabled(&pdev->dev)) {
1102                 ret = tegra_spi_runtime_resume(&pdev->dev);
1103                 if (ret)
1104                         goto exit_pm_disable;
1105         }
1106
1107         ret = pm_runtime_get_sync(&pdev->dev);
1108         if (ret < 0) {
1109                 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1110                 goto exit_pm_disable;
1111         }
1112         tspi->def_command1_reg  = SPI_M_S;
1113         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1114         pm_runtime_put(&pdev->dev);
1115
1116         master->dev.of_node = pdev->dev.of_node;
1117         ret = devm_spi_register_master(&pdev->dev, master);
1118         if (ret < 0) {
1119                 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1120                 goto exit_pm_disable;
1121         }
1122         return ret;
1123
1124 exit_pm_disable:
1125         pm_runtime_disable(&pdev->dev);
1126         if (!pm_runtime_status_suspended(&pdev->dev))
1127                 tegra_spi_runtime_suspend(&pdev->dev);
1128         tegra_spi_deinit_dma_param(tspi, false);
1129 exit_rx_dma_free:
1130         tegra_spi_deinit_dma_param(tspi, true);
1131 exit_free_irq:
1132         free_irq(spi_irq, tspi);
1133 exit_free_master:
1134         spi_master_put(master);
1135         return ret;
1136 }
1137
1138 static int tegra_spi_remove(struct platform_device *pdev)
1139 {
1140         struct spi_master *master = platform_get_drvdata(pdev);
1141         struct tegra_spi_data   *tspi = spi_master_get_devdata(master);
1142
1143         free_irq(tspi->irq, tspi);
1144
1145         if (tspi->tx_dma_chan)
1146                 tegra_spi_deinit_dma_param(tspi, false);
1147
1148         if (tspi->rx_dma_chan)
1149                 tegra_spi_deinit_dma_param(tspi, true);
1150
1151         pm_runtime_disable(&pdev->dev);
1152         if (!pm_runtime_status_suspended(&pdev->dev))
1153                 tegra_spi_runtime_suspend(&pdev->dev);
1154
1155         return 0;
1156 }
1157
1158 #ifdef CONFIG_PM_SLEEP
1159 static int tegra_spi_suspend(struct device *dev)
1160 {
1161         struct spi_master *master = dev_get_drvdata(dev);
1162
1163         return spi_master_suspend(master);
1164 }
1165
1166 static int tegra_spi_resume(struct device *dev)
1167 {
1168         struct spi_master *master = dev_get_drvdata(dev);
1169         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1170         int ret;
1171
1172         ret = pm_runtime_get_sync(dev);
1173         if (ret < 0) {
1174                 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1175                 return ret;
1176         }
1177         tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1178         pm_runtime_put(dev);
1179
1180         return spi_master_resume(master);
1181 }
1182 #endif
1183
1184 static int tegra_spi_runtime_suspend(struct device *dev)
1185 {
1186         struct spi_master *master = dev_get_drvdata(dev);
1187         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1188
1189         /* Flush all write which are in PPSB queue by reading back */
1190         tegra_spi_readl(tspi, SPI_COMMAND1);
1191
1192         clk_disable_unprepare(tspi->clk);
1193         return 0;
1194 }
1195
1196 static int tegra_spi_runtime_resume(struct device *dev)
1197 {
1198         struct spi_master *master = dev_get_drvdata(dev);
1199         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1200         int ret;
1201
1202         ret = clk_prepare_enable(tspi->clk);
1203         if (ret < 0) {
1204                 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1205                 return ret;
1206         }
1207         return 0;
1208 }
1209
1210 static const struct dev_pm_ops tegra_spi_pm_ops = {
1211         SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1212                 tegra_spi_runtime_resume, NULL)
1213         SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1214 };
1215 static struct platform_driver tegra_spi_driver = {
1216         .driver = {
1217                 .name           = "spi-tegra114",
1218                 .owner          = THIS_MODULE,
1219                 .pm             = &tegra_spi_pm_ops,
1220                 .of_match_table = tegra_spi_of_match,
1221         },
1222         .probe =        tegra_spi_probe,
1223         .remove =       tegra_spi_remove,
1224 };
1225 module_platform_driver(tegra_spi_driver);
1226
1227 MODULE_ALIAS("platform:spi-tegra114");
1228 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1229 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1230 MODULE_LICENSE("GPL v2");