drivers/spi/spi-tegra114.c

   1 /*
   2  * SPI driver for NVIDIA's Tegra114 SPI Controller.
   3  *
   4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/delay.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/dmapool.h>
  25 #include <linux/err.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kernel.h>
  29 #include <linux/kthread.h>
  30 #include <linux/module.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/reset.h>
  36 #include <linux/spi/spi.h>
  37
  38 #define SPI_COMMAND1                            0x000
  39 #define SPI_BIT_LENGTH(x)                       (((x) & 0x1f) << 0)
  40 #define SPI_PACKED                              (1 << 5)
  41 #define SPI_TX_EN                               (1 << 11)
  42 #define SPI_RX_EN                               (1 << 12)
  43 #define SPI_BOTH_EN_BYTE                        (1 << 13)
  44 #define SPI_BOTH_EN_BIT                         (1 << 14)
  45 #define SPI_LSBYTE_FE                           (1 << 15)
  46 #define SPI_LSBIT_FE                            (1 << 16)
  47 #define SPI_BIDIROE                             (1 << 17)
  48 #define SPI_IDLE_SDA_DRIVE_LOW                  (0 << 18)
  49 #define SPI_IDLE_SDA_DRIVE_HIGH                 (1 << 18)
  50 #define SPI_IDLE_SDA_PULL_LOW                   (2 << 18)
  51 #define SPI_IDLE_SDA_PULL_HIGH                  (3 << 18)
  52 #define SPI_IDLE_SDA_MASK                       (3 << 18)
  53 #define SPI_CS_SW_VAL                           (1 << 20)
  54 #define SPI_CS_SW_HW                            (1 << 21)
  55 /* SPI_CS_POL_INACTIVE bits are default high */
  56                                                 /* n from 0 to 3 */
  57 #define SPI_CS_POL_INACTIVE(n)                  (1 << (22 + (n)))
  58 #define SPI_CS_POL_INACTIVE_MASK                (0xF << 22)
  59
  60 #define SPI_CS_SEL_0                            (0 << 26)
  61 #define SPI_CS_SEL_1                            (1 << 26)
  62 #define SPI_CS_SEL_2                            (2 << 26)
  63 #define SPI_CS_SEL_3                            (3 << 26)
  64 #define SPI_CS_SEL_MASK                         (3 << 26)
  65 #define SPI_CS_SEL(x)                           (((x) & 0x3) << 26)
  66 #define SPI_CONTROL_MODE_0                      (0 << 28)
  67 #define SPI_CONTROL_MODE_1                      (1 << 28)
  68 #define SPI_CONTROL_MODE_2                      (2 << 28)
  69 #define SPI_CONTROL_MODE_3                      (3 << 28)
  70 #define SPI_CONTROL_MODE_MASK                   (3 << 28)
  71 #define SPI_MODE_SEL(x)                         (((x) & 0x3) << 28)
  72 #define SPI_M_S                                 (1 << 30)
  73 #define SPI_PIO                                 (1 << 31)
  74
  75 #define SPI_COMMAND2                            0x004
  76 #define SPI_TX_TAP_DELAY(x)                     (((x) & 0x3F) << 6)
  77 #define SPI_RX_TAP_DELAY(x)                     (((x) & 0x3F) << 0)
  78
  79 #define SPI_CS_TIMING1                          0x008
  80 #define SPI_SETUP_HOLD(setup, hold)             (((setup) << 4) | (hold))
  81 #define SPI_CS_SETUP_HOLD(reg, cs, val)                 \
  82                 ((((val) & 0xFFu) << ((cs) * 8)) |      \
  83                 ((reg) & ~(0xFFu << ((cs) * 8))))
  84
  85 #define SPI_CS_TIMING2                          0x00C
  86 #define CYCLES_BETWEEN_PACKETS_0(x)             (((x) & 0x1F) << 0)
  87 #define CS_ACTIVE_BETWEEN_PACKETS_0             (1 << 5)
  88 #define CYCLES_BETWEEN_PACKETS_1(x)             (((x) & 0x1F) << 8)
  89 #define CS_ACTIVE_BETWEEN_PACKETS_1             (1 << 13)
  90 #define CYCLES_BETWEEN_PACKETS_2(x)             (((x) & 0x1F) << 16)
  91 #define CS_ACTIVE_BETWEEN_PACKETS_2             (1 << 21)
  92 #define CYCLES_BETWEEN_PACKETS_3(x)             (((x) & 0x1F) << 24)
  93 #define CS_ACTIVE_BETWEEN_PACKETS_3             (1 << 29)
  94 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val)         \
  95                 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) |      \
  96                         ((reg) & ~(1 << ((cs) * 8 + 5))))
  97 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)            \
  98                 (reg = (((val) & 0xF) << ((cs) * 8)) |          \
  99                         ((reg) & ~(0xF << ((cs) * 8))))
 100
 101 #define SPI_TRANS_STATUS                        0x010
 102 #define SPI_BLK_CNT(val)                        (((val) >> 0) & 0xFFFF)
 103 #define SPI_SLV_IDLE_COUNT(val)                 (((val) >> 16) & 0xFF)
 104 #define SPI_RDY                                 (1 << 30)
 105
 106 #define SPI_FIFO_STATUS                         0x014
 107 #define SPI_RX_FIFO_EMPTY                       (1 << 0)
 108 #define SPI_RX_FIFO_FULL                        (1 << 1)
 109 #define SPI_TX_FIFO_EMPTY                       (1 << 2)
 110 #define SPI_TX_FIFO_FULL                        (1 << 3)
 111 #define SPI_RX_FIFO_UNF                         (1 << 4)
 112 #define SPI_RX_FIFO_OVF                         (1 << 5)
 113 #define SPI_TX_FIFO_UNF                         (1 << 6)
 114 #define SPI_TX_FIFO_OVF                         (1 << 7)
 115 #define SPI_ERR                                 (1 << 8)
 116 #define SPI_TX_FIFO_FLUSH                       (1 << 14)
 117 #define SPI_RX_FIFO_FLUSH                       (1 << 15)
 118 #define SPI_TX_FIFO_EMPTY_COUNT(val)            (((val) >> 16) & 0x7F)
 119 #define SPI_RX_FIFO_FULL_COUNT(val)             (((val) >> 23) & 0x7F)
 120 #define SPI_FRAME_END                           (1 << 30)
 121 #define SPI_CS_INACTIVE                         (1 << 31)
 122
 123 #define SPI_FIFO_ERROR                          (SPI_RX_FIFO_UNF | \
 124                         SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
 125 #define SPI_FIFO_EMPTY                  (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
 126
 127 #define SPI_TX_DATA                             0x018
 128 #define SPI_RX_DATA                             0x01C
 129
 130 #define SPI_DMA_CTL                             0x020
 131 #define SPI_TX_TRIG_1                           (0 << 15)
 132 #define SPI_TX_TRIG_4                           (1 << 15)
 133 #define SPI_TX_TRIG_8                           (2 << 15)
 134 #define SPI_TX_TRIG_16                          (3 << 15)
 135 #define SPI_TX_TRIG_MASK                        (3 << 15)
 136 #define SPI_RX_TRIG_1                           (0 << 19)
 137 #define SPI_RX_TRIG_4                           (1 << 19)
 138 #define SPI_RX_TRIG_8                           (2 << 19)
 139 #define SPI_RX_TRIG_16                          (3 << 19)
 140 #define SPI_RX_TRIG_MASK                        (3 << 19)
 141 #define SPI_IE_TX                               (1 << 28)
 142 #define SPI_IE_RX                               (1 << 29)
 143 #define SPI_CONT                                (1 << 30)
 144 #define SPI_DMA                                 (1 << 31)
 145 #define SPI_DMA_EN                              SPI_DMA
 146
 147 #define SPI_DMA_BLK                             0x024
 148 #define SPI_DMA_BLK_SET(x)                      (((x) & 0xFFFF) << 0)
 149
 150 #define SPI_TX_FIFO                             0x108
 151 #define SPI_RX_FIFO                             0x188
 152 #define SPI_INTR_MASK                           0x18c
 153 #define SPI_INTR_ALL_MASK                       (0x1fUL << 25)
 154 #define MAX_CHIP_SELECT                         4
 155 #define SPI_FIFO_DEPTH                          64
 156 #define DATA_DIR_TX                             (1 << 0)
 157 #define DATA_DIR_RX                             (1 << 1)
 158
 159 #define SPI_DMA_TIMEOUT                         (msecs_to_jiffies(1000))
 160 #define DEFAULT_SPI_DMA_BUF_LEN                 (16*1024)
 161 #define TX_FIFO_EMPTY_COUNT_MAX                 SPI_TX_FIFO_EMPTY_COUNT(0x40)
 162 #define RX_FIFO_FULL_COUNT_ZERO                 SPI_RX_FIFO_FULL_COUNT(0)
 163 #define MAX_HOLD_CYCLES                         16
 164 #define SPI_DEFAULT_SPEED                       25000000
 165
 166 struct tegra_spi_soc_data {
 167         bool has_intr_mask_reg;
 168 };
 169
 170 struct tegra_spi_data {
 171         struct device                           *dev;
 172         struct spi_master                       *master;
 173         spinlock_t                              lock;
 174
 175         struct clk                              *clk;
 176         struct reset_control                    *rst;
 177         void __iomem                            *base;
 178         phys_addr_t                             phys;
 179         unsigned                                irq;
 180         u32                                     cur_speed;
 181
 182         struct spi_device                       *cur_spi;
 183         struct spi_device                       *cs_control;
 184         unsigned                                cur_pos;
 185         unsigned                                words_per_32bit;
 186         unsigned                                bytes_per_word;
 187         unsigned                                curr_dma_words;
 188         unsigned                                cur_direction;
 189
 190         unsigned                                cur_rx_pos;
 191         unsigned                                cur_tx_pos;
 192
 193         unsigned                                dma_buf_size;
 194         unsigned                                max_buf_size;
 195         bool                                    is_curr_dma_xfer;
 196
 197         struct completion                       rx_dma_complete;
 198         struct completion                       tx_dma_complete;
 199
 200         u32                                     tx_status;
 201         u32                                     rx_status;
 202         u32                                     status_reg;
 203         bool                                    is_packed;
 204
 205         u32                                     command1_reg;
 206         u32                                     dma_control_reg;
 207         u32                                     def_command1_reg;
 208
 209         struct completion                       xfer_completion;
 210         struct spi_transfer                     *curr_xfer;
 211         struct dma_chan                         *rx_dma_chan;
 212         u32                                     *rx_dma_buf;
 213         dma_addr_t                              rx_dma_phys;
 214         struct dma_async_tx_descriptor          *rx_dma_desc;
 215
 216         struct dma_chan                         *tx_dma_chan;
 217         u32                                     *tx_dma_buf;
 218         dma_addr_t                              tx_dma_phys;
 219         struct dma_async_tx_descriptor          *tx_dma_desc;
 220         const struct tegra_spi_soc_data         *soc_data;
 221 };
 222
 223 static int tegra_spi_runtime_suspend(struct device *dev);
 224 static int tegra_spi_runtime_resume(struct device *dev);
 225
 226 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
 227                 unsigned long reg)
 228 {
 229         return readl(tspi->base + reg);
 230 }
 231
 232 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
 233                 u32 val, unsigned long reg)
 234 {
 235         writel(val, tspi->base + reg);
 236
 237         /* Read back register to make sure that register writes completed */
 238         if (reg != SPI_TX_FIFO)
 239                 readl(tspi->base + SPI_COMMAND1);
 240 }
 241
 242 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
 243 {
 244         u32 val;
 245
 246         /* Write 1 to clear status register */
 247         val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
 248         tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
 249
 250         /* Clear fifo status error if any */
 251         val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 252         if (val & SPI_ERR)
 253                 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
 254                                 SPI_FIFO_STATUS);
 255 }
 256
 257 static unsigned tegra_spi_calculate_curr_xfer_param(
 258         struct spi_device *spi, struct tegra_spi_data *tspi,
 259         struct spi_transfer *t)
 260 {
 261         unsigned remain_len = t->len - tspi->cur_pos;
 262         unsigned max_word;
 263         unsigned bits_per_word = t->bits_per_word;
 264         unsigned max_len;
 265         unsigned total_fifo_words;
 266
 267         tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
 268
 269         if ((bits_per_word == 8 || bits_per_word == 16 ||
 270              bits_per_word == 32) && t->len > 3) {
 271                 tspi->is_packed = 1;
 272                 tspi->words_per_32bit = 32/bits_per_word;
 273         } else {
 274                 tspi->is_packed = 0;
 275                 tspi->words_per_32bit = 1;
 276         }
 277
 278         if (tspi->is_packed) {
 279                 max_len = min(remain_len, tspi->max_buf_size);
 280                 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
 281                 total_fifo_words = (max_len + 3) / 4;
 282         } else {
 283                 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
 284                 max_word = min(max_word, tspi->max_buf_size/4);
 285                 tspi->curr_dma_words = max_word;
 286                 total_fifo_words = max_word;
 287         }
 288         return total_fifo_words;
 289 }
 290
 291 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
 292         struct tegra_spi_data *tspi, struct spi_transfer *t)
 293 {
 294         unsigned nbytes;
 295         unsigned tx_empty_count;
 296         u32 fifo_status;
 297         unsigned max_n_32bit;
 298         unsigned i, count;
 299         unsigned int written_words;
 300         unsigned fifo_words_left;
 301         u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 302
 303         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 304         tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
 305
 306         if (tspi->is_packed) {
 307                 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
 308                 written_words = min(fifo_words_left, tspi->curr_dma_words);
 309                 nbytes = written_words * tspi->bytes_per_word;
 310                 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
 311                 for (count = 0; count < max_n_32bit; count++) {
 312                         u32 x = 0;
 313
 314                         for (i = 0; (i < 4) && nbytes; i++, nbytes--)
 315                                 x |= (u32)(*tx_buf++) << (i * 8);
 316                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 317                 }
 318
 319                 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
 320         } else {
 321                 unsigned int write_bytes;
 322                 max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
 323                 written_words = max_n_32bit;
 324                 nbytes = written_words * tspi->bytes_per_word;
 325                 if (nbytes > t->len - tspi->cur_pos)
 326                         nbytes = t->len - tspi->cur_pos;
 327                 write_bytes = nbytes;
 328                 for (count = 0; count < max_n_32bit; count++) {
 329                         u32 x = 0;
 330
 331                         for (i = 0; nbytes && (i < tspi->bytes_per_word);
 332                                                         i++, nbytes--)
 333                                 x |= (u32)(*tx_buf++) << (i * 8);
 334                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 335                 }
 336
 337                 tspi->cur_tx_pos += write_bytes;
 338         }
 339
 340         return written_words;
 341 }
 342
 343 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
 344                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 345 {
 346         unsigned rx_full_count;
 347         u32 fifo_status;
 348         unsigned i, count;
 349         unsigned int read_words = 0;
 350         unsigned len;
 351         u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
 352
 353         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 354         rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
 355         if (tspi->is_packed) {
 356                 len = tspi->curr_dma_words * tspi->bytes_per_word;
 357                 for (count = 0; count < rx_full_count; count++) {
 358                         u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
 359
 360                         for (i = 0; len && (i < 4); i++, len--)
 361                                 *rx_buf++ = (x >> i*8) & 0xFF;
 362                 }
 363                 read_words += tspi->curr_dma_words;
 364                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 365         } else {
 366                 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
 367                 u8 bytes_per_word = tspi->bytes_per_word;
 368                 unsigned int read_bytes;
 369
 370                 len = rx_full_count * bytes_per_word;
 371                 if (len > t->len - tspi->cur_pos)
 372                         len = t->len - tspi->cur_pos;
 373                 read_bytes = len;
 374                 for (count = 0; count < rx_full_count; count++) {
 375                         u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
 376
 377                         for (i = 0; len && (i < bytes_per_word); i++, len--)
 378                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
 379                 }
 380                 read_words += rx_full_count;
 381                 tspi->cur_rx_pos += read_bytes;
 382         }
 383
 384         return read_words;
 385 }
 386
 387 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
 388                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 389 {
 390         /* Make the dma buffer to read by cpu */
 391         dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
 392                                 tspi->dma_buf_size, DMA_TO_DEVICE);
 393
 394         if (tspi->is_packed) {
 395                 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
 396
 397                 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
 398                 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 399         } else {
 400                 unsigned int i;
 401                 unsigned int count;
 402                 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 403                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
 404                 unsigned int write_bytes;
 405
 406                 if (consume > t->len - tspi->cur_pos)
 407                         consume = t->len - tspi->cur_pos;
 408                 write_bytes = consume;
 409                 for (count = 0; count < tspi->curr_dma_words; count++) {
 410                         u32 x = 0;
 411
 412                         for (i = 0; consume && (i < tspi->bytes_per_word);
 413                                                         i++, consume--)
 414                                 x |= (u32)(*tx_buf++) << (i * 8);
 415                         tspi->tx_dma_buf[count] = x;
 416                 }
 417
 418                 tspi->cur_tx_pos += write_bytes;
 419         }
 420
 421         /* Make the dma buffer to read by dma */
 422         dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
 423                                 tspi->dma_buf_size, DMA_TO_DEVICE);
 424 }
 425
 426 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
 427                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 428 {
 429         /* Make the dma buffer to read by cpu */
 430         dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
 431                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 432
 433         if (tspi->is_packed) {
 434                 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
 435
 436                 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
 437                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 438         } else {
 439                 unsigned int i;
 440                 unsigned int count;
 441                 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
 442                 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
 443                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
 444                 unsigned int read_bytes;
 445
 446                 if (consume > t->len - tspi->cur_pos)
 447                         consume = t->len - tspi->cur_pos;
 448                 read_bytes = consume;
 449                 for (count = 0; count < tspi->curr_dma_words; count++) {
 450                         u32 x = tspi->rx_dma_buf[count] & rx_mask;
 451
 452                         for (i = 0; consume && (i < tspi->bytes_per_word);
 453                                                         i++, consume--)
 454                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
 455                 }
 456
 457                 tspi->cur_rx_pos += read_bytes;
 458         }
 459
 460         /* Make the dma buffer to read by dma */
 461         dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 462                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 463 }
 464
 465 static void tegra_spi_dma_complete(void *args)
 466 {
 467         struct completion *dma_complete = args;
 468
 469         complete(dma_complete);
 470 }
 471
 472 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
 473 {
 474         reinit_completion(&tspi->tx_dma_complete);
 475         tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
 476                                 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
 477                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 478         if (!tspi->tx_dma_desc) {
 479                 dev_err(tspi->dev, "Not able to get desc for Tx\n");
 480                 return -EIO;
 481         }
 482
 483         tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
 484         tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
 485
 486         dmaengine_submit(tspi->tx_dma_desc);
 487         dma_async_issue_pending(tspi->tx_dma_chan);
 488         return 0;
 489 }
 490
 491 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
 492 {
 493         reinit_completion(&tspi->rx_dma_complete);
 494         tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
 495                                 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
 496                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 497         if (!tspi->rx_dma_desc) {
 498                 dev_err(tspi->dev, "Not able to get desc for Rx\n");
 499                 return -EIO;
 500         }
 501
 502         tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
 503         tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
 504
 505         dmaengine_submit(tspi->rx_dma_desc);
 506         dma_async_issue_pending(tspi->rx_dma_chan);
 507         return 0;
 508 }
 509
 510 static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi)
 511 {
 512         unsigned long timeout = jiffies + HZ;
 513         u32 status;
 514
 515         status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 516         if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
 517                 status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
 518                 tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
 519                 while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
 520                         status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 521                         if (time_after(jiffies, timeout)) {
 522                                 dev_err(tspi->dev,
 523                                         "timeout waiting for fifo flush\n");
 524                                 return -EIO;
 525                         }
 526
 527                         udelay(1);
 528                 }
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int tegra_spi_start_dma_based_transfer(
 535                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 536 {
 537         u32 val;
 538         unsigned int len;
 539         int ret = 0;
 540         u8 dma_burst;
 541         struct dma_slave_config dma_sconfig = {0};
 542
 543         val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
 544         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 545
 546         if (tspi->is_packed)
 547                 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
 548                                         4) * 4;
 549         else
 550                 len = tspi->curr_dma_words * 4;
 551
 552         /* Set attention level based on length of transfer */
 553         if (len & 0xF) {
 554                 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
 555                 dma_burst = 1;
 556         } else if (((len) >> 4) & 0x1) {
 557                 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
 558                 dma_burst = 4;
 559         } else {
 560                 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
 561                 dma_burst = 8;
 562         }
 563
 564         if (!tspi->soc_data->has_intr_mask_reg) {
 565                 if (tspi->cur_direction & DATA_DIR_TX)
 566                         val |= SPI_IE_TX;
 567
 568                 if (tspi->cur_direction & DATA_DIR_RX)
 569                         val |= SPI_IE_RX;
 570         }
 571
 572         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 573         tspi->dma_control_reg = val;
 574
 575         dma_sconfig.device_fc = true;
 576         if (tspi->cur_direction & DATA_DIR_TX) {
 577                 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
 578                 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 579                 dma_sconfig.dst_maxburst = dma_burst;
 580                 ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig);
 581                 if (ret < 0) {
 582                         dev_err(tspi->dev,
 583                                 "DMA slave config failed: %d\n", ret);
 584                         return ret;
 585                 }
 586
 587                 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
 588                 ret = tegra_spi_start_tx_dma(tspi, len);
 589                 if (ret < 0) {
 590                         dev_err(tspi->dev,
 591                                 "Starting tx dma failed, err %d\n", ret);
 592                         return ret;
 593                 }
 594         }
 595
 596         if (tspi->cur_direction & DATA_DIR_RX) {
 597                 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
 598                 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 599                 dma_sconfig.src_maxburst = dma_burst;
 600                 ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig);
 601                 if (ret < 0) {
 602                         dev_err(tspi->dev,
 603                                 "DMA slave config failed: %d\n", ret);
 604                         return ret;
 605                 }
 606
 607                 /* Make the dma buffer to read by dma */
 608                 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 609                                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 610
 611                 ret = tegra_spi_start_rx_dma(tspi, len);
 612                 if (ret < 0) {
 613                         dev_err(tspi->dev,
 614                                 "Starting rx dma failed, err %d\n", ret);
 615                         if (tspi->cur_direction & DATA_DIR_TX)
 616                                 dmaengine_terminate_all(tspi->tx_dma_chan);
 617                         return ret;
 618                 }
 619         }
 620         tspi->is_curr_dma_xfer = true;
 621         tspi->dma_control_reg = val;
 622
 623         val |= SPI_DMA_EN;
 624         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 625         return ret;
 626 }
 627
 628 static int tegra_spi_start_cpu_based_transfer(
 629                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 630 {
 631         u32 val;
 632         unsigned cur_words;
 633
 634         if (tspi->cur_direction & DATA_DIR_TX)
 635                 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
 636         else
 637                 cur_words = tspi->curr_dma_words;
 638
 639         val = SPI_DMA_BLK_SET(cur_words - 1);
 640         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 641
 642         val = 0;
 643         if (tspi->cur_direction & DATA_DIR_TX)
 644                 val |= SPI_IE_TX;
 645
 646         if (tspi->cur_direction & DATA_DIR_RX)
 647                 val |= SPI_IE_RX;
 648
 649         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 650         tspi->dma_control_reg = val;
 651
 652         tspi->is_curr_dma_xfer = false;
 653
 654         val = tspi->command1_reg;
 655         val |= SPI_PIO;
 656         tegra_spi_writel(tspi, val, SPI_COMMAND1);
 657         return 0;
 658 }
 659
 660 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
 661                         bool dma_to_memory)
 662 {
 663         struct dma_chan *dma_chan;
 664         u32 *dma_buf;
 665         dma_addr_t dma_phys;
 666         int ret;
 667
 668         dma_chan = dma_request_slave_channel_reason(tspi->dev,
 669                                         dma_to_memory ? "rx" : "tx");
 670         if (IS_ERR(dma_chan)) {
 671                 ret = PTR_ERR(dma_chan);
 672                 if (ret != -EPROBE_DEFER)
 673                         dev_err(tspi->dev,
 674                                 "Dma channel is not available: %d\n", ret);
 675                 return ret;
 676         }
 677
 678         dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
 679                                 &dma_phys, GFP_KERNEL);
 680         if (!dma_buf) {
 681                 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
 682                 dma_release_channel(dma_chan);
 683                 return -ENOMEM;
 684         }
 685
 686         if (dma_to_memory) {
 687                 tspi->rx_dma_chan = dma_chan;
 688                 tspi->rx_dma_buf = dma_buf;
 689                 tspi->rx_dma_phys = dma_phys;
 690         } else {
 691                 tspi->tx_dma_chan = dma_chan;
 692                 tspi->tx_dma_buf = dma_buf;
 693                 tspi->tx_dma_phys = dma_phys;
 694         }
 695         return 0;
 696 }
 697
 698 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 699         bool dma_to_memory)
 700 {
 701         u32 *dma_buf;
 702         dma_addr_t dma_phys;
 703         struct dma_chan *dma_chan;
 704
 705         if (dma_to_memory) {
 706                 dma_buf = tspi->rx_dma_buf;
 707                 dma_chan = tspi->rx_dma_chan;
 708                 dma_phys = tspi->rx_dma_phys;
 709                 tspi->rx_dma_chan = NULL;
 710                 tspi->rx_dma_buf = NULL;
 711         } else {
 712                 dma_buf = tspi->tx_dma_buf;
 713                 dma_chan = tspi->tx_dma_chan;
 714                 dma_phys = tspi->tx_dma_phys;
 715                 tspi->tx_dma_buf = NULL;
 716                 tspi->tx_dma_chan = NULL;
 717         }
 718         if (!dma_chan)
 719                 return;
 720
 721         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 722         dma_release_channel(dma_chan);
 723 }
 724
 725 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 726                 struct spi_transfer *t, bool is_first_of_msg)
 727 {
 728         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 729         u32 speed = t->speed_hz;
 730         u8 bits_per_word = t->bits_per_word;
 731         u32 command1;
 732         int req_mode;
 733
 734         if (speed != tspi->cur_speed) {
 735                 clk_set_rate(tspi->clk, speed);
 736                 tspi->cur_speed = speed;
 737         }
 738
 739         tspi->cur_spi = spi;
 740         tspi->cur_pos = 0;
 741         tspi->cur_rx_pos = 0;
 742         tspi->cur_tx_pos = 0;
 743         tspi->curr_xfer = t;
 744
 745         if (is_first_of_msg) {
 746                 tegra_spi_clear_status(tspi);
 747
 748                 command1 = tspi->def_command1_reg;
 749                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 750
 751                 command1 &= ~SPI_CONTROL_MODE_MASK;
 752                 req_mode = spi->mode & 0x3;
 753                 if (req_mode == SPI_MODE_0)
 754                         command1 |= SPI_CONTROL_MODE_0;
 755                 else if (req_mode == SPI_MODE_1)
 756                         command1 |= SPI_CONTROL_MODE_1;
 757                 else if (req_mode == SPI_MODE_2)
 758                         command1 |= SPI_CONTROL_MODE_2;
 759                 else if (req_mode == SPI_MODE_3)
 760                         command1 |= SPI_CONTROL_MODE_3;
 761
 762                 if (spi->mode & SPI_LSB_FIRST)
 763                         command1 |= SPI_LSBIT_FE;
 764                 else
 765                         command1 &= ~SPI_LSBIT_FE;
 766
 767                 if (spi->mode & SPI_3WIRE)
 768                         command1 |= SPI_BIDIROE;
 769                 else
 770                         command1 &= ~SPI_BIDIROE;
 771
 772                 if (tspi->cs_control) {
 773                         if (tspi->cs_control != spi)
 774                                 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 775                         tspi->cs_control = NULL;
 776                 } else
 777                         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 778
 779                 command1 |= SPI_CS_SW_HW;
 780                 if (spi->mode & SPI_CS_HIGH)
 781                         command1 |= SPI_CS_SW_VAL;
 782                 else
 783                         command1 &= ~SPI_CS_SW_VAL;
 784
 785                 tegra_spi_writel(tspi, 0, SPI_COMMAND2);
 786         } else {
 787                 command1 = tspi->command1_reg;
 788                 command1 &= ~SPI_BIT_LENGTH(~0);
 789                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 790         }
 791
 792         return command1;
 793 }
 794
 795 static int tegra_spi_start_transfer_one(struct spi_device *spi,
 796                 struct spi_transfer *t, u32 command1)
 797 {
 798         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 799         unsigned total_fifo_words;
 800         int ret;
 801
 802         total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
 803
 804         if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL)
 805                 command1 |= SPI_BOTH_EN_BIT;
 806         else
 807                 command1 &= ~SPI_BOTH_EN_BIT;
 808
 809         if (tspi->is_packed)
 810                 command1 |= SPI_PACKED;
 811         else
 812                 command1 &= ~SPI_PACKED;
 813
 814         command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
 815         tspi->cur_direction = 0;
 816         if (t->rx_buf) {
 817                 command1 |= SPI_RX_EN;
 818                 tspi->cur_direction |= DATA_DIR_RX;
 819         }
 820         if (t->tx_buf) {
 821                 command1 |= SPI_TX_EN;
 822                 tspi->cur_direction |= DATA_DIR_TX;
 823         }
 824         command1 |= SPI_CS_SEL(spi->chip_select);
 825         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 826         tspi->command1_reg = command1;
 827
 828         dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
 829                 tspi->def_command1_reg, (unsigned)command1);
 830
 831         ret = tegra_spi_flush_fifos(tspi);
 832         if (ret < 0)
 833                 return ret;
 834         if (total_fifo_words > SPI_FIFO_DEPTH)
 835                 ret = tegra_spi_start_dma_based_transfer(tspi, t);
 836         else
 837                 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
 838         return ret;
 839 }
 840
 841 static int tegra_spi_setup(struct spi_device *spi)
 842 {
 843         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 844         u32 val;
 845         unsigned long flags;
 846         int ret;
 847
 848         dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
 849                 spi->bits_per_word,
 850                 spi->mode & SPI_CPOL ? "" : "~",
 851                 spi->mode & SPI_CPHA ? "" : "~",
 852                 spi->max_speed_hz);
 853
 854         ret = pm_runtime_get_sync(tspi->dev);
 855         if (ret < 0) {
 856                 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
 857                 return ret;
 858         }
 859
 860         if (tspi->soc_data->has_intr_mask_reg) {
 861                 val = tegra_spi_readl(tspi, SPI_INTR_MASK);
 862                 val &= ~SPI_INTR_ALL_MASK;
 863                 tegra_spi_writel(tspi, val, SPI_INTR_MASK);
 864         }
 865
 866         spin_lock_irqsave(&tspi->lock, flags);
 867         val = tspi->def_command1_reg;
 868         if (spi->mode & SPI_CS_HIGH)
 869                 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
 870         else
 871                 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
 872         tspi->def_command1_reg = val;
 873         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 874         spin_unlock_irqrestore(&tspi->lock, flags);
 875
 876         pm_runtime_put(tspi->dev);
 877         return 0;
 878 }
 879
 880 static void tegra_spi_transfer_delay(int delay)
 881 {
 882         if (!delay)
 883                 return;
 884
 885         if (delay >= 1000)
 886                 mdelay(delay / 1000);
 887
 888         udelay(delay % 1000);
 889 }
 890
 891 static void tegra_spi_transfer_end(struct spi_device *spi)
 892 {
 893         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 894         int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
 895
 896         if (cs_val)
 897                 tspi->command1_reg |= SPI_CS_SW_VAL;
 898         else
 899                 tspi->command1_reg &= ~SPI_CS_SW_VAL;
 900         tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
 901         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 902 }
 903
 904 static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
 905 {
 906         dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
 907         dev_dbg(tspi->dev, "Command1:    0x%08x | Command2:    0x%08x\n",
 908                 tegra_spi_readl(tspi, SPI_COMMAND1),
 909                 tegra_spi_readl(tspi, SPI_COMMAND2));
 910         dev_dbg(tspi->dev, "DMA_CTL:     0x%08x | DMA_BLK:     0x%08x\n",
 911                 tegra_spi_readl(tspi, SPI_DMA_CTL),
 912                 tegra_spi_readl(tspi, SPI_DMA_BLK));
 913         dev_dbg(tspi->dev, "TRANS_STAT:  0x%08x | FIFO_STATUS: 0x%08x\n",
 914                 tegra_spi_readl(tspi, SPI_TRANS_STATUS),
 915                 tegra_spi_readl(tspi, SPI_FIFO_STATUS));
 916 }
 917
 918 static int tegra_spi_transfer_one_message(struct spi_master *master,
 919                         struct spi_message *msg)
 920 {
 921         bool is_first_msg = true;
 922         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
 923         struct spi_transfer *xfer;
 924         struct spi_device *spi = msg->spi;
 925         int ret;
 926         bool skip = false;
 927
 928         msg->status = 0;
 929         msg->actual_length = 0;
 930
 931         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 932                 u32 cmd1;
 933
 934                 reinit_completion(&tspi->xfer_completion);
 935
 936                 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
 937
 938                 if (!xfer->len) {
 939                         ret = 0;
 940                         skip = true;
 941                         goto complete_xfer;
 942                 }
 943
 944                 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
 945                 if (ret < 0) {
 946                         dev_err(tspi->dev,
 947                                 "spi can not start transfer, err %d\n", ret);
 948                         goto complete_xfer;
 949                 }
 950
 951                 is_first_msg = false;
 952                 ret = wait_for_completion_timeout(&tspi->xfer_completion,
 953                                                 SPI_DMA_TIMEOUT);
 954                 if (WARN_ON(ret == 0)) {
 955                         dev_err(tspi->dev,
 956                                 "spi transfer timeout, err %d\n", ret);
 957                         if (tspi->is_curr_dma_xfer &&
 958                             (tspi->cur_direction & DATA_DIR_TX))
 959                                 dmaengine_terminate_all(tspi->tx_dma_chan);
 960                         if (tspi->is_curr_dma_xfer &&
 961                             (tspi->cur_direction & DATA_DIR_RX))
 962                                 dmaengine_terminate_all(tspi->rx_dma_chan);
 963                         ret = -EIO;
 964                         tegra_spi_dump_regs(tspi);
 965                         tegra_spi_flush_fifos(tspi);
 966                         reset_control_assert(tspi->rst);
 967                         udelay(2);
 968                         reset_control_deassert(tspi->rst);
 969                         goto complete_xfer;
 970                 }
 971
 972                 if (tspi->tx_status ||  tspi->rx_status) {
 973                         dev_err(tspi->dev, "Error in Transfer\n");
 974                         ret = -EIO;
 975                         tegra_spi_dump_regs(tspi);
 976                         goto complete_xfer;
 977                 }
 978                 msg->actual_length += xfer->len;
 979
 980 complete_xfer:
 981                 if (ret < 0 || skip) {
 982                         tegra_spi_transfer_end(spi);
 983                         tegra_spi_transfer_delay(xfer->delay_usecs);
 984                         goto exit;
 985                 } else if (list_is_last(&xfer->transfer_list,
 986                                         &msg->transfers)) {
 987                         if (xfer->cs_change)
 988                                 tspi->cs_control = spi;
 989                         else {
 990                                 tegra_spi_transfer_end(spi);
 991                                 tegra_spi_transfer_delay(xfer->delay_usecs);
 992                         }
 993                 } else if (xfer->cs_change) {
 994                         tegra_spi_transfer_end(spi);
 995                         tegra_spi_transfer_delay(xfer->delay_usecs);
 996                 }
 997
 998         }
 999         ret = 0;
1000 exit:
1001         msg->status = ret;
1002         spi_finalize_current_message(master);
1003         return ret;
1004 }
1005
1006 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
1007 {
1008         struct spi_transfer *t = tspi->curr_xfer;
1009         unsigned long flags;
1010
1011         spin_lock_irqsave(&tspi->lock, flags);
1012         if (tspi->tx_status ||  tspi->rx_status) {
1013                 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
1014                         tspi->status_reg);
1015                 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
1016                         tspi->command1_reg, tspi->dma_control_reg);
1017                 tegra_spi_dump_regs(tspi);
1018                 tegra_spi_flush_fifos(tspi);
1019                 complete(&tspi->xfer_completion);
1020                 spin_unlock_irqrestore(&tspi->lock, flags);
1021                 reset_control_assert(tspi->rst);
1022                 udelay(2);
1023                 reset_control_deassert(tspi->rst);
1024                 return IRQ_HANDLED;
1025         }
1026
1027         if (tspi->cur_direction & DATA_DIR_RX)
1028                 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
1029
1030         if (tspi->cur_direction & DATA_DIR_TX)
1031                 tspi->cur_pos = tspi->cur_tx_pos;
1032         else
1033                 tspi->cur_pos = tspi->cur_rx_pos;
1034
1035         if (tspi->cur_pos == t->len) {
1036                 complete(&tspi->xfer_completion);
1037                 goto exit;
1038         }
1039
1040         tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
1041         tegra_spi_start_cpu_based_transfer(tspi, t);
1042 exit:
1043         spin_unlock_irqrestore(&tspi->lock, flags);
1044         return IRQ_HANDLED;
1045 }
1046
1047 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
1048 {
1049         struct spi_transfer *t = tspi->curr_xfer;
1050         long wait_status;
1051         int err = 0;
1052         unsigned total_fifo_words;
1053         unsigned long flags;
1054
1055         /* Abort dmas if any error */
1056         if (tspi->cur_direction & DATA_DIR_TX) {
1057                 if (tspi->tx_status) {
1058                         dmaengine_terminate_all(tspi->tx_dma_chan);
1059                         err += 1;
1060                 } else {
1061                         wait_status = wait_for_completion_interruptible_timeout(
1062                                 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
1063                         if (wait_status <= 0) {
1064                                 dmaengine_terminate_all(tspi->tx_dma_chan);
1065                                 dev_err(tspi->dev, "TxDma Xfer failed\n");
1066                                 err += 1;
1067                         }
1068                 }
1069         }
1070
1071         if (tspi->cur_direction & DATA_DIR_RX) {
1072                 if (tspi->rx_status) {
1073                         dmaengine_terminate_all(tspi->rx_dma_chan);
1074                         err += 2;
1075                 } else {
1076                         wait_status = wait_for_completion_interruptible_timeout(
1077                                 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
1078                         if (wait_status <= 0) {
1079                                 dmaengine_terminate_all(tspi->rx_dma_chan);
1080                                 dev_err(tspi->dev, "RxDma Xfer failed\n");
1081                                 err += 2;
1082                         }
1083                 }
1084         }
1085
1086         spin_lock_irqsave(&tspi->lock, flags);
1087         if (err) {
1088                 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
1089                         tspi->status_reg);
1090                 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
1091                         tspi->command1_reg, tspi->dma_control_reg);
1092                 tegra_spi_dump_regs(tspi);
1093                 tegra_spi_flush_fifos(tspi);
1094                 complete(&tspi->xfer_completion);
1095                 spin_unlock_irqrestore(&tspi->lock, flags);
1096                 reset_control_assert(tspi->rst);
1097                 udelay(2);
1098                 reset_control_deassert(tspi->rst);
1099                 return IRQ_HANDLED;
1100         }
1101
1102         if (tspi->cur_direction & DATA_DIR_RX)
1103                 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1104
1105         if (tspi->cur_direction & DATA_DIR_TX)
1106                 tspi->cur_pos = tspi->cur_tx_pos;
1107         else
1108                 tspi->cur_pos = tspi->cur_rx_pos;
1109
1110         if (tspi->cur_pos == t->len) {
1111                 complete(&tspi->xfer_completion);
1112                 goto exit;
1113         }
1114
1115         /* Continue transfer in current message */
1116         total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
1117                                                         tspi, t);
1118         if (total_fifo_words > SPI_FIFO_DEPTH)
1119                 err = tegra_spi_start_dma_based_transfer(tspi, t);
1120         else
1121                 err = tegra_spi_start_cpu_based_transfer(tspi, t);
1122
1123 exit:
1124         spin_unlock_irqrestore(&tspi->lock, flags);
1125         return IRQ_HANDLED;
1126 }
1127
1128 static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
1129 {
1130         struct tegra_spi_data *tspi = context_data;
1131
1132         if (!tspi->is_curr_dma_xfer)
1133                 return handle_cpu_based_xfer(tspi);
1134         return handle_dma_based_xfer(tspi);
1135 }
1136
1137 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1138 {
1139         struct tegra_spi_data *tspi = context_data;
1140
1141         tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1142         if (tspi->cur_direction & DATA_DIR_TX)
1143                 tspi->tx_status = tspi->status_reg &
1144                                         (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1145
1146         if (tspi->cur_direction & DATA_DIR_RX)
1147                 tspi->rx_status = tspi->status_reg &
1148                                         (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1149         tegra_spi_clear_status(tspi);
1150
1151         return IRQ_WAKE_THREAD;
1152 }
1153
1154 static struct tegra_spi_soc_data tegra114_spi_soc_data = {
1155         .has_intr_mask_reg = false,
1156 };
1157
1158 static struct tegra_spi_soc_data tegra124_spi_soc_data = {
1159         .has_intr_mask_reg = false,
1160 };
1161
1162 static struct tegra_spi_soc_data tegra210_spi_soc_data = {
1163         .has_intr_mask_reg = true,
1164 };
1165
1166 static const struct of_device_id tegra_spi_of_match[] = {
1167         {
1168                 .compatible = "nvidia,tegra114-spi",
1169                 .data       = &tegra114_spi_soc_data,
1170         }, {
1171                 .compatible = "nvidia,tegra124-spi",
1172                 .data       = &tegra124_spi_soc_data,
1173         }, {
1174                 .compatible = "nvidia,tegra210-spi",
1175                 .data       = &tegra210_spi_soc_data,
1176         },
1177         {}
1178 };
1179 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1180
1181 static int tegra_spi_probe(struct platform_device *pdev)
1182 {
1183         struct spi_master       *master;
1184         struct tegra_spi_data   *tspi;
1185         struct resource         *r;
1186         int ret, spi_irq;
1187         int bus_num;
1188
1189         master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1190         if (!master) {
1191                 dev_err(&pdev->dev, "master allocation failed\n");
1192                 return -ENOMEM;
1193         }
1194         platform_set_drvdata(pdev, master);
1195         tspi = spi_master_get_devdata(master);
1196
1197         if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1198                                  &master->max_speed_hz))
1199                 master->max_speed_hz = 25000000; /* 25MHz */
1200
1201         /* the spi->mode bits understood by this driver: */
1202         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
1203                             SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
1204         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1205         master->setup = tegra_spi_setup;
1206         master->transfer_one_message = tegra_spi_transfer_one_message;
1207         master->num_chipselect = MAX_CHIP_SELECT;
1208         master->auto_runtime_pm = true;
1209         bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
1210         if (bus_num >= 0)
1211                 master->bus_num = bus_num;
1212
1213         tspi->master = master;
1214         tspi->dev = &pdev->dev;
1215         spin_lock_init(&tspi->lock);
1216
1217         tspi->soc_data = of_device_get_match_data(&pdev->dev);
1218         if (!tspi->soc_data) {
1219                 dev_err(&pdev->dev, "unsupported tegra\n");
1220                 ret = -ENODEV;
1221                 goto exit_free_master;
1222         }
1223
1224         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1225         tspi->base = devm_ioremap_resource(&pdev->dev, r);
1226         if (IS_ERR(tspi->base)) {
1227                 ret = PTR_ERR(tspi->base);
1228                 goto exit_free_master;
1229         }
1230         tspi->phys = r->start;
1231
1232         spi_irq = platform_get_irq(pdev, 0);
1233         tspi->irq = spi_irq;
1234
1235         tspi->clk = devm_clk_get(&pdev->dev, "spi");
1236         if (IS_ERR(tspi->clk)) {
1237                 dev_err(&pdev->dev, "can not get clock\n");
1238                 ret = PTR_ERR(tspi->clk);
1239                 goto exit_free_master;
1240         }
1241
1242         tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1243         if (IS_ERR(tspi->rst)) {
1244                 dev_err(&pdev->dev, "can not get reset\n");
1245                 ret = PTR_ERR(tspi->rst);
1246                 goto exit_free_master;
1247         }
1248
1249         tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1250         tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1251
1252         ret = tegra_spi_init_dma_param(tspi, true);
1253         if (ret < 0)
1254                 goto exit_free_master;
1255         ret = tegra_spi_init_dma_param(tspi, false);
1256         if (ret < 0)
1257                 goto exit_rx_dma_free;
1258         tspi->max_buf_size = tspi->dma_buf_size;
1259         init_completion(&tspi->tx_dma_complete);
1260         init_completion(&tspi->rx_dma_complete);
1261
1262         init_completion(&tspi->xfer_completion);
1263
1264         pm_runtime_enable(&pdev->dev);
1265         if (!pm_runtime_enabled(&pdev->dev)) {
1266                 ret = tegra_spi_runtime_resume(&pdev->dev);
1267                 if (ret)
1268                         goto exit_pm_disable;
1269         }
1270
1271         ret = pm_runtime_get_sync(&pdev->dev);
1272         if (ret < 0) {
1273                 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1274                 goto exit_pm_disable;
1275         }
1276
1277         reset_control_assert(tspi->rst);
1278         udelay(2);
1279         reset_control_deassert(tspi->rst);
1280         tspi->def_command1_reg  = SPI_M_S;
1281         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1282         pm_runtime_put(&pdev->dev);
1283         ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1284                                    tegra_spi_isr_thread, IRQF_ONESHOT,
1285                                    dev_name(&pdev->dev), tspi);
1286         if (ret < 0) {
1287                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1288                         tspi->irq);
1289                 goto exit_pm_disable;
1290         }
1291
1292         master->dev.of_node = pdev->dev.of_node;
1293         ret = devm_spi_register_master(&pdev->dev, master);
1294         if (ret < 0) {
1295                 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1296                 goto exit_free_irq;
1297         }
1298         return ret;
1299
1300 exit_free_irq:
1301         free_irq(spi_irq, tspi);
1302 exit_pm_disable:
1303         pm_runtime_disable(&pdev->dev);
1304         if (!pm_runtime_status_suspended(&pdev->dev))
1305                 tegra_spi_runtime_suspend(&pdev->dev);
1306         tegra_spi_deinit_dma_param(tspi, false);
1307 exit_rx_dma_free:
1308         tegra_spi_deinit_dma_param(tspi, true);
1309 exit_free_master:
1310         spi_master_put(master);
1311         return ret;
1312 }
1313
1314 static int tegra_spi_remove(struct platform_device *pdev)
1315 {
1316         struct spi_master *master = platform_get_drvdata(pdev);
1317         struct tegra_spi_data   *tspi = spi_master_get_devdata(master);
1318
1319         free_irq(tspi->irq, tspi);
1320
1321         if (tspi->tx_dma_chan)
1322                 tegra_spi_deinit_dma_param(tspi, false);
1323
1324         if (tspi->rx_dma_chan)
1325                 tegra_spi_deinit_dma_param(tspi, true);
1326
1327         pm_runtime_disable(&pdev->dev);
1328         if (!pm_runtime_status_suspended(&pdev->dev))
1329                 tegra_spi_runtime_suspend(&pdev->dev);
1330
1331         return 0;
1332 }
1333
1334 #ifdef CONFIG_PM_SLEEP
1335 static int tegra_spi_suspend(struct device *dev)
1336 {
1337         struct spi_master *master = dev_get_drvdata(dev);
1338
1339         return spi_master_suspend(master);
1340 }
1341
1342 static int tegra_spi_resume(struct device *dev)
1343 {
1344         struct spi_master *master = dev_get_drvdata(dev);
1345         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1346         int ret;
1347
1348         ret = pm_runtime_get_sync(dev);
1349         if (ret < 0) {
1350                 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1351                 return ret;
1352         }
1353         tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1354         pm_runtime_put(dev);
1355
1356         return spi_master_resume(master);
1357 }
1358 #endif
1359
1360 static int tegra_spi_runtime_suspend(struct device *dev)
1361 {
1362         struct spi_master *master = dev_get_drvdata(dev);
1363         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1364
1365         /* Flush all write which are in PPSB queue by reading back */
1366         tegra_spi_readl(tspi, SPI_COMMAND1);
1367
1368         clk_disable_unprepare(tspi->clk);
1369         return 0;
1370 }
1371
1372 static int tegra_spi_runtime_resume(struct device *dev)
1373 {
1374         struct spi_master *master = dev_get_drvdata(dev);
1375         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1376         int ret;
1377
1378         ret = clk_prepare_enable(tspi->clk);
1379         if (ret < 0) {
1380                 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1381                 return ret;
1382         }
1383         return 0;
1384 }
1385
1386 static const struct dev_pm_ops tegra_spi_pm_ops = {
1387         SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1388                 tegra_spi_runtime_resume, NULL)
1389         SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1390 };
1391 static struct platform_driver tegra_spi_driver = {
1392         .driver = {
1393                 .name           = "spi-tegra114",
1394                 .pm             = &tegra_spi_pm_ops,
1395                 .of_match_table = tegra_spi_of_match,
1396         },
1397         .probe =        tegra_spi_probe,
1398         .remove =       tegra_spi_remove,
1399 };
1400 module_platform_driver(tegra_spi_driver);
1401
1402 MODULE_ALIAS("platform:spi-tegra114");
1403 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1404 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1405 MODULE_LICENSE("GPL v2");