drivers/spi/spi-stm32-qspi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/errno.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/reset.h>
  22 #include <linux/sizes.h>
  23 #include <linux/spi/spi-mem.h>
  24
  25 #define QSPI_CR                 0x00
  26 #define CR_EN                   BIT(0)
  27 #define CR_ABORT                BIT(1)
  28 #define CR_DMAEN                BIT(2)
  29 #define CR_TCEN                 BIT(3)
  30 #define CR_SSHIFT               BIT(4)
  31 #define CR_DFM                  BIT(6)
  32 #define CR_FSEL                 BIT(7)
  33 #define CR_FTHRES_SHIFT         8
  34 #define CR_TEIE                 BIT(16)
  35 #define CR_TCIE                 BIT(17)
  36 #define CR_FTIE                 BIT(18)
  37 #define CR_SMIE                 BIT(19)
  38 #define CR_TOIE                 BIT(20)
  39 #define CR_APMS                 BIT(22)
  40 #define CR_PRESC_MASK           GENMASK(31, 24)
  41
  42 #define QSPI_DCR                0x04
  43 #define DCR_FSIZE_MASK          GENMASK(20, 16)
  44
  45 #define QSPI_SR                 0x08
  46 #define SR_TEF                  BIT(0)
  47 #define SR_TCF                  BIT(1)
  48 #define SR_FTF                  BIT(2)
  49 #define SR_SMF                  BIT(3)
  50 #define SR_TOF                  BIT(4)
  51 #define SR_BUSY                 BIT(5)
  52 #define SR_FLEVEL_MASK          GENMASK(13, 8)
  53
  54 #define QSPI_FCR                0x0c
  55 #define FCR_CTEF                BIT(0)
  56 #define FCR_CTCF                BIT(1)
  57 #define FCR_CSMF                BIT(3)
  58
  59 #define QSPI_DLR                0x10
  60
  61 #define QSPI_CCR                0x14
  62 #define CCR_INST_MASK           GENMASK(7, 0)
  63 #define CCR_IMODE_MASK          GENMASK(9, 8)
  64 #define CCR_ADMODE_MASK         GENMASK(11, 10)
  65 #define CCR_ADSIZE_MASK         GENMASK(13, 12)
  66 #define CCR_DCYC_MASK           GENMASK(22, 18)
  67 #define CCR_DMODE_MASK          GENMASK(25, 24)
  68 #define CCR_FMODE_MASK          GENMASK(27, 26)
  69 #define CCR_FMODE_INDW          (0U << 26)
  70 #define CCR_FMODE_INDR          (1U << 26)
  71 #define CCR_FMODE_APM           (2U << 26)
  72 #define CCR_FMODE_MM            (3U << 26)
  73 #define CCR_BUSWIDTH_0          0x0
  74 #define CCR_BUSWIDTH_1          0x1
  75 #define CCR_BUSWIDTH_2          0x2
  76 #define CCR_BUSWIDTH_4          0x3
  77
  78 #define QSPI_AR                 0x18
  79 #define QSPI_ABR                0x1c
  80 #define QSPI_DR                 0x20
  81 #define QSPI_PSMKR              0x24
  82 #define QSPI_PSMAR              0x28
  83 #define QSPI_PIR                0x2c
  84 #define QSPI_LPTR               0x30
  85
  86 #define STM32_QSPI_MAX_MMAP_SZ  SZ_256M
  87 #define STM32_QSPI_MAX_NORCHIP  2
  88
  89 #define STM32_FIFO_TIMEOUT_US 30000
  90 #define STM32_BUSY_TIMEOUT_US 100000
  91 #define STM32_ABT_TIMEOUT_US 100000
  92 #define STM32_COMP_TIMEOUT_MS 1000
  93 #define STM32_AUTOSUSPEND_DELAY -1
  94
  95 struct stm32_qspi_flash {
  96         u32 cs;
  97         u32 presc;
  98 };
  99
 100 struct stm32_qspi {
 101         struct device *dev;
 102         struct spi_controller *ctrl;
 103         phys_addr_t phys_base;
 104         void __iomem *io_base;
 105         void __iomem *mm_base;
 106         resource_size_t mm_size;
 107         struct clk *clk;
 108         u32 clk_rate;
 109         struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
 110         struct completion data_completion;
 111         struct completion match_completion;
 112         u32 fmode;
 113
 114         struct dma_chan *dma_chtx;
 115         struct dma_chan *dma_chrx;
 116         struct completion dma_completion;
 117
 118         u32 cr_reg;
 119         u32 dcr_reg;
 120         unsigned long status_timeout;
 121
 122         /*
 123          * to protect device configuration, could be different between
 124          * 2 flash access (bk1, bk2)
 125          */
 126         struct mutex lock;
 127 };
 128
 129 static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
 130 {
 131         struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
 132         u32 cr, sr;
 133
 134         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 135         sr = readl_relaxed(qspi->io_base + QSPI_SR);
 136
 137         if (cr & CR_SMIE && sr & SR_SMF) {
 138                 /* disable irq */
 139                 cr &= ~CR_SMIE;
 140                 writel_relaxed(cr, qspi->io_base + QSPI_CR);
 141                 complete(&qspi->match_completion);
 142
 143                 return IRQ_HANDLED;
 144         }
 145
 146         if (sr & (SR_TEF | SR_TCF)) {
 147                 /* disable irq */
 148                 cr &= ~CR_TCIE & ~CR_TEIE;
 149                 writel_relaxed(cr, qspi->io_base + QSPI_CR);
 150                 complete(&qspi->data_completion);
 151         }
 152
 153         return IRQ_HANDLED;
 154 }
 155
 156 static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
 157 {
 158         *val = readb_relaxed(addr);
 159 }
 160
 161 static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
 162 {
 163         writeb_relaxed(*val, addr);
 164 }
 165
 166 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
 167                               const struct spi_mem_op *op)
 168 {
 169         void (*tx_fifo)(u8 *val, void __iomem *addr);
 170         u32 len = op->data.nbytes, sr;
 171         u8 *buf;
 172         int ret;
 173
 174         if (op->data.dir == SPI_MEM_DATA_IN) {
 175                 tx_fifo = stm32_qspi_read_fifo;
 176                 buf = op->data.buf.in;
 177
 178         } else {
 179                 tx_fifo = stm32_qspi_write_fifo;
 180                 buf = (u8 *)op->data.buf.out;
 181         }
 182
 183         while (len--) {
 184                 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
 185                                                         sr, (sr & SR_FTF), 1,
 186                                                         STM32_FIFO_TIMEOUT_US);
 187                 if (ret) {
 188                         dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
 189                                 len, sr);
 190                         return ret;
 191                 }
 192                 tx_fifo(buf++, qspi->io_base + QSPI_DR);
 193         }
 194
 195         return 0;
 196 }
 197
 198 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
 199                             const struct spi_mem_op *op)
 200 {
 201         memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
 202                       op->data.nbytes);
 203         return 0;
 204 }
 205
 206 static void stm32_qspi_dma_callback(void *arg)
 207 {
 208         struct completion *dma_completion = arg;
 209
 210         complete(dma_completion);
 211 }
 212
 213 static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
 214                              const struct spi_mem_op *op)
 215 {
 216         struct dma_async_tx_descriptor *desc;
 217         enum dma_transfer_direction dma_dir;
 218         struct dma_chan *dma_ch;
 219         struct sg_table sgt;
 220         dma_cookie_t cookie;
 221         u32 cr, t_out;
 222         int err;
 223
 224         if (op->data.dir == SPI_MEM_DATA_IN) {
 225                 dma_dir = DMA_DEV_TO_MEM;
 226                 dma_ch = qspi->dma_chrx;
 227         } else {
 228                 dma_dir = DMA_MEM_TO_DEV;
 229                 dma_ch = qspi->dma_chtx;
 230         }
 231
 232         /*
 233          * spi_map_buf return -EINVAL if the buffer is not DMA-able
 234          * (DMA-able: in vmalloc | kmap | virt_addr_valid)
 235          */
 236         err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
 237         if (err)
 238                 return err;
 239
 240         desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
 241                                        dma_dir, DMA_PREP_INTERRUPT);
 242         if (!desc) {
 243                 err = -ENOMEM;
 244                 goto out_unmap;
 245         }
 246
 247         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 248
 249         reinit_completion(&qspi->dma_completion);
 250         desc->callback = stm32_qspi_dma_callback;
 251         desc->callback_param = &qspi->dma_completion;
 252         cookie = dmaengine_submit(desc);
 253         err = dma_submit_error(cookie);
 254         if (err)
 255                 goto out;
 256
 257         dma_async_issue_pending(dma_ch);
 258
 259         writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
 260
 261         t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
 262         if (!wait_for_completion_timeout(&qspi->dma_completion,
 263                                          msecs_to_jiffies(t_out)))
 264                 err = -ETIMEDOUT;
 265
 266         if (err)
 267                 dmaengine_terminate_all(dma_ch);
 268
 269 out:
 270         writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
 271 out_unmap:
 272         spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
 273
 274         return err;
 275 }
 276
 277 static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
 278 {
 279         if (!op->data.nbytes)
 280                 return 0;
 281
 282         if (qspi->fmode == CCR_FMODE_MM)
 283                 return stm32_qspi_tx_mm(qspi, op);
 284         else if (((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
 285                  (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx)) &&
 286                   op->data.nbytes > 4)
 287                 if (!stm32_qspi_tx_dma(qspi, op))
 288                         return 0;
 289
 290         return stm32_qspi_tx_poll(qspi, op);
 291 }
 292
 293 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
 294 {
 295         u32 sr;
 296
 297         return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
 298                                                  !(sr & SR_BUSY), 1,
 299                                                  STM32_BUSY_TIMEOUT_US);
 300 }
 301
 302 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi)
 303 {
 304         u32 cr, sr;
 305         int err = 0;
 306
 307         if ((readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF) ||
 308             qspi->fmode == CCR_FMODE_APM)
 309                 goto out;
 310
 311         reinit_completion(&qspi->data_completion);
 312         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 313         writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
 314
 315         if (!wait_for_completion_timeout(&qspi->data_completion,
 316                                 msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
 317                 err = -ETIMEDOUT;
 318         } else {
 319                 sr = readl_relaxed(qspi->io_base + QSPI_SR);
 320                 if (sr & SR_TEF)
 321                         err = -EIO;
 322         }
 323
 324 out:
 325         /* clear flags */
 326         writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
 327         if (!err)
 328                 err = stm32_qspi_wait_nobusy(qspi);
 329
 330         return err;
 331 }
 332
 333 static int stm32_qspi_wait_poll_status(struct stm32_qspi *qspi,
 334                                        const struct spi_mem_op *op)
 335 {
 336         u32 cr;
 337
 338         reinit_completion(&qspi->match_completion);
 339         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 340         writel_relaxed(cr | CR_SMIE, qspi->io_base + QSPI_CR);
 341
 342         if (!wait_for_completion_timeout(&qspi->match_completion,
 343                                 msecs_to_jiffies(qspi->status_timeout)))
 344                 return -ETIMEDOUT;
 345
 346         writel_relaxed(FCR_CSMF, qspi->io_base + QSPI_FCR);
 347
 348         return 0;
 349 }
 350
 351 static int stm32_qspi_get_mode(u8 buswidth)
 352 {
 353         if (buswidth == 4)
 354                 return CCR_BUSWIDTH_4;
 355
 356         return buswidth;
 357 }
 358
 359 static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
 360 {
 361         struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
 362         struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
 363         u32 ccr, cr;
 364         int timeout, err = 0, err_poll_status = 0;
 365
 366         dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
 367                 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
 368                 op->dummy.buswidth, op->data.buswidth,
 369                 op->addr.val, op->data.nbytes);
 370
 371         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 372         cr &= ~CR_PRESC_MASK & ~CR_FSEL;
 373         cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
 374         cr |= FIELD_PREP(CR_FSEL, flash->cs);
 375         writel_relaxed(cr, qspi->io_base + QSPI_CR);
 376
 377         if (op->data.nbytes)
 378                 writel_relaxed(op->data.nbytes - 1,
 379                                qspi->io_base + QSPI_DLR);
 380
 381         ccr = qspi->fmode;
 382         ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
 383         ccr |= FIELD_PREP(CCR_IMODE_MASK,
 384                           stm32_qspi_get_mode(op->cmd.buswidth));
 385
 386         if (op->addr.nbytes) {
 387                 ccr |= FIELD_PREP(CCR_ADMODE_MASK,
 388                                   stm32_qspi_get_mode(op->addr.buswidth));
 389                 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
 390         }
 391
 392         if (op->dummy.nbytes)
 393                 ccr |= FIELD_PREP(CCR_DCYC_MASK,
 394                                   op->dummy.nbytes * 8 / op->dummy.buswidth);
 395
 396         if (op->data.nbytes) {
 397                 ccr |= FIELD_PREP(CCR_DMODE_MASK,
 398                                   stm32_qspi_get_mode(op->data.buswidth));
 399         }
 400
 401         writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
 402
 403         if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
 404                 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
 405
 406         if (qspi->fmode == CCR_FMODE_APM)
 407                 err_poll_status = stm32_qspi_wait_poll_status(qspi, op);
 408
 409         err = stm32_qspi_tx(qspi, op);
 410
 411         /*
 412          * Abort in:
 413          * -error case
 414          * -read memory map: prefetching must be stopped if we read the last
 415          *  byte of device (device size - fifo size). like device size is not
 416          *  knows, the prefetching is always stop.
 417          */
 418         if (err || err_poll_status || qspi->fmode == CCR_FMODE_MM)
 419                 goto abort;
 420
 421         /* wait end of tx in indirect mode */
 422         err = stm32_qspi_wait_cmd(qspi);
 423         if (err)
 424                 goto abort;
 425
 426         return 0;
 427
 428 abort:
 429         cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
 430         writel_relaxed(cr, qspi->io_base + QSPI_CR);
 431
 432         /* wait clear of abort bit by hw */
 433         timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
 434                                                     cr, !(cr & CR_ABORT), 1,
 435                                                     STM32_ABT_TIMEOUT_US);
 436
 437         writel_relaxed(FCR_CTCF | FCR_CSMF, qspi->io_base + QSPI_FCR);
 438
 439         if (err || err_poll_status || timeout)
 440                 dev_err(qspi->dev, "%s err:%d err_poll_status:%d abort timeout:%d\n",
 441                         __func__, err, err_poll_status, timeout);
 442
 443         return err;
 444 }
 445
 446 static int stm32_qspi_poll_status(struct spi_mem *mem, const struct spi_mem_op *op,
 447                                   u16 mask, u16 match,
 448                                   unsigned long initial_delay_us,
 449                                   unsigned long polling_rate_us,
 450                                   unsigned long timeout_ms)
 451 {
 452         struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
 453         int ret;
 454
 455         if (!spi_mem_supports_op(mem, op))
 456                 return -EOPNOTSUPP;
 457
 458         ret = pm_runtime_resume_and_get(qspi->dev);
 459         if (ret < 0)
 460                 return ret;
 461
 462         mutex_lock(&qspi->lock);
 463
 464         writel_relaxed(mask, qspi->io_base + QSPI_PSMKR);
 465         writel_relaxed(match, qspi->io_base + QSPI_PSMAR);
 466         qspi->fmode = CCR_FMODE_APM;
 467         qspi->status_timeout = timeout_ms;
 468
 469         ret = stm32_qspi_send(mem, op);
 470         mutex_unlock(&qspi->lock);
 471
 472         pm_runtime_mark_last_busy(qspi->dev);
 473         pm_runtime_put_autosuspend(qspi->dev);
 474
 475         return ret;
 476 }
 477
 478 static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 479 {
 480         struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
 481         int ret;
 482
 483         ret = pm_runtime_resume_and_get(qspi->dev);
 484         if (ret < 0)
 485                 return ret;
 486
 487         mutex_lock(&qspi->lock);
 488         if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes)
 489                 qspi->fmode = CCR_FMODE_INDR;
 490         else
 491                 qspi->fmode = CCR_FMODE_INDW;
 492
 493         ret = stm32_qspi_send(mem, op);
 494         mutex_unlock(&qspi->lock);
 495
 496         pm_runtime_mark_last_busy(qspi->dev);
 497         pm_runtime_put_autosuspend(qspi->dev);
 498
 499         return ret;
 500 }
 501
 502 static int stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc)
 503 {
 504         struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->master);
 505
 506         if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
 507                 return -EOPNOTSUPP;
 508
 509         /* should never happen, as mm_base == null is an error probe exit condition */
 510         if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
 511                 return -EOPNOTSUPP;
 512
 513         if (!qspi->mm_size)
 514                 return -EOPNOTSUPP;
 515
 516         return 0;
 517 }
 518
 519 static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc,
 520                                       u64 offs, size_t len, void *buf)
 521 {
 522         struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->master);
 523         struct spi_mem_op op;
 524         u32 addr_max;
 525         int ret;
 526
 527         ret = pm_runtime_resume_and_get(qspi->dev);
 528         if (ret < 0)
 529                 return ret;
 530
 531         mutex_lock(&qspi->lock);
 532         /* make a local copy of desc op_tmpl and complete dirmap rdesc
 533          * spi_mem_op template with offs, len and *buf in  order to get
 534          * all needed transfer information into struct spi_mem_op
 535          */
 536         memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
 537         dev_dbg(qspi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
 538
 539         op.data.nbytes = len;
 540         op.addr.val = desc->info.offset + offs;
 541         op.data.buf.in = buf;
 542
 543         addr_max = op.addr.val + op.data.nbytes + 1;
 544         if (addr_max < qspi->mm_size && op.addr.buswidth)
 545                 qspi->fmode = CCR_FMODE_MM;
 546         else
 547                 qspi->fmode = CCR_FMODE_INDR;
 548
 549         ret = stm32_qspi_send(desc->mem, &op);
 550         mutex_unlock(&qspi->lock);
 551
 552         pm_runtime_mark_last_busy(qspi->dev);
 553         pm_runtime_put_autosuspend(qspi->dev);
 554
 555         return ret ?: len;
 556 }
 557
 558 static int stm32_qspi_setup(struct spi_device *spi)
 559 {
 560         struct spi_controller *ctrl = spi->master;
 561         struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
 562         struct stm32_qspi_flash *flash;
 563         u32 presc;
 564         int ret;
 565
 566         if (ctrl->busy)
 567                 return -EBUSY;
 568
 569         if (!spi->max_speed_hz)
 570                 return -EINVAL;
 571
 572         ret = pm_runtime_resume_and_get(qspi->dev);
 573         if (ret < 0)
 574                 return ret;
 575
 576         presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
 577
 578         flash = &qspi->flash[spi->chip_select];
 579         flash->cs = spi->chip_select;
 580         flash->presc = presc;
 581
 582         mutex_lock(&qspi->lock);
 583         qspi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
 584         writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
 585
 586         /* set dcr fsize to max address */
 587         qspi->dcr_reg = DCR_FSIZE_MASK;
 588         writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
 589         mutex_unlock(&qspi->lock);
 590
 591         pm_runtime_mark_last_busy(qspi->dev);
 592         pm_runtime_put_autosuspend(qspi->dev);
 593
 594         return 0;
 595 }
 596
 597 static int stm32_qspi_dma_setup(struct stm32_qspi *qspi)
 598 {
 599         struct dma_slave_config dma_cfg;
 600         struct device *dev = qspi->dev;
 601         int ret = 0;
 602
 603         memset(&dma_cfg, 0, sizeof(dma_cfg));
 604
 605         dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 606         dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 607         dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
 608         dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
 609         dma_cfg.src_maxburst = 4;
 610         dma_cfg.dst_maxburst = 4;
 611
 612         qspi->dma_chrx = dma_request_chan(dev, "rx");
 613         if (IS_ERR(qspi->dma_chrx)) {
 614                 ret = PTR_ERR(qspi->dma_chrx);
 615                 qspi->dma_chrx = NULL;
 616                 if (ret == -EPROBE_DEFER)
 617                         goto out;
 618         } else {
 619                 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
 620                         dev_err(dev, "dma rx config failed\n");
 621                         dma_release_channel(qspi->dma_chrx);
 622                         qspi->dma_chrx = NULL;
 623                 }
 624         }
 625
 626         qspi->dma_chtx = dma_request_chan(dev, "tx");
 627         if (IS_ERR(qspi->dma_chtx)) {
 628                 ret = PTR_ERR(qspi->dma_chtx);
 629                 qspi->dma_chtx = NULL;
 630         } else {
 631                 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
 632                         dev_err(dev, "dma tx config failed\n");
 633                         dma_release_channel(qspi->dma_chtx);
 634                         qspi->dma_chtx = NULL;
 635                 }
 636         }
 637
 638 out:
 639         init_completion(&qspi->dma_completion);
 640
 641         if (ret != -EPROBE_DEFER)
 642                 ret = 0;
 643
 644         return ret;
 645 }
 646
 647 static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
 648 {
 649         if (qspi->dma_chtx)
 650                 dma_release_channel(qspi->dma_chtx);
 651         if (qspi->dma_chrx)
 652                 dma_release_channel(qspi->dma_chrx);
 653 }
 654
 655 /*
 656  * no special host constraint, so use default spi_mem_default_supports_op
 657  * to check supported mode.
 658  */
 659 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
 660         .exec_op        = stm32_qspi_exec_op,
 661         .dirmap_create  = stm32_qspi_dirmap_create,
 662         .dirmap_read    = stm32_qspi_dirmap_read,
 663         .poll_status    = stm32_qspi_poll_status,
 664 };
 665
 666 static int stm32_qspi_probe(struct platform_device *pdev)
 667 {
 668         struct device *dev = &pdev->dev;
 669         struct spi_controller *ctrl;
 670         struct reset_control *rstc;
 671         struct stm32_qspi *qspi;
 672         struct resource *res;
 673         int ret, irq;
 674
 675         ctrl = devm_spi_alloc_master(dev, sizeof(*qspi));
 676         if (!ctrl)
 677                 return -ENOMEM;
 678
 679         qspi = spi_controller_get_devdata(ctrl);
 680         qspi->ctrl = ctrl;
 681
 682         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
 683         qspi->io_base = devm_ioremap_resource(dev, res);
 684         if (IS_ERR(qspi->io_base))
 685                 return PTR_ERR(qspi->io_base);
 686
 687         qspi->phys_base = res->start;
 688
 689         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
 690         qspi->mm_base = devm_ioremap_resource(dev, res);
 691         if (IS_ERR(qspi->mm_base))
 692                 return PTR_ERR(qspi->mm_base);
 693
 694         qspi->mm_size = resource_size(res);
 695         if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ)
 696                 return -EINVAL;
 697
 698         irq = platform_get_irq(pdev, 0);
 699         if (irq < 0)
 700                 return irq;
 701
 702         ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
 703                                dev_name(dev), qspi);
 704         if (ret) {
 705                 dev_err(dev, "failed to request irq\n");
 706                 return ret;
 707         }
 708
 709         init_completion(&qspi->data_completion);
 710         init_completion(&qspi->match_completion);
 711
 712         qspi->clk = devm_clk_get(dev, NULL);
 713         if (IS_ERR(qspi->clk))
 714                 return PTR_ERR(qspi->clk);
 715
 716         qspi->clk_rate = clk_get_rate(qspi->clk);
 717         if (!qspi->clk_rate)
 718                 return -EINVAL;
 719
 720         ret = clk_prepare_enable(qspi->clk);
 721         if (ret) {
 722                 dev_err(dev, "can not enable the clock\n");
 723                 return ret;
 724         }
 725
 726         rstc = devm_reset_control_get_exclusive(dev, NULL);
 727         if (IS_ERR(rstc)) {
 728                 ret = PTR_ERR(rstc);
 729                 if (ret == -EPROBE_DEFER)
 730                         goto err_clk_disable;
 731         } else {
 732                 reset_control_assert(rstc);
 733                 udelay(2);
 734                 reset_control_deassert(rstc);
 735         }
 736
 737         qspi->dev = dev;
 738         platform_set_drvdata(pdev, qspi);
 739         ret = stm32_qspi_dma_setup(qspi);
 740         if (ret)
 741                 goto err_dma_free;
 742
 743         mutex_init(&qspi->lock);
 744
 745         ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
 746                 | SPI_TX_DUAL | SPI_TX_QUAD;
 747         ctrl->setup = stm32_qspi_setup;
 748         ctrl->bus_num = -1;
 749         ctrl->mem_ops = &stm32_qspi_mem_ops;
 750         ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
 751         ctrl->dev.of_node = dev->of_node;
 752
 753         pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY);
 754         pm_runtime_use_autosuspend(dev);
 755         pm_runtime_set_active(dev);
 756         pm_runtime_enable(dev);
 757         pm_runtime_get_noresume(dev);
 758
 759         ret = spi_register_master(ctrl);
 760         if (ret)
 761                 goto err_pm_runtime_free;
 762
 763         pm_runtime_mark_last_busy(dev);
 764         pm_runtime_put_autosuspend(dev);
 765
 766         return 0;
 767
 768 err_pm_runtime_free:
 769         pm_runtime_get_sync(qspi->dev);
 770         /* disable qspi */
 771         writel_relaxed(0, qspi->io_base + QSPI_CR);
 772         mutex_destroy(&qspi->lock);
 773         pm_runtime_put_noidle(qspi->dev);
 774         pm_runtime_disable(qspi->dev);
 775         pm_runtime_set_suspended(qspi->dev);
 776         pm_runtime_dont_use_autosuspend(qspi->dev);
 777 err_dma_free:
 778         stm32_qspi_dma_free(qspi);
 779 err_clk_disable:
 780         clk_disable_unprepare(qspi->clk);
 781
 782         return ret;
 783 }
 784
 785 static int stm32_qspi_remove(struct platform_device *pdev)
 786 {
 787         struct stm32_qspi *qspi = platform_get_drvdata(pdev);
 788
 789         pm_runtime_get_sync(qspi->dev);
 790         spi_unregister_master(qspi->ctrl);
 791         /* disable qspi */
 792         writel_relaxed(0, qspi->io_base + QSPI_CR);
 793         stm32_qspi_dma_free(qspi);
 794         mutex_destroy(&qspi->lock);
 795         pm_runtime_put_noidle(qspi->dev);
 796         pm_runtime_disable(qspi->dev);
 797         pm_runtime_set_suspended(qspi->dev);
 798         pm_runtime_dont_use_autosuspend(qspi->dev);
 799         clk_disable_unprepare(qspi->clk);
 800
 801         return 0;
 802 }
 803
 804 static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev)
 805 {
 806         struct stm32_qspi *qspi = dev_get_drvdata(dev);
 807
 808         clk_disable_unprepare(qspi->clk);
 809
 810         return 0;
 811 }
 812
 813 static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev)
 814 {
 815         struct stm32_qspi *qspi = dev_get_drvdata(dev);
 816
 817         return clk_prepare_enable(qspi->clk);
 818 }
 819
 820 static int __maybe_unused stm32_qspi_suspend(struct device *dev)
 821 {
 822         pinctrl_pm_select_sleep_state(dev);
 823
 824         return pm_runtime_force_suspend(dev);
 825 }
 826
 827 static int __maybe_unused stm32_qspi_resume(struct device *dev)
 828 {
 829         struct stm32_qspi *qspi = dev_get_drvdata(dev);
 830         int ret;
 831
 832         ret = pm_runtime_force_resume(dev);
 833         if (ret < 0)
 834                 return ret;
 835
 836         pinctrl_pm_select_default_state(dev);
 837
 838         ret = pm_runtime_resume_and_get(dev);
 839         if (ret < 0)
 840                 return ret;
 841
 842         writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
 843         writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
 844
 845         pm_runtime_mark_last_busy(dev);
 846         pm_runtime_put_autosuspend(dev);
 847
 848         return 0;
 849 }
 850
 851 static const struct dev_pm_ops stm32_qspi_pm_ops = {
 852         SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend,
 853                            stm32_qspi_runtime_resume, NULL)
 854         SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume)
 855 };
 856
 857 static const struct of_device_id stm32_qspi_match[] = {
 858         {.compatible = "st,stm32f469-qspi"},
 859         {}
 860 };
 861 MODULE_DEVICE_TABLE(of, stm32_qspi_match);
 862
 863 static struct platform_driver stm32_qspi_driver = {
 864         .probe  = stm32_qspi_probe,
 865         .remove = stm32_qspi_remove,
 866         .driver = {
 867                 .name = "stm32-qspi",
 868                 .of_match_table = stm32_qspi_match,
 869                 .pm = &stm32_qspi_pm_ops,
 870         },
 871 };
 872 module_platform_driver(stm32_qspi_driver);
 873
 874 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
 875 MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
 876 MODULE_LICENSE("GPL v2");