drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/delay.h>
  20 #include <linux/clk.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/gpio.h>
  27 #include <linux/of.h>
  28 #include <linux/of_gpio.h>
  29
  30 #include <linux/platform_data/spi-s3c64xx.h>
  31
  32 #define MAX_SPI_PORTS           6
  33 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  34 #define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
  35 #define AUTOSUSPEND_TIMEOUT     2000
  36
  37 /* Registers and bit-fields */
  38
  39 #define S3C64XX_SPI_CH_CFG              0x00
  40 #define S3C64XX_SPI_CLK_CFG             0x04
  41 #define S3C64XX_SPI_MODE_CFG    0x08
  42 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  43 #define S3C64XX_SPI_INT_EN              0x10
  44 #define S3C64XX_SPI_STATUS              0x14
  45 #define S3C64XX_SPI_TX_DATA             0x18
  46 #define S3C64XX_SPI_RX_DATA             0x1C
  47 #define S3C64XX_SPI_PACKET_CNT  0x20
  48 #define S3C64XX_SPI_PENDING_CLR 0x24
  49 #define S3C64XX_SPI_SWAP_CFG    0x28
  50 #define S3C64XX_SPI_FB_CLK              0x2C
  51
  52 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  53 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  54 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  55 #define S3C64XX_SPI_CPOL_L              (1<<3)
  56 #define S3C64XX_SPI_CPHA_B              (1<<2)
  57 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  58 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  59
  60 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  61 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  62 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  63 #define S3C64XX_SPI_PSR_MASK            0xff
  64
  65 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  66 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  67 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  68 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  69 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  70 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  71 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  72 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  73 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  74 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  75 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  76
  77 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  78 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  79 #define S3C64XX_SPI_SLAVE_NSC_CNT_2             (2<<4)
  80
  81 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  88
  89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  93 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  94 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  95
  96 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  97
  98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
  99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 102 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 103
 104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 105 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 106 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 107 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 109 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 110 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 111 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 112
 113 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 114
 115 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 116 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 117                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 118 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 119 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 120                                         FIFO_LVL_MASK(i))
 121
 122 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 123 #define S3C64XX_SPI_TRAILCNT_OFF        19
 124
 125 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 126
 127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 128 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 129
 130 #define RXBUSY    (1<<2)
 131 #define TXBUSY    (1<<3)
 132
 133 struct s3c64xx_spi_dma_data {
 134         struct dma_chan *ch;
 135         enum dma_transfer_direction direction;
 136 };
 137
 138 /**
 139  * struct s3c64xx_spi_info - SPI Controller hardware info
 140  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 141  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 142  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 143  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 144  * @clk_from_cmu: True, if the controller does not include a clock mux and
 145  *      prescaler unit.
 146  *
 147  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 148  * differ in some aspects such as the size of the fifo and spi bus clock
 149  * setup. Such differences are specified to the driver using this structure
 150  * which is provided as driver data to the driver.
 151  */
 152 struct s3c64xx_spi_port_config {
 153         int     fifo_lvl_mask[MAX_SPI_PORTS];
 154         int     rx_lvl_offset;
 155         int     tx_st_done;
 156         int     quirks;
 157         bool    high_speed;
 158         bool    clk_from_cmu;
 159 };
 160
 161 /**
 162  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 163  * @clk: Pointer to the spi clock.
 164  * @src_clk: Pointer to the clock used to generate SPI signals.
 165  * @master: Pointer to the SPI Protocol master.
 166  * @cntrlr_info: Platform specific data for the controller this driver manages.
 167  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 168  * @lock: Controller specific lock.
 169  * @state: Set of FLAGS to indicate status.
 170  * @rx_dmach: Controller's DMA channel for Rx.
 171  * @tx_dmach: Controller's DMA channel for Tx.
 172  * @sfr_start: BUS address of SPI controller regs.
 173  * @regs: Pointer to ioremap'ed controller registers.
 174  * @irq: interrupt
 175  * @xfer_completion: To indicate completion of xfer task.
 176  * @cur_mode: Stores the active configuration of the controller.
 177  * @cur_bpw: Stores the active bits per word settings.
 178  * @cur_speed: Stores the active xfer clock speed.
 179  */
 180 struct s3c64xx_spi_driver_data {
 181         void __iomem                    *regs;
 182         struct clk                      *clk;
 183         struct clk                      *src_clk;
 184         struct platform_device          *pdev;
 185         struct spi_master               *master;
 186         struct s3c64xx_spi_info  *cntrlr_info;
 187         struct spi_device               *tgl_spi;
 188         spinlock_t                      lock;
 189         unsigned long                   sfr_start;
 190         struct completion               xfer_completion;
 191         unsigned                        state;
 192         unsigned                        cur_mode, cur_bpw;
 193         unsigned                        cur_speed;
 194         struct s3c64xx_spi_dma_data     rx_dma;
 195         struct s3c64xx_spi_dma_data     tx_dma;
 196         struct s3c64xx_spi_port_config  *port_conf;
 197         unsigned int                    port_id;
 198 };
 199
 200 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 201 {
 202         void __iomem *regs = sdd->regs;
 203         unsigned long loops;
 204         u32 val;
 205
 206         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 207
 208         val = readl(regs + S3C64XX_SPI_CH_CFG);
 209         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 210         writel(val, regs + S3C64XX_SPI_CH_CFG);
 211
 212         val = readl(regs + S3C64XX_SPI_CH_CFG);
 213         val |= S3C64XX_SPI_CH_SW_RST;
 214         val &= ~S3C64XX_SPI_CH_HS_EN;
 215         writel(val, regs + S3C64XX_SPI_CH_CFG);
 216
 217         /* Flush TxFIFO*/
 218         loops = msecs_to_loops(1);
 219         do {
 220                 val = readl(regs + S3C64XX_SPI_STATUS);
 221         } while (TX_FIFO_LVL(val, sdd) && loops--);
 222
 223         if (loops == 0)
 224                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 225
 226         /* Flush RxFIFO*/
 227         loops = msecs_to_loops(1);
 228         do {
 229                 val = readl(regs + S3C64XX_SPI_STATUS);
 230                 if (RX_FIFO_LVL(val, sdd))
 231                         readl(regs + S3C64XX_SPI_RX_DATA);
 232                 else
 233                         break;
 234         } while (loops--);
 235
 236         if (loops == 0)
 237                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 238
 239         val = readl(regs + S3C64XX_SPI_CH_CFG);
 240         val &= ~S3C64XX_SPI_CH_SW_RST;
 241         writel(val, regs + S3C64XX_SPI_CH_CFG);
 242
 243         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 244         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 245         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 246 }
 247
 248 static void s3c64xx_spi_dmacb(void *data)
 249 {
 250         struct s3c64xx_spi_driver_data *sdd;
 251         struct s3c64xx_spi_dma_data *dma = data;
 252         unsigned long flags;
 253
 254         if (dma->direction == DMA_DEV_TO_MEM)
 255                 sdd = container_of(data,
 256                         struct s3c64xx_spi_driver_data, rx_dma);
 257         else
 258                 sdd = container_of(data,
 259                         struct s3c64xx_spi_driver_data, tx_dma);
 260
 261         spin_lock_irqsave(&sdd->lock, flags);
 262
 263         if (dma->direction == DMA_DEV_TO_MEM) {
 264                 sdd->state &= ~RXBUSY;
 265                 if (!(sdd->state & TXBUSY))
 266                         complete(&sdd->xfer_completion);
 267         } else {
 268                 sdd->state &= ~TXBUSY;
 269                 if (!(sdd->state & RXBUSY))
 270                         complete(&sdd->xfer_completion);
 271         }
 272
 273         spin_unlock_irqrestore(&sdd->lock, flags);
 274 }
 275
 276 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 277                         struct sg_table *sgt)
 278 {
 279         struct s3c64xx_spi_driver_data *sdd;
 280         struct dma_slave_config config;
 281         struct dma_async_tx_descriptor *desc;
 282
 283         memset(&config, 0, sizeof(config));
 284
 285         if (dma->direction == DMA_DEV_TO_MEM) {
 286                 sdd = container_of((void *)dma,
 287                         struct s3c64xx_spi_driver_data, rx_dma);
 288                 config.direction = dma->direction;
 289                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 290                 config.src_addr_width = sdd->cur_bpw / 8;
 291                 config.src_maxburst = 1;
 292                 dmaengine_slave_config(dma->ch, &config);
 293         } else {
 294                 sdd = container_of((void *)dma,
 295                         struct s3c64xx_spi_driver_data, tx_dma);
 296                 config.direction = dma->direction;
 297                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 298                 config.dst_addr_width = sdd->cur_bpw / 8;
 299                 config.dst_maxburst = 1;
 300                 dmaengine_slave_config(dma->ch, &config);
 301         }
 302
 303         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
 304                                        dma->direction, DMA_PREP_INTERRUPT);
 305
 306         desc->callback = s3c64xx_spi_dmacb;
 307         desc->callback_param = dma;
 308
 309         dmaengine_submit(desc);
 310         dma_async_issue_pending(dma->ch);
 311 }
 312
 313 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
 314 {
 315         struct s3c64xx_spi_driver_data *sdd =
 316                                         spi_master_get_devdata(spi->master);
 317
 318         if (enable) {
 319                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
 320                         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 321                 } else {
 322                         u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 323
 324                         ssel |= (S3C64XX_SPI_SLAVE_AUTO |
 325                                                 S3C64XX_SPI_SLAVE_NSC_CNT_2);
 326                         writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 327                 }
 328         } else {
 329                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 330                 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
 331                 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 332         }
 333 }
 334
 335 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 336 {
 337         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 338         dma_filter_fn filter = sdd->cntrlr_info->filter;
 339         struct device *dev = &sdd->pdev->dev;
 340         dma_cap_mask_t mask;
 341         int ret;
 342
 343         if (!is_polling(sdd)) {
 344                 dma_cap_zero(mask);
 345                 dma_cap_set(DMA_SLAVE, mask);
 346
 347                 /* Acquire DMA channels */
 348                 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 349                                    sdd->cntrlr_info->dma_rx, dev, "rx");
 350                 if (!sdd->rx_dma.ch) {
 351                         dev_err(dev, "Failed to get RX DMA channel\n");
 352                         ret = -EBUSY;
 353                         goto out;
 354                 }
 355                 spi->dma_rx = sdd->rx_dma.ch;
 356
 357                 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 358                                    sdd->cntrlr_info->dma_tx, dev, "tx");
 359                 if (!sdd->tx_dma.ch) {
 360                         dev_err(dev, "Failed to get TX DMA channel\n");
 361                         ret = -EBUSY;
 362                         goto out_rx;
 363                 }
 364                 spi->dma_tx = sdd->tx_dma.ch;
 365         }
 366
 367         return 0;
 368
 369 out_rx:
 370         dma_release_channel(sdd->rx_dma.ch);
 371 out:
 372         return ret;
 373 }
 374
 375 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 376 {
 377         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 378
 379         /* Free DMA channels */
 380         if (!is_polling(sdd)) {
 381                 dma_release_channel(sdd->rx_dma.ch);
 382                 dma_release_channel(sdd->tx_dma.ch);
 383         }
 384
 385         return 0;
 386 }
 387
 388 static bool s3c64xx_spi_can_dma(struct spi_master *master,
 389                                 struct spi_device *spi,
 390                                 struct spi_transfer *xfer)
 391 {
 392         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 393
 394         return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
 395 }
 396
 397 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 398                                 struct spi_device *spi,
 399                                 struct spi_transfer *xfer, int dma_mode)
 400 {
 401         void __iomem *regs = sdd->regs;
 402         u32 modecfg, chcfg;
 403
 404         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 405         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 406
 407         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 408         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 409
 410         if (dma_mode) {
 411                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 412         } else {
 413                 /* Always shift in data in FIFO, even if xfer is Tx only,
 414                  * this helps setting PCKT_CNT value for generating clocks
 415                  * as exactly needed.
 416                  */
 417                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 418                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 419                                         | S3C64XX_SPI_PACKET_CNT_EN,
 420                                         regs + S3C64XX_SPI_PACKET_CNT);
 421         }
 422
 423         if (xfer->tx_buf != NULL) {
 424                 sdd->state |= TXBUSY;
 425                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 426                 if (dma_mode) {
 427                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 428                         prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
 429                 } else {
 430                         switch (sdd->cur_bpw) {
 431                         case 32:
 432                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 433                                         xfer->tx_buf, xfer->len / 4);
 434                                 break;
 435                         case 16:
 436                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 437                                         xfer->tx_buf, xfer->len / 2);
 438                                 break;
 439                         default:
 440                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 441                                         xfer->tx_buf, xfer->len);
 442                                 break;
 443                         }
 444                 }
 445         }
 446
 447         if (xfer->rx_buf != NULL) {
 448                 sdd->state |= RXBUSY;
 449
 450                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 451                                         && !(sdd->cur_mode & SPI_CPHA))
 452                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 453
 454                 if (dma_mode) {
 455                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 456                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 457                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 458                                         | S3C64XX_SPI_PACKET_CNT_EN,
 459                                         regs + S3C64XX_SPI_PACKET_CNT);
 460                         prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
 461                 }
 462         }
 463
 464         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 465         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 466 }
 467
 468 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 469                                         int timeout_ms)
 470 {
 471         void __iomem *regs = sdd->regs;
 472         unsigned long val = 1;
 473         u32 status;
 474
 475         /* max fifo depth available */
 476         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 477
 478         if (timeout_ms)
 479                 val = msecs_to_loops(timeout_ms);
 480
 481         do {
 482                 status = readl(regs + S3C64XX_SPI_STATUS);
 483         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 484
 485         /* return the actual received data length */
 486         return RX_FIFO_LVL(status, sdd);
 487 }
 488
 489 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
 490                         struct spi_transfer *xfer)
 491 {
 492         void __iomem *regs = sdd->regs;
 493         unsigned long val;
 494         u32 status;
 495         int ms;
 496
 497         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 498         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 499         ms += 10; /* some tolerance */
 500
 501         val = msecs_to_jiffies(ms) + 10;
 502         val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 503
 504         /*
 505          * If the previous xfer was completed within timeout, then
 506          * proceed further else return -EIO.
 507          * DmaTx returns after simply writing data in the FIFO,
 508          * w/o waiting for real transmission on the bus to finish.
 509          * DmaRx returns only after Dma read data from FIFO which
 510          * needs bus transmission to finish, so we don't worry if
 511          * Xfer involved Rx(with or without Tx).
 512          */
 513         if (val && !xfer->rx_buf) {
 514                 val = msecs_to_loops(10);
 515                 status = readl(regs + S3C64XX_SPI_STATUS);
 516                 while ((TX_FIFO_LVL(status, sdd)
 517                         || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 518                        && --val) {
 519                         cpu_relax();
 520                         status = readl(regs + S3C64XX_SPI_STATUS);
 521                 }
 522
 523         }
 524
 525         /* If timed out while checking rx/tx status return error */
 526         if (!val)
 527                 return -EIO;
 528
 529         return 0;
 530 }
 531
 532 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
 533                         struct spi_transfer *xfer)
 534 {
 535         void __iomem *regs = sdd->regs;
 536         unsigned long val;
 537         u32 status;
 538         int loops;
 539         u32 cpy_len;
 540         u8 *buf;
 541         int ms;
 542
 543         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 544         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 545         ms += 10; /* some tolerance */
 546
 547         val = msecs_to_loops(ms);
 548         do {
 549                 status = readl(regs + S3C64XX_SPI_STATUS);
 550         } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 551
 552
 553         /* If it was only Tx */
 554         if (!xfer->rx_buf) {
 555                 sdd->state &= ~TXBUSY;
 556                 return 0;
 557         }
 558
 559         /*
 560          * If the receive length is bigger than the controller fifo
 561          * size, calculate the loops and read the fifo as many times.
 562          * loops = length / max fifo size (calculated by using the
 563          * fifo mask).
 564          * For any size less than the fifo size the below code is
 565          * executed atleast once.
 566          */
 567         loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 568         buf = xfer->rx_buf;
 569         do {
 570                 /* wait for data to be received in the fifo */
 571                 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 572                                                        (loops ? ms : 0));
 573
 574                 switch (sdd->cur_bpw) {
 575                 case 32:
 576                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 577                                      buf, cpy_len / 4);
 578                         break;
 579                 case 16:
 580                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 581                                      buf, cpy_len / 2);
 582                         break;
 583                 default:
 584                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 585                                     buf, cpy_len);
 586                         break;
 587                 }
 588
 589                 buf = buf + cpy_len;
 590         } while (loops--);
 591         sdd->state &= ~RXBUSY;
 592
 593         return 0;
 594 }
 595
 596 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 597 {
 598         void __iomem *regs = sdd->regs;
 599         u32 val;
 600
 601         /* Disable Clock */
 602         if (sdd->port_conf->clk_from_cmu) {
 603                 clk_disable_unprepare(sdd->src_clk);
 604         } else {
 605                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 606                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 607                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 608         }
 609
 610         /* Set Polarity and Phase */
 611         val = readl(regs + S3C64XX_SPI_CH_CFG);
 612         val &= ~(S3C64XX_SPI_CH_SLAVE |
 613                         S3C64XX_SPI_CPOL_L |
 614                         S3C64XX_SPI_CPHA_B);
 615
 616         if (sdd->cur_mode & SPI_CPOL)
 617                 val |= S3C64XX_SPI_CPOL_L;
 618
 619         if (sdd->cur_mode & SPI_CPHA)
 620                 val |= S3C64XX_SPI_CPHA_B;
 621
 622         writel(val, regs + S3C64XX_SPI_CH_CFG);
 623
 624         /* Set Channel & DMA Mode */
 625         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 626         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 627                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 628
 629         switch (sdd->cur_bpw) {
 630         case 32:
 631                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 632                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 633                 break;
 634         case 16:
 635                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 636                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 637                 break;
 638         default:
 639                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 640                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 641                 break;
 642         }
 643
 644         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 645
 646         if (sdd->port_conf->clk_from_cmu) {
 647                 /* Configure Clock */
 648                 /* There is half-multiplier before the SPI */
 649                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 650                 /* Enable Clock */
 651                 clk_prepare_enable(sdd->src_clk);
 652         } else {
 653                 /* Configure Clock */
 654                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 655                 val &= ~S3C64XX_SPI_PSR_MASK;
 656                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 657                                 & S3C64XX_SPI_PSR_MASK);
 658                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 659
 660                 /* Enable Clock */
 661                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 662                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 663                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 664         }
 665 }
 666
 667 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 668
 669 static int s3c64xx_spi_prepare_message(struct spi_master *master,
 670                                        struct spi_message *msg)
 671 {
 672         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 673         struct spi_device *spi = msg->spi;
 674         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 675
 676         /* If Master's(controller) state differs from that needed by Slave */
 677         if (sdd->cur_speed != spi->max_speed_hz
 678                         || sdd->cur_mode != spi->mode
 679                         || sdd->cur_bpw != spi->bits_per_word) {
 680                 sdd->cur_bpw = spi->bits_per_word;
 681                 sdd->cur_speed = spi->max_speed_hz;
 682                 sdd->cur_mode = spi->mode;
 683                 s3c64xx_spi_config(sdd);
 684         }
 685
 686         /* Configure feedback delay */
 687         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 688
 689         return 0;
 690 }
 691
 692 static int s3c64xx_spi_transfer_one(struct spi_master *master,
 693                                     struct spi_device *spi,
 694                                     struct spi_transfer *xfer)
 695 {
 696         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 697         int status;
 698         u32 speed;
 699         u8 bpw;
 700         unsigned long flags;
 701         int use_dma;
 702
 703         reinit_completion(&sdd->xfer_completion);
 704
 705         /* Only BPW and Speed may change across transfers */
 706         bpw = xfer->bits_per_word;
 707         speed = xfer->speed_hz;
 708
 709         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 710                 sdd->cur_bpw = bpw;
 711                 sdd->cur_speed = speed;
 712                 s3c64xx_spi_config(sdd);
 713         }
 714
 715         /* Polling method for xfers not bigger than FIFO capacity */
 716         use_dma = 0;
 717         if (!is_polling(sdd) &&
 718             (sdd->rx_dma.ch && sdd->tx_dma.ch &&
 719              (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
 720                 use_dma = 1;
 721
 722         spin_lock_irqsave(&sdd->lock, flags);
 723
 724         /* Pending only which is to be done */
 725         sdd->state &= ~RXBUSY;
 726         sdd->state &= ~TXBUSY;
 727
 728         enable_datapath(sdd, spi, xfer, use_dma);
 729
 730         /* Start the signals */
 731         s3c64xx_spi_set_cs(spi, true);
 732
 733         spin_unlock_irqrestore(&sdd->lock, flags);
 734
 735         if (use_dma)
 736                 status = wait_for_dma(sdd, xfer);
 737         else
 738                 status = wait_for_pio(sdd, xfer);
 739
 740         if (status) {
 741                 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 742                         xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 743                         (sdd->state & RXBUSY) ? 'f' : 'p',
 744                         (sdd->state & TXBUSY) ? 'f' : 'p',
 745                         xfer->len);
 746
 747                 if (use_dma) {
 748                         if (xfer->tx_buf != NULL
 749                             && (sdd->state & TXBUSY))
 750                                 dmaengine_terminate_all(sdd->tx_dma.ch);
 751                         if (xfer->rx_buf != NULL
 752                             && (sdd->state & RXBUSY))
 753                                 dmaengine_terminate_all(sdd->rx_dma.ch);
 754                 }
 755         } else {
 756                 flush_fifo(sdd);
 757         }
 758
 759         return status;
 760 }
 761
 762 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 763                                 struct spi_device *spi)
 764 {
 765         struct s3c64xx_spi_csinfo *cs;
 766         struct device_node *slave_np, *data_np = NULL;
 767         u32 fb_delay = 0;
 768
 769         slave_np = spi->dev.of_node;
 770         if (!slave_np) {
 771                 dev_err(&spi->dev, "device node not found\n");
 772                 return ERR_PTR(-EINVAL);
 773         }
 774
 775         data_np = of_get_child_by_name(slave_np, "controller-data");
 776         if (!data_np) {
 777                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 778                 return ERR_PTR(-EINVAL);
 779         }
 780
 781         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 782         if (!cs) {
 783                 of_node_put(data_np);
 784                 return ERR_PTR(-ENOMEM);
 785         }
 786
 787         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 788         cs->fb_delay = fb_delay;
 789         of_node_put(data_np);
 790         return cs;
 791 }
 792
 793 /*
 794  * Here we only check the validity of requested configuration
 795  * and save the configuration in a local data-structure.
 796  * The controller is actually configured only just before we
 797  * get a message to transfer.
 798  */
 799 static int s3c64xx_spi_setup(struct spi_device *spi)
 800 {
 801         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 802         struct s3c64xx_spi_driver_data *sdd;
 803         struct s3c64xx_spi_info *sci;
 804         int err;
 805
 806         sdd = spi_master_get_devdata(spi->master);
 807         if (spi->dev.of_node) {
 808                 cs = s3c64xx_get_slave_ctrldata(spi);
 809                 spi->controller_data = cs;
 810         } else if (cs) {
 811                 /* On non-DT platforms the SPI core will set spi->cs_gpio
 812                  * to -ENOENT. The GPIO pin used to drive the chip select
 813                  * is defined by using platform data so spi->cs_gpio value
 814                  * has to be override to have the proper GPIO pin number.
 815                  */
 816                 spi->cs_gpio = cs->line;
 817         }
 818
 819         if (IS_ERR_OR_NULL(cs)) {
 820                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 821                 return -ENODEV;
 822         }
 823
 824         if (!spi_get_ctldata(spi)) {
 825                 if (gpio_is_valid(spi->cs_gpio)) {
 826                         err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
 827                                                dev_name(&spi->dev));
 828                         if (err) {
 829                                 dev_err(&spi->dev,
 830                                         "Failed to get /CS gpio [%d]: %d\n",
 831                                         spi->cs_gpio, err);
 832                                 goto err_gpio_req;
 833                         }
 834                 }
 835
 836                 spi_set_ctldata(spi, cs);
 837         }
 838
 839         sci = sdd->cntrlr_info;
 840
 841         pm_runtime_get_sync(&sdd->pdev->dev);
 842
 843         /* Check if we can provide the requested rate */
 844         if (!sdd->port_conf->clk_from_cmu) {
 845                 u32 psr, speed;
 846
 847                 /* Max possible */
 848                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 849
 850                 if (spi->max_speed_hz > speed)
 851                         spi->max_speed_hz = speed;
 852
 853                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 854                 psr &= S3C64XX_SPI_PSR_MASK;
 855                 if (psr == S3C64XX_SPI_PSR_MASK)
 856                         psr--;
 857
 858                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 859                 if (spi->max_speed_hz < speed) {
 860                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 861                                 psr++;
 862                         } else {
 863                                 err = -EINVAL;
 864                                 goto setup_exit;
 865                         }
 866                 }
 867
 868                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 869                 if (spi->max_speed_hz >= speed) {
 870                         spi->max_speed_hz = speed;
 871                 } else {
 872                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
 873                                 spi->max_speed_hz);
 874                         err = -EINVAL;
 875                         goto setup_exit;
 876                 }
 877         }
 878
 879         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 880         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 881         s3c64xx_spi_set_cs(spi, false);
 882
 883         return 0;
 884
 885 setup_exit:
 886         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 887         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 888         /* setup() returns with device de-selected */
 889         s3c64xx_spi_set_cs(spi, false);
 890
 891         if (gpio_is_valid(spi->cs_gpio))
 892                 gpio_free(spi->cs_gpio);
 893         spi_set_ctldata(spi, NULL);
 894
 895 err_gpio_req:
 896         if (spi->dev.of_node)
 897                 kfree(cs);
 898
 899         return err;
 900 }
 901
 902 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 903 {
 904         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 905
 906         if (gpio_is_valid(spi->cs_gpio)) {
 907                 gpio_free(spi->cs_gpio);
 908                 if (spi->dev.of_node)
 909                         kfree(cs);
 910                 else {
 911                         /* On non-DT platforms, the SPI core sets
 912                          * spi->cs_gpio to -ENOENT and .setup()
 913                          * overrides it with the GPIO pin value
 914                          * passed using platform data.
 915                          */
 916                         spi->cs_gpio = -ENOENT;
 917                 }
 918         }
 919
 920         spi_set_ctldata(spi, NULL);
 921 }
 922
 923 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 924 {
 925         struct s3c64xx_spi_driver_data *sdd = data;
 926         struct spi_master *spi = sdd->master;
 927         unsigned int val, clr = 0;
 928
 929         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
 930
 931         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
 932                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
 933                 dev_err(&spi->dev, "RX overrun\n");
 934         }
 935         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
 936                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
 937                 dev_err(&spi->dev, "RX underrun\n");
 938         }
 939         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
 940                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
 941                 dev_err(&spi->dev, "TX overrun\n");
 942         }
 943         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
 944                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 945                 dev_err(&spi->dev, "TX underrun\n");
 946         }
 947
 948         /* Clear the pending irq by setting and then clearing it */
 949         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 950         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 951
 952         return IRQ_HANDLED;
 953 }
 954
 955 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
 956 {
 957         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 958         void __iomem *regs = sdd->regs;
 959         unsigned int val;
 960
 961         sdd->cur_speed = 0;
 962
 963         if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 964                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 965
 966         /* Disable Interrupts - we use Polling if not DMA mode */
 967         writel(0, regs + S3C64XX_SPI_INT_EN);
 968
 969         if (!sdd->port_conf->clk_from_cmu)
 970                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
 971                                 regs + S3C64XX_SPI_CLK_CFG);
 972         writel(0, regs + S3C64XX_SPI_MODE_CFG);
 973         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 974
 975         /* Clear any irq pending bits, should set and clear the bits */
 976         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
 977                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
 978                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
 979                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 980         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
 981         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
 982
 983         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
 984
 985         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 986         val &= ~S3C64XX_SPI_MODE_4BURST;
 987         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 988         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 989         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 990
 991         flush_fifo(sdd);
 992 }
 993
 994 #ifdef CONFIG_OF
 995 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
 996 {
 997         struct s3c64xx_spi_info *sci;
 998         u32 temp;
 999
1000         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1001         if (!sci)
1002                 return ERR_PTR(-ENOMEM);
1003
1004         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1005                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1006                 sci->src_clk_nr = 0;
1007         } else {
1008                 sci->src_clk_nr = temp;
1009         }
1010
1011         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1012                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1013                 sci->num_cs = 1;
1014         } else {
1015                 sci->num_cs = temp;
1016         }
1017
1018         return sci;
1019 }
1020 #else
1021 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1022 {
1023         return dev_get_platdata(dev);
1024 }
1025 #endif
1026
1027 static const struct of_device_id s3c64xx_spi_dt_match[];
1028
1029 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1030                                                 struct platform_device *pdev)
1031 {
1032 #ifdef CONFIG_OF
1033         if (pdev->dev.of_node) {
1034                 const struct of_device_id *match;
1035                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1036                 return (struct s3c64xx_spi_port_config *)match->data;
1037         }
1038 #endif
1039         return (struct s3c64xx_spi_port_config *)
1040                          platform_get_device_id(pdev)->driver_data;
1041 }
1042
1043 static int s3c64xx_spi_probe(struct platform_device *pdev)
1044 {
1045         struct resource *mem_res;
1046         struct s3c64xx_spi_driver_data *sdd;
1047         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1048         struct spi_master *master;
1049         int ret, irq;
1050         char clk_name[16];
1051
1052         if (!sci && pdev->dev.of_node) {
1053                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1054                 if (IS_ERR(sci))
1055                         return PTR_ERR(sci);
1056         }
1057
1058         if (!sci) {
1059                 dev_err(&pdev->dev, "platform_data missing!\n");
1060                 return -ENODEV;
1061         }
1062
1063         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1064         if (mem_res == NULL) {
1065                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1066                 return -ENXIO;
1067         }
1068
1069         irq = platform_get_irq(pdev, 0);
1070         if (irq < 0) {
1071                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1072                 return irq;
1073         }
1074
1075         master = spi_alloc_master(&pdev->dev,
1076                                 sizeof(struct s3c64xx_spi_driver_data));
1077         if (master == NULL) {
1078                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1079                 return -ENOMEM;
1080         }
1081
1082         platform_set_drvdata(pdev, master);
1083
1084         sdd = spi_master_get_devdata(master);
1085         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1086         sdd->master = master;
1087         sdd->cntrlr_info = sci;
1088         sdd->pdev = pdev;
1089         sdd->sfr_start = mem_res->start;
1090         if (pdev->dev.of_node) {
1091                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1092                 if (ret < 0) {
1093                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1094                                 ret);
1095                         goto err0;
1096                 }
1097                 sdd->port_id = ret;
1098         } else {
1099                 sdd->port_id = pdev->id;
1100         }
1101
1102         sdd->cur_bpw = 8;
1103
1104         if (!sdd->pdev->dev.of_node && (!sci->dma_tx || !sci->dma_rx)) {
1105                 dev_warn(&pdev->dev, "Unable to get SPI tx/rx DMA data. Switching to poll mode\n");
1106                 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1107         }
1108
1109         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1110         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1111
1112         master->dev.of_node = pdev->dev.of_node;
1113         master->bus_num = sdd->port_id;
1114         master->setup = s3c64xx_spi_setup;
1115         master->cleanup = s3c64xx_spi_cleanup;
1116         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1117         master->prepare_message = s3c64xx_spi_prepare_message;
1118         master->transfer_one = s3c64xx_spi_transfer_one;
1119         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1120         master->num_chipselect = sci->num_cs;
1121         master->dma_alignment = 8;
1122         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1123                                         SPI_BPW_MASK(8);
1124         /* the spi->mode bits understood by this driver: */
1125         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1126         master->auto_runtime_pm = true;
1127         if (!is_polling(sdd))
1128                 master->can_dma = s3c64xx_spi_can_dma;
1129
1130         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1131         if (IS_ERR(sdd->regs)) {
1132                 ret = PTR_ERR(sdd->regs);
1133                 goto err0;
1134         }
1135
1136         if (sci->cfg_gpio && sci->cfg_gpio()) {
1137                 dev_err(&pdev->dev, "Unable to config gpio\n");
1138                 ret = -EBUSY;
1139                 goto err0;
1140         }
1141
1142         /* Setup clocks */
1143         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1144         if (IS_ERR(sdd->clk)) {
1145                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1146                 ret = PTR_ERR(sdd->clk);
1147                 goto err0;
1148         }
1149
1150         if (clk_prepare_enable(sdd->clk)) {
1151                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1152                 ret = -EBUSY;
1153                 goto err0;
1154         }
1155
1156         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1157         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1158         if (IS_ERR(sdd->src_clk)) {
1159                 dev_err(&pdev->dev,
1160                         "Unable to acquire clock '%s'\n", clk_name);
1161                 ret = PTR_ERR(sdd->src_clk);
1162                 goto err2;
1163         }
1164
1165         if (clk_prepare_enable(sdd->src_clk)) {
1166                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1167                 ret = -EBUSY;
1168                 goto err2;
1169         }
1170
1171         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1172         pm_runtime_use_autosuspend(&pdev->dev);
1173         pm_runtime_set_active(&pdev->dev);
1174         pm_runtime_enable(&pdev->dev);
1175         pm_runtime_get_sync(&pdev->dev);
1176
1177         /* Setup Deufult Mode */
1178         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1179
1180         spin_lock_init(&sdd->lock);
1181         init_completion(&sdd->xfer_completion);
1182
1183         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1184                                 "spi-s3c64xx", sdd);
1185         if (ret != 0) {
1186                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1187                         irq, ret);
1188                 goto err3;
1189         }
1190
1191         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1192                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1193                sdd->regs + S3C64XX_SPI_INT_EN);
1194
1195         ret = devm_spi_register_master(&pdev->dev, master);
1196         if (ret != 0) {
1197                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1198                 goto err3;
1199         }
1200
1201         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1202                                         sdd->port_id, master->num_chipselect);
1203         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%p, Tx-%p]\n",
1204                                         mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1,
1205                                         sci->dma_rx, sci->dma_tx);
1206
1207         pm_runtime_mark_last_busy(&pdev->dev);
1208         pm_runtime_put_autosuspend(&pdev->dev);
1209
1210         return 0;
1211
1212 err3:
1213         pm_runtime_put_noidle(&pdev->dev);
1214         pm_runtime_disable(&pdev->dev);
1215         pm_runtime_set_suspended(&pdev->dev);
1216
1217         clk_disable_unprepare(sdd->src_clk);
1218 err2:
1219         clk_disable_unprepare(sdd->clk);
1220 err0:
1221         spi_master_put(master);
1222
1223         return ret;
1224 }
1225
1226 static int s3c64xx_spi_remove(struct platform_device *pdev)
1227 {
1228         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1229         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1230
1231         pm_runtime_get_sync(&pdev->dev);
1232
1233         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1234
1235         clk_disable_unprepare(sdd->src_clk);
1236
1237         clk_disable_unprepare(sdd->clk);
1238
1239         pm_runtime_put_noidle(&pdev->dev);
1240         pm_runtime_disable(&pdev->dev);
1241         pm_runtime_set_suspended(&pdev->dev);
1242
1243         return 0;
1244 }
1245
1246 #ifdef CONFIG_PM_SLEEP
1247 static int s3c64xx_spi_suspend(struct device *dev)
1248 {
1249         struct spi_master *master = dev_get_drvdata(dev);
1250         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1251
1252         int ret = spi_master_suspend(master);
1253         if (ret)
1254                 return ret;
1255
1256         ret = pm_runtime_force_suspend(dev);
1257         if (ret < 0)
1258                 return ret;
1259
1260         sdd->cur_speed = 0; /* Output Clock is stopped */
1261
1262         return 0;
1263 }
1264
1265 static int s3c64xx_spi_resume(struct device *dev)
1266 {
1267         struct spi_master *master = dev_get_drvdata(dev);
1268         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1269         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1270         int ret;
1271
1272         if (sci->cfg_gpio)
1273                 sci->cfg_gpio();
1274
1275         ret = pm_runtime_force_resume(dev);
1276         if (ret < 0)
1277                 return ret;
1278
1279         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1280
1281         return spi_master_resume(master);
1282 }
1283 #endif /* CONFIG_PM_SLEEP */
1284
1285 #ifdef CONFIG_PM
1286 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1287 {
1288         struct spi_master *master = dev_get_drvdata(dev);
1289         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1290
1291         clk_disable_unprepare(sdd->clk);
1292         clk_disable_unprepare(sdd->src_clk);
1293
1294         return 0;
1295 }
1296
1297 static int s3c64xx_spi_runtime_resume(struct device *dev)
1298 {
1299         struct spi_master *master = dev_get_drvdata(dev);
1300         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1301         int ret;
1302
1303         ret = clk_prepare_enable(sdd->src_clk);
1304         if (ret != 0)
1305                 return ret;
1306
1307         ret = clk_prepare_enable(sdd->clk);
1308         if (ret != 0) {
1309                 clk_disable_unprepare(sdd->src_clk);
1310                 return ret;
1311         }
1312
1313         return 0;
1314 }
1315 #endif /* CONFIG_PM */
1316
1317 static const struct dev_pm_ops s3c64xx_spi_pm = {
1318         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1319         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1320                            s3c64xx_spi_runtime_resume, NULL)
1321 };
1322
1323 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1324         .fifo_lvl_mask  = { 0x7f },
1325         .rx_lvl_offset  = 13,
1326         .tx_st_done     = 21,
1327         .high_speed     = true,
1328 };
1329
1330 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1331         .fifo_lvl_mask  = { 0x7f, 0x7F },
1332         .rx_lvl_offset  = 13,
1333         .tx_st_done     = 21,
1334 };
1335
1336 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1337         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1338         .rx_lvl_offset  = 15,
1339         .tx_st_done     = 25,
1340         .high_speed     = true,
1341 };
1342
1343 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1344         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1345         .rx_lvl_offset  = 15,
1346         .tx_st_done     = 25,
1347         .high_speed     = true,
1348         .clk_from_cmu   = true,
1349 };
1350
1351 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1352         .fifo_lvl_mask  = { 0x1ff },
1353         .rx_lvl_offset  = 15,
1354         .tx_st_done     = 25,
1355         .high_speed     = true,
1356         .clk_from_cmu   = true,
1357         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1358 };
1359
1360 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1361         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1362         .rx_lvl_offset  = 15,
1363         .tx_st_done     = 25,
1364         .high_speed     = true,
1365         .clk_from_cmu   = true,
1366         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1367 };
1368
1369 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1370         {
1371                 .name           = "s3c2443-spi",
1372                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1373         }, {
1374                 .name           = "s3c6410-spi",
1375                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1376         },
1377         { },
1378 };
1379
1380 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1381         { .compatible = "samsung,s3c2443-spi",
1382                         .data = (void *)&s3c2443_spi_port_config,
1383         },
1384         { .compatible = "samsung,s3c6410-spi",
1385                         .data = (void *)&s3c6410_spi_port_config,
1386         },
1387         { .compatible = "samsung,s5pv210-spi",
1388                         .data = (void *)&s5pv210_spi_port_config,
1389         },
1390         { .compatible = "samsung,exynos4210-spi",
1391                         .data = (void *)&exynos4_spi_port_config,
1392         },
1393         { .compatible = "samsung,exynos5440-spi",
1394                         .data = (void *)&exynos5440_spi_port_config,
1395         },
1396         { .compatible = "samsung,exynos7-spi",
1397                         .data = (void *)&exynos7_spi_port_config,
1398         },
1399         { },
1400 };
1401 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1402
1403 static struct platform_driver s3c64xx_spi_driver = {
1404         .driver = {
1405                 .name   = "s3c64xx-spi",
1406                 .pm = &s3c64xx_spi_pm,
1407                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1408         },
1409         .probe = s3c64xx_spi_probe,
1410         .remove = s3c64xx_spi_remove,
1411         .id_table = s3c64xx_spi_driver_ids,
1412 };
1413 MODULE_ALIAS("platform:s3c64xx-spi");
1414
1415 module_platform_driver(s3c64xx_spi_driver);
1416
1417 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1418 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1419 MODULE_LICENSE("GPL");