2 * Marvell Orion SPI controller driver
4 * Author: Shadi Ammouri <shadi@marvell.com>
5 * Copyright (C) 2007-2008 Marvell Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
17 #include <linux/spi/spi.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
21 #include <linux/clk.h>
22 #include <linux/sizes.h>
23 #include <asm/unaligned.h>
25 #define DRIVER_NAME "orion_spi"
27 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
28 #define SPI_AUTOSUSPEND_TIMEOUT 200
30 #define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
31 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
33 #define ORION_SPI_IF_CTRL_REG 0x00
34 #define ORION_SPI_IF_CONFIG_REG 0x04
35 #define ORION_SPI_DATA_OUT_REG 0x08
36 #define ORION_SPI_DATA_IN_REG 0x0c
37 #define ORION_SPI_INT_CAUSE_REG 0x10
39 #define ORION_SPI_MODE_CPOL (1 << 11)
40 #define ORION_SPI_MODE_CPHA (1 << 12)
41 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
42 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
43 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
47 struct spi_master *master;
52 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
54 return orion_spi->base + reg;
58 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
60 void __iomem *reg_addr = spi_reg(orion_spi, reg);
63 val = readl(reg_addr);
65 writel(val, reg_addr);
69 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
71 void __iomem *reg_addr = spi_reg(orion_spi, reg);
74 val = readl(reg_addr);
76 writel(val, reg_addr);
79 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
85 struct orion_spi *orion_spi;
87 orion_spi = spi_master_get_devdata(spi->master);
89 tclk_hz = clk_get_rate(orion_spi->clk);
92 * the supported rates are: 4,6,8...30
93 * round up as we look for equal or less speed
95 rate = DIV_ROUND_UP(tclk_hz, speed);
96 rate = roundup(rate, 2);
98 /* check if requested speed is too small */
105 /* Convert the rate to SPI clock divisor value. */
106 prescale = 0x10 + rate/2;
108 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
109 reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
110 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
116 orion_spi_mode_set(struct spi_device *spi)
119 struct orion_spi *orion_spi;
121 orion_spi = spi_master_get_devdata(spi->master);
123 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
124 reg &= ~ORION_SPI_MODE_MASK;
125 if (spi->mode & SPI_CPOL)
126 reg |= ORION_SPI_MODE_CPOL;
127 if (spi->mode & SPI_CPHA)
128 reg |= ORION_SPI_MODE_CPHA;
129 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
133 * called only when no transfer is active on the bus
136 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
138 struct orion_spi *orion_spi;
139 unsigned int speed = spi->max_speed_hz;
140 unsigned int bits_per_word = spi->bits_per_word;
143 orion_spi = spi_master_get_devdata(spi->master);
145 if ((t != NULL) && t->speed_hz)
148 if ((t != NULL) && t->bits_per_word)
149 bits_per_word = t->bits_per_word;
151 orion_spi_mode_set(spi);
153 rc = orion_spi_baudrate_set(spi, speed);
157 if (bits_per_word == 16)
158 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
159 ORION_SPI_IF_8_16_BIT_MODE);
161 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
162 ORION_SPI_IF_8_16_BIT_MODE);
167 static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
170 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
172 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
175 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
179 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
180 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
190 orion_spi_write_read_8bit(struct spi_device *spi,
191 const u8 **tx_buf, u8 **rx_buf)
193 void __iomem *tx_reg, *rx_reg, *int_reg;
194 struct orion_spi *orion_spi;
196 orion_spi = spi_master_get_devdata(spi->master);
197 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
198 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
199 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
201 /* clear the interrupt cause register */
202 writel(0x0, int_reg);
204 if (tx_buf && *tx_buf)
205 writel(*(*tx_buf)++, tx_reg);
209 if (orion_spi_wait_till_ready(orion_spi) < 0) {
210 dev_err(&spi->dev, "TXS timed out\n");
214 if (rx_buf && *rx_buf)
215 *(*rx_buf)++ = readl(rx_reg);
221 orion_spi_write_read_16bit(struct spi_device *spi,
222 const u16 **tx_buf, u16 **rx_buf)
224 void __iomem *tx_reg, *rx_reg, *int_reg;
225 struct orion_spi *orion_spi;
227 orion_spi = spi_master_get_devdata(spi->master);
228 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
229 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
230 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
232 /* clear the interrupt cause register */
233 writel(0x0, int_reg);
235 if (tx_buf && *tx_buf)
236 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
240 if (orion_spi_wait_till_ready(orion_spi) < 0) {
241 dev_err(&spi->dev, "TXS timed out\n");
245 if (rx_buf && *rx_buf)
246 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
252 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
257 word_len = spi->bits_per_word;
261 const u8 *tx = xfer->tx_buf;
262 u8 *rx = xfer->rx_buf;
265 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
269 } else if (word_len == 16) {
270 const u16 *tx = xfer->tx_buf;
271 u16 *rx = xfer->rx_buf;
274 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
281 return xfer->len - count;
284 static int orion_spi_transfer_one_message(struct spi_master *master,
285 struct spi_message *m)
287 struct orion_spi *orion_spi = spi_master_get_devdata(master);
288 struct spi_device *spi = m->spi;
289 struct spi_transfer *t = NULL;
290 int par_override = 0;
295 status = orion_spi_setup_transfer(spi, NULL);
300 list_for_each_entry(t, &m->transfers, transfer_list) {
301 if (par_override || t->speed_hz || t->bits_per_word) {
303 status = orion_spi_setup_transfer(spi, t);
306 if (!t->speed_hz && !t->bits_per_word)
311 orion_spi_set_cs(orion_spi, 1);
316 m->actual_length += orion_spi_write_read(spi, t);
319 udelay(t->delay_usecs);
322 orion_spi_set_cs(orion_spi, 0);
329 orion_spi_set_cs(orion_spi, 0);
332 spi_finalize_current_message(master);
337 static int orion_spi_reset(struct orion_spi *orion_spi)
339 /* Verify that the CS is deasserted */
340 orion_spi_set_cs(orion_spi, 0);
345 static int orion_spi_probe(struct platform_device *pdev)
347 struct spi_master *master;
348 struct orion_spi *spi;
350 unsigned long tclk_hz;
353 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
354 if (master == NULL) {
355 dev_dbg(&pdev->dev, "master allocation failed\n");
360 master->bus_num = pdev->id;
361 if (pdev->dev.of_node) {
363 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
365 master->bus_num = cell_index;
368 /* we support only mode 0, and no options */
369 master->mode_bits = SPI_CPHA | SPI_CPOL;
371 master->transfer_one_message = orion_spi_transfer_one_message;
372 master->num_chipselect = ORION_NUM_CHIPSELECTS;
373 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
374 master->auto_runtime_pm = true;
376 platform_set_drvdata(pdev, master);
378 spi = spi_master_get_devdata(master);
379 spi->master = master;
381 spi->clk = devm_clk_get(&pdev->dev, NULL);
382 if (IS_ERR(spi->clk)) {
383 status = PTR_ERR(spi->clk);
387 status = clk_prepare_enable(spi->clk);
391 tclk_hz = clk_get_rate(spi->clk);
392 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
393 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);
395 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
396 spi->base = devm_ioremap_resource(&pdev->dev, r);
397 if (IS_ERR(spi->base)) {
398 status = PTR_ERR(spi->base);
402 pm_runtime_set_active(&pdev->dev);
403 pm_runtime_use_autosuspend(&pdev->dev);
404 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
405 pm_runtime_enable(&pdev->dev);
407 status = orion_spi_reset(spi);
411 pm_runtime_mark_last_busy(&pdev->dev);
412 pm_runtime_put_autosuspend(&pdev->dev);
414 master->dev.of_node = pdev->dev.of_node;
415 status = spi_register_master(master);
422 pm_runtime_disable(&pdev->dev);
424 clk_disable_unprepare(spi->clk);
426 spi_master_put(master);
431 static int orion_spi_remove(struct platform_device *pdev)
433 struct spi_master *master = platform_get_drvdata(pdev);
434 struct orion_spi *spi = spi_master_get_devdata(master);
436 pm_runtime_get_sync(&pdev->dev);
437 clk_disable_unprepare(spi->clk);
439 spi_unregister_master(master);
440 pm_runtime_disable(&pdev->dev);
445 MODULE_ALIAS("platform:" DRIVER_NAME);
447 #ifdef CONFIG_PM_RUNTIME
448 static int orion_spi_runtime_suspend(struct device *dev)
450 struct spi_master *master = dev_get_drvdata(dev);
451 struct orion_spi *spi = spi_master_get_devdata(master);
453 clk_disable_unprepare(spi->clk);
457 static int orion_spi_runtime_resume(struct device *dev)
459 struct spi_master *master = dev_get_drvdata(dev);
460 struct orion_spi *spi = spi_master_get_devdata(master);
462 return clk_prepare_enable(spi->clk);
466 static const struct dev_pm_ops orion_spi_pm_ops = {
467 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
468 orion_spi_runtime_resume,
472 static const struct of_device_id orion_spi_of_match_table[] = {
473 { .compatible = "marvell,orion-spi", },
476 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
478 static struct platform_driver orion_spi_driver = {
481 .owner = THIS_MODULE,
482 .pm = &orion_spi_pm_ops,
483 .of_match_table = of_match_ptr(orion_spi_of_match_table),
485 .probe = orion_spi_probe,
486 .remove = orion_spi_remove,
489 module_platform_driver(orion_spi_driver);
491 MODULE_DESCRIPTION("Orion SPI driver");
492 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
493 MODULE_LICENSE("GPL");