2 * OMAP7xx SPI 100k controller driver
3 * Author: Fabrice Crohas <fcrohas@gmail.com>
4 * from original omap1_mcspi driver
6 * Copyright (C) 2005, 2006 Nokia Corporation
7 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
8 * Juha Yrj�l� <juha.yrjola@nokia.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/module.h>
29 #include <linux/device.h>
30 #include <linux/delay.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
35 #include <linux/gpio.h>
36 #include <linux/slab.h>
38 #include <linux/spi/spi.h>
40 #define OMAP1_SPI100K_MAX_FREQ 48000000
42 #define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12)
44 #define SPI_SETUP1 0x00
45 #define SPI_SETUP2 0x02
47 #define SPI_STATUS 0x06
48 #define SPI_TX_LSB 0x08
49 #define SPI_TX_MSB 0x0a
50 #define SPI_RX_LSB 0x0c
51 #define SPI_RX_MSB 0x0e
53 #define SPI_SETUP1_INT_READ_ENABLE (1UL << 5)
54 #define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4)
55 #define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1)
56 #define SPI_SETUP1_CLOCK_ENABLE (1UL << 0)
58 #define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0)
59 #define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0)
60 #define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5)
61 #define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5)
62 #define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10)
63 #define SPI_SETUP2_EDGE_TRIGGER (1UL << 10)
65 #define SPI_CTRL_SEN(x) ((x) << 7)
66 #define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2)
67 #define SPI_CTRL_WR (1UL << 1)
68 #define SPI_CTRL_RD (1UL << 0)
70 #define SPI_STATUS_WE (1UL << 1)
71 #define SPI_STATUS_RD (1UL << 0)
77 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
78 * cache operations; better heuristics consider wordsize and bitrate.
80 #define DMA_MIN_BYTES 8
83 #define SPI_SHUTDOWN 1
85 struct omap1_spi100k {
86 struct spi_master *master;
90 /* Virtual base address of the controller */
93 /* State of the SPI */
97 struct omap1_spi100k_cs {
102 #define MOD_REG_BIT(val, mask, set) do { \
109 static void spi100k_enable_clock(struct spi_master *master)
112 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
115 val = readw(spi100k->base + SPI_SETUP1);
116 val |= SPI_SETUP1_CLOCK_ENABLE;
117 writew(val, spi100k->base + SPI_SETUP1);
120 static void spi100k_disable_clock(struct spi_master *master)
123 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
126 val = readw(spi100k->base + SPI_SETUP1);
127 val &= ~SPI_SETUP1_CLOCK_ENABLE;
128 writew(val, spi100k->base + SPI_SETUP1);
131 static void spi100k_write_data(struct spi_master *master, int len, int data)
133 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
135 /* write 16-bit word, shifting 8-bit data if necessary */
141 spi100k_enable_clock(master);
142 writew( data , spi100k->base + SPI_TX_MSB);
144 writew(SPI_CTRL_SEN(0) |
145 SPI_CTRL_WORD_SIZE(len) |
147 spi100k->base + SPI_CTRL);
149 /* Wait for bit ack send change */
150 while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE);
153 spi100k_disable_clock(master);
156 static int spi100k_read_data(struct spi_master *master, int len)
159 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
161 /* Always do at least 16 bits */
165 spi100k_enable_clock(master);
166 writew(SPI_CTRL_SEN(0) |
167 SPI_CTRL_WORD_SIZE(len) |
169 spi100k->base + SPI_CTRL);
171 while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD);
174 dataL = readw(spi100k->base + SPI_RX_LSB);
175 dataH = readw(spi100k->base + SPI_RX_MSB);
176 spi100k_disable_clock(master);
181 static void spi100k_open(struct spi_master *master)
183 /* get control of SPI */
184 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
186 writew(SPI_SETUP1_INT_READ_ENABLE |
187 SPI_SETUP1_INT_WRITE_ENABLE |
188 SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
190 /* configure clock and interrupts */
191 writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
192 SPI_SETUP2_NEGATIVE_LEVEL |
193 SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
196 static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
199 writew(0x05fc, spi100k->base + SPI_CTRL);
201 writew(0x05fd, spi100k->base + SPI_CTRL);
205 omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
207 struct omap1_spi100k *spi100k;
208 struct omap1_spi100k_cs *cs = spi->controller_state;
209 unsigned int count, c;
212 spi100k = spi_master_get_devdata(spi->master);
215 word_len = cs->word_len;
225 if (xfer->tx_buf != NULL)
226 spi100k_write_data(spi->master, word_len, *tx++);
227 if (xfer->rx_buf != NULL)
228 *rx++ = spi100k_read_data(spi->master, word_len);
230 } else if (word_len <= 16) {
238 if (xfer->tx_buf != NULL)
239 spi100k_write_data(spi->master,word_len, *tx++);
240 if (xfer->rx_buf != NULL)
241 *rx++ = spi100k_read_data(spi->master,word_len);
243 } else if (word_len <= 32) {
251 if (xfer->tx_buf != NULL)
252 spi100k_write_data(spi->master,word_len, *tx);
253 if (xfer->rx_buf != NULL)
254 *rx = spi100k_read_data(spi->master,word_len);
260 /* called only when no transfer is active to this device */
261 static int omap1_spi100k_setup_transfer(struct spi_device *spi,
262 struct spi_transfer *t)
264 struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
265 struct omap1_spi100k_cs *cs = spi->controller_state;
266 u8 word_len = spi->bits_per_word;
268 if (t != NULL && t->bits_per_word)
269 word_len = t->bits_per_word;
273 if (spi->bits_per_word > 32)
275 cs->word_len = word_len;
277 /* SPI init before transfer */
278 writew(0x3e , spi100k->base + SPI_SETUP1);
279 writew(0x00 , spi100k->base + SPI_STATUS);
280 writew(0x3e , spi100k->base + SPI_CTRL);
285 /* the spi->mode bits understood by this driver: */
286 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
288 static int omap1_spi100k_setup(struct spi_device *spi)
291 struct omap1_spi100k *spi100k;
292 struct omap1_spi100k_cs *cs = spi->controller_state;
294 spi100k = spi_master_get_devdata(spi->master);
297 cs = kzalloc(sizeof *cs, GFP_KERNEL);
300 cs->base = spi100k->base + spi->chip_select * 0x14;
301 spi->controller_state = cs;
304 spi100k_open(spi->master);
306 clk_prepare_enable(spi100k->ick);
307 clk_prepare_enable(spi100k->fck);
309 ret = omap1_spi100k_setup_transfer(spi, NULL);
311 clk_disable_unprepare(spi100k->ick);
312 clk_disable_unprepare(spi100k->fck);
317 static int omap1_spi100k_prepare_hardware(struct spi_master *master)
319 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
321 clk_prepare_enable(spi100k->ick);
322 clk_prepare_enable(spi100k->fck);
327 static int omap1_spi100k_transfer_one_message(struct spi_master *master,
328 struct spi_message *m)
330 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
331 struct spi_device *spi = m->spi;
332 struct spi_transfer *t = NULL;
334 int par_override = 0;
337 list_for_each_entry(t, &m->transfers, transfer_list) {
338 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
342 if (par_override || t->speed_hz || t->bits_per_word) {
344 status = omap1_spi100k_setup_transfer(spi, t);
347 if (!t->speed_hz && !t->bits_per_word)
352 omap1_spi100k_force_cs(spi100k, 1);
359 count = omap1_spi100k_txrx_pio(spi, t);
360 m->actual_length += count;
362 if (count != t->len) {
369 udelay(t->delay_usecs);
371 /* ignore the "leave it on after last xfer" hint */
374 omap1_spi100k_force_cs(spi100k, 0);
379 /* Restore defaults if they were overriden */
382 status = omap1_spi100k_setup_transfer(spi, NULL);
386 omap1_spi100k_force_cs(spi100k, 0);
390 spi_finalize_current_message(master);
395 static int omap1_spi100k_unprepare_hardware(struct spi_master *master)
397 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
399 clk_disable_unprepare(spi100k->ick);
400 clk_disable_unprepare(spi100k->fck);
405 static int omap1_spi100k_probe(struct platform_device *pdev)
407 struct spi_master *master;
408 struct omap1_spi100k *spi100k;
414 master = spi_alloc_master(&pdev->dev, sizeof *spi100k);
415 if (master == NULL) {
416 dev_dbg(&pdev->dev, "master allocation failed\n");
421 master->bus_num = pdev->id;
423 master->setup = omap1_spi100k_setup;
424 master->transfer_one_message = omap1_spi100k_transfer_one_message;
425 master->prepare_transfer_hardware = omap1_spi100k_prepare_hardware;
426 master->unprepare_transfer_hardware = omap1_spi100k_unprepare_hardware;
427 master->cleanup = NULL;
428 master->num_chipselect = 2;
429 master->mode_bits = MODEBITS;
430 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
431 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
432 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
434 platform_set_drvdata(pdev, master);
436 spi100k = spi_master_get_devdata(master);
437 spi100k->master = master;
440 * The memory region base address is taken as the platform_data.
441 * You should allocate this with ioremap() before initializing
444 spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev);
446 spi100k->ick = devm_clk_get(&pdev->dev, "ick");
447 if (IS_ERR(spi100k->ick)) {
448 dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
449 status = PTR_ERR(spi100k->ick);
453 spi100k->fck = devm_clk_get(&pdev->dev, "fck");
454 if (IS_ERR(spi100k->fck)) {
455 dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
456 status = PTR_ERR(spi100k->fck);
460 status = spi_register_master(master);
464 spi100k->state = SPI_RUNNING;
469 spi_master_put(master);
473 static int omap1_spi100k_remove(struct platform_device *pdev)
475 struct spi_master *master;
476 struct omap1_spi100k *spi100k;
480 master = platform_get_drvdata(pdev);
481 spi100k = spi_master_get_devdata(master);
486 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
488 spi_unregister_master(master);
493 static struct platform_driver omap1_spi100k_driver = {
495 .name = "omap1_spi100k",
496 .owner = THIS_MODULE,
498 .probe = omap1_spi100k_probe,
499 .remove = omap1_spi100k_remove,
502 module_platform_driver(omap1_spi100k_driver);
504 MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
505 MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
506 MODULE_LICENSE("GPL");