2 * MPC512x PSC in SPI mode driver.
4 * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
5 * Original port from 52xx driver:
6 * Hongjun Chen <hong-jun.chen@freescale.com>
8 * Fork of mpc52xx_psc_spi.c:
9 * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/of_address.h>
23 #include <linux/of_platform.h>
24 #include <linux/completion.h>
26 #include <linux/delay.h>
27 #include <linux/clk.h>
28 #include <linux/spi/spi.h>
29 #include <linux/fsl_devices.h>
30 #include <linux/gpio.h>
31 #include <asm/mpc52xx_psc.h>
33 struct mpc512x_psc_spi {
34 void (*cs_control)(struct spi_device *spi, bool on);
36 /* driver internal data */
37 struct mpc52xx_psc __iomem *psc;
38 struct mpc512x_psc_fifo __iomem *fifo;
43 struct completion txisrdone;
46 /* controller state */
47 struct mpc512x_psc_spi_cs {
52 /* set clock freq, clock ramp, bits per work
53 * if t is NULL then reset the values to the default values
55 static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
56 struct spi_transfer *t)
58 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
60 cs->speed_hz = (t && t->speed_hz)
61 ? t->speed_hz : spi->max_speed_hz;
62 cs->bits_per_word = (t && t->bits_per_word)
63 ? t->bits_per_word : spi->bits_per_word;
64 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
68 static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
70 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
71 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
72 struct mpc52xx_psc __iomem *psc = mps->psc;
77 sicr = in_be32(&psc->sicr);
79 /* Set clock phase and polarity */
80 if (spi->mode & SPI_CPHA)
85 if (spi->mode & SPI_CPOL)
90 if (spi->mode & SPI_LSB_FIRST)
94 out_be32(&psc->sicr, sicr);
96 ccr = in_be32(&psc->ccr);
99 bclkdiv = (mps->mclk / cs->speed_hz) - 1;
101 bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
103 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
104 out_be32(&psc->ccr, ccr);
105 mps->bits_per_word = cs->bits_per_word;
107 if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
108 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
111 static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
113 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
115 if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
116 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
120 /* extract and scale size field in txsz or rxsz */
121 #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
125 static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
126 struct spi_transfer *t)
128 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
129 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
130 size_t tx_len = t->len;
131 size_t rx_len = t->len;
132 u8 *tx_buf = (u8 *)t->tx_buf;
133 u8 *rx_buf = (u8 *)t->rx_buf;
135 if (!tx_buf && !rx_buf && t->len)
138 while (rx_len || tx_len) {
146 * send the TX bytes in as large a chunk as possible
147 * but neither exceed the TX nor the RX FIFOs
149 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
150 txcount = min(fifosz, tx_len);
151 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
152 fifosz -= in_be32(&fifo->rxcnt) + 1;
153 txcount = min(fifosz, txcount);
156 /* fill the TX FIFO */
157 while (txcount-- > 0) {
158 data = tx_buf ? *tx_buf++ : 0;
159 if (tx_len == EOFBYTE && t->cs_change)
160 setbits32(&fifo->txcmd,
161 MPC512x_PSC_FIFO_EOF);
162 out_8(&fifo->txdata_8, data);
166 /* have the ISR trigger when the TX FIFO is empty */
167 INIT_COMPLETION(mps->txisrdone);
168 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
169 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
170 wait_for_completion(&mps->txisrdone);
174 * consume as much RX data as the FIFO holds, while we
175 * iterate over the transfer's TX data length
177 * only insist in draining all the remaining RX bytes
178 * when the TX bytes were exhausted (that's at the very
179 * end of this transfer, not when still iterating over
180 * the transfer's chunks)
186 * grab whatever was in the FIFO when we started
187 * looking, don't bother fetching what was added to
188 * the FIFO while we read from it -- we'll return
189 * here eventually and prefer sending out remaining
192 fifosz = in_be32(&fifo->rxcnt);
193 rxcount = min(fifosz, rx_len);
194 while (rxcount-- > 0) {
195 data = in_8(&fifo->rxdata_8);
202 * come back later if there still is TX data to send,
203 * bail out of the RX drain loop if all of the TX data
204 * was sent and all of the RX data was received (i.e.
205 * when the transmission has completed)
213 * TX data transmission has completed while RX data
214 * is still pending -- that's a transient situation
215 * which depends on wire speed and specific
216 * hardware implementation details (buffering) yet
217 * should resolve very quickly
219 * just yield for a moment to not hog the CPU for
220 * too long when running SPI at low speed
222 * the timeout range is rather arbitrary and tries
223 * to balance throughput against system load; the
224 * chosen values result in a minimal timeout of 50
225 * times 10us and thus work at speeds as low as
226 * some 20kbps, while the maximum timeout at the
227 * transfer's end could be 5ms _if_ nothing else
228 * ticks in the system _and_ RX data still wasn't
229 * received, which only occurs in situations that
230 * are exceptional; removing the unpredictability
231 * of the timeout either decreases throughput
232 * (longer timeouts), or puts more load on the
233 * system (fixed short timeouts) or requires the
234 * use of a timeout API instead of a counter and an
235 * unknown inner delay
237 usleep_range(10, 100);
239 } while (--rxtries > 0);
240 if (!tx_len && rx_len && !rxtries) {
242 * not enough RX bytes even after several retries
243 * and the resulting rather long timeout?
245 rxcount = in_be32(&fifo->rxcnt);
247 "short xfer, missing %zd RX bytes, FIFO level %zd\n",
252 * drain and drop RX data which "should not be there" in
253 * the first place, for undisturbed transmission this turns
254 * into a NOP (except for the FIFO level fetch)
256 if (!tx_len && !rx_len) {
257 while (in_be32(&fifo->rxcnt))
258 in_8(&fifo->rxdata_8);
265 static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
266 struct spi_message *m)
268 struct spi_device *spi;
271 struct spi_transfer *t;
276 list_for_each_entry(t, &m->transfers, transfer_list) {
277 if (t->bits_per_word || t->speed_hz) {
278 status = mpc512x_psc_spi_transfer_setup(spi, t);
284 mpc512x_psc_spi_activate_cs(spi);
285 cs_change = t->cs_change;
287 status = mpc512x_psc_spi_transfer_rxtx(spi, t);
290 m->actual_length += t->len;
293 udelay(t->delay_usecs);
296 mpc512x_psc_spi_deactivate_cs(spi);
300 m->complete(m->context);
302 if (status || !cs_change)
303 mpc512x_psc_spi_deactivate_cs(spi);
305 mpc512x_psc_spi_transfer_setup(spi, NULL);
307 spi_finalize_current_message(master);
311 static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
313 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
314 struct mpc52xx_psc __iomem *psc = mps->psc;
316 dev_dbg(&master->dev, "%s()\n", __func__);
320 out_8(&psc->mode, 0x0);
322 /* enable transmitter/receiver */
323 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
328 static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
330 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
331 struct mpc52xx_psc __iomem *psc = mps->psc;
332 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
334 dev_dbg(&master->dev, "%s()\n", __func__);
336 /* disable transmitter/receiver and fifo interrupt */
337 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
338 out_be32(&fifo->tximr, 0);
343 static int mpc512x_psc_spi_setup(struct spi_device *spi)
345 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
348 if (spi->bits_per_word % 8)
352 cs = kzalloc(sizeof *cs, GFP_KERNEL);
356 if (gpio_is_valid(spi->cs_gpio)) {
357 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
359 dev_err(&spi->dev, "can't get CS gpio: %d\n",
364 gpio_direction_output(spi->cs_gpio,
365 spi->mode & SPI_CS_HIGH ? 0 : 1);
368 spi->controller_state = cs;
371 cs->bits_per_word = spi->bits_per_word;
372 cs->speed_hz = spi->max_speed_hz;
377 static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
379 if (gpio_is_valid(spi->cs_gpio))
380 gpio_free(spi->cs_gpio);
381 kfree(spi->controller_state);
384 static int mpc512x_psc_spi_port_config(struct spi_master *master,
385 struct mpc512x_psc_spi *mps)
387 struct mpc52xx_psc __iomem *psc = mps->psc;
388 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
396 sprintf(name, "psc%d_mclk", master->bus_num);
397 spiclk = clk_get(&master->dev, name);
399 mps->mclk = clk_get_rate(spiclk);
402 /* Reset the PSC into a known state */
403 out_8(&psc->command, MPC52xx_PSC_RST_RX);
404 out_8(&psc->command, MPC52xx_PSC_RST_TX);
405 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
407 /* Disable psc interrupts all useful interrupts are in fifo */
408 out_be16(&psc->isr_imr.imr, 0);
410 /* Disable fifo interrupts, will be enabled later */
411 out_be32(&fifo->tximr, 0);
412 out_be32(&fifo->rximr, 0);
414 /* Setup fifo slice address and size */
415 /*out_be32(&fifo->txsz, 0x0fe00004);*/
416 /*out_be32(&fifo->rxsz, 0x0ff00004);*/
418 sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
419 0x00800000 | /* GenClk = 1 -- internal clk */
420 0x00008000 | /* SPI = 1 */
421 0x00004000 | /* MSTR = 1 -- SPI master */
422 0x00000800; /* UseEOF = 1 -- SS low until EOF */
424 out_be32(&psc->sicr, sicr);
426 ccr = in_be32(&psc->ccr);
428 bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
429 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
430 out_be32(&psc->ccr, ccr);
432 /* Set 2ms DTL delay */
433 out_8(&psc->ctur, 0x00);
434 out_8(&psc->ctlr, 0x82);
436 /* we don't use the alarms */
437 out_be32(&fifo->rxalarm, 0xfff);
438 out_be32(&fifo->txalarm, 0);
440 /* Enable FIFO slices for Rx/Tx */
441 out_be32(&fifo->rxcmd,
442 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
443 out_be32(&fifo->txcmd,
444 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
446 mps->bits_per_word = 8;
451 static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
453 struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
454 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
456 /* clear interrupt and wake up the rx/tx routine */
457 if (in_be32(&fifo->txisr) &
458 in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
459 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
460 out_be32(&fifo->tximr, 0);
461 complete(&mps->txisrdone);
467 static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
469 gpio_set_value(spi->cs_gpio, onoff);
472 /* bus_num is used only for the case dev->platform_data == NULL */
473 static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
474 u32 size, unsigned int irq,
477 struct fsl_spi_platform_data *pdata = dev->platform_data;
478 struct mpc512x_psc_spi *mps;
479 struct spi_master *master;
483 master = spi_alloc_master(dev, sizeof *mps);
487 dev_set_drvdata(dev, master);
488 mps = spi_master_get_devdata(master);
492 mps->cs_control = mpc512x_spi_cs_control;
493 master->bus_num = bus_num;
495 mps->cs_control = pdata->cs_control;
496 master->bus_num = pdata->bus_num;
497 master->num_chipselect = pdata->max_chipselect;
500 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
501 master->setup = mpc512x_psc_spi_setup;
502 master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
503 master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
504 master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
505 master->cleanup = mpc512x_psc_spi_cleanup;
506 master->dev.of_node = dev->of_node;
508 tempp = ioremap(regaddr, size);
510 dev_err(dev, "could not ioremap I/O port range\n");
516 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
518 ret = request_irq(mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
519 "mpc512x-psc-spi", mps);
522 init_completion(&mps->txisrdone);
524 ret = mpc512x_psc_spi_port_config(master, mps);
528 ret = spi_register_master(master);
535 free_irq(mps->irq, mps);
539 spi_master_put(master);
544 static int mpc512x_psc_spi_do_remove(struct device *dev)
546 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
547 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
549 spi_unregister_master(master);
550 free_irq(mps->irq, mps);
553 spi_master_put(master);
558 static int mpc512x_psc_spi_of_probe(struct platform_device *op)
560 const u32 *regaddr_p;
561 u64 regaddr64, size64;
564 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
566 dev_err(&op->dev, "Invalid PSC address\n");
569 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
571 /* get PSC id (0..11, used by port_config) */
572 id = of_alias_get_id(op->dev.of_node, "spi");
574 dev_err(&op->dev, "no alias id for %s\n",
575 op->dev.of_node->full_name);
579 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
580 irq_of_parse_and_map(op->dev.of_node, 0), id);
583 static int mpc512x_psc_spi_of_remove(struct platform_device *op)
585 return mpc512x_psc_spi_do_remove(&op->dev);
588 static struct of_device_id mpc512x_psc_spi_of_match[] = {
589 { .compatible = "fsl,mpc5121-psc-spi", },
593 MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
595 static struct platform_driver mpc512x_psc_spi_of_driver = {
596 .probe = mpc512x_psc_spi_of_probe,
597 .remove = mpc512x_psc_spi_of_remove,
599 .name = "mpc512x-psc-spi",
600 .owner = THIS_MODULE,
601 .of_match_table = mpc512x_psc_spi_of_match,
604 module_platform_driver(mpc512x_psc_spi_of_driver);
606 MODULE_AUTHOR("John Rigby");
607 MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
608 MODULE_LICENSE("GPL");