1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/sched.h>
15 #include <linux/completion.h>
16 #include <linux/spinlock.h>
17 #include <linux/err.h>
18 #include <linux/gpio.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/spi/spi.h>
23 #include <lantiq_soc.h>
26 #define LTQ_SPI_RX_IRQ_NAME "spi_rx"
27 #define LTQ_SPI_TX_IRQ_NAME "spi_tx"
28 #define LTQ_SPI_ERR_IRQ_NAME "spi_err"
29 #define LTQ_SPI_FRM_IRQ_NAME "spi_frm"
31 #define LTQ_SPI_CLC 0x00
32 #define LTQ_SPI_PISEL 0x04
33 #define LTQ_SPI_ID 0x08
34 #define LTQ_SPI_CON 0x10
35 #define LTQ_SPI_STAT 0x14
36 #define LTQ_SPI_WHBSTATE 0x18
37 #define LTQ_SPI_TB 0x20
38 #define LTQ_SPI_RB 0x24
39 #define LTQ_SPI_RXFCON 0x30
40 #define LTQ_SPI_TXFCON 0x34
41 #define LTQ_SPI_FSTAT 0x38
42 #define LTQ_SPI_BRT 0x40
43 #define LTQ_SPI_BRSTAT 0x44
44 #define LTQ_SPI_SFCON 0x60
45 #define LTQ_SPI_SFSTAT 0x64
46 #define LTQ_SPI_GPOCON 0x70
47 #define LTQ_SPI_GPOSTAT 0x74
48 #define LTQ_SPI_FPGO 0x78
49 #define LTQ_SPI_RXREQ 0x80
50 #define LTQ_SPI_RXCNT 0x84
51 #define LTQ_SPI_DMACON 0xec
52 #define LTQ_SPI_IRNEN 0xf4
53 #define LTQ_SPI_IRNICR 0xf8
54 #define LTQ_SPI_IRNCR 0xfc
56 #define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
57 #define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S)
58 #define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
59 #define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S)
60 #define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
61 #define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
63 #define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */
64 #define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S)
65 #define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */
66 #define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S)
67 #define LTQ_SPI_ID_MOD_S 8 /* Module ID */
68 #define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S)
69 #define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */
70 #define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S)
71 #define LTQ_SPI_ID_REV_M 0x1F /* Hardware revision number */
73 #define LTQ_SPI_CON_BM_S 16 /* Data width selection */
74 #define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S)
75 #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
76 #define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
77 #define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
78 #define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
79 #define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
80 #define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
81 #define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
82 #define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
83 #define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
84 #define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
85 #define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
86 #define LTQ_SPI_CON_HB BIT(4) /* Heading control */
87 #define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
88 #define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
90 #define LTQ_SPI_STAT_RXBV_S 28
91 #define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S)
92 #define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
93 #define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
94 #define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
95 #define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
96 #define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
97 #define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
98 #define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */
99 #define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
100 #define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
101 #define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \
102 LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \
103 LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE)
105 #define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
106 #define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
107 #define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
108 #define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
109 #define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
110 #define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
111 #define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
112 #define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
113 #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
114 #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
115 #define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
116 #define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
117 #define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
118 #define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
119 #define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
120 #define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
121 #define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \
122 LTQ_SPI_WHBSTATE_CLRME | \
123 LTQ_SPI_WHBSTATE_CLRTE | \
124 LTQ_SPI_WHBSTATE_CLRRE | \
125 LTQ_SPI_WHBSTATE_CLRAE | \
126 LTQ_SPI_WHBSTATE_CLRTUE)
128 #define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */
129 #define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S)
130 #define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
131 #define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
133 #define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */
134 #define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S)
135 #define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
136 #define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
138 #define LTQ_SPI_FSTAT_RXFFL_S 0
139 #define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S)
140 #define LTQ_SPI_FSTAT_TXFFL_S 8
141 #define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S)
143 #define LTQ_SPI_GPOCON_ISCSBN_S 8
144 #define LTQ_SPI_GPOCON_INVOUTN_S 0
146 #define LTQ_SPI_FGPO_SETOUTN_S 8
147 #define LTQ_SPI_FGPO_CLROUTN_S 0
149 #define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */
150 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
152 #define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */
153 #define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
154 #define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
155 #define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */
156 #define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */
157 #define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */
158 #define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */
159 #define LTQ_SPI_IRNEN_ALL 0x1F
161 struct lantiq_ssc_hwcfg {
162 unsigned int irnen_r;
163 unsigned int irnen_t;
166 struct lantiq_ssc_spi {
167 struct spi_master *master;
169 void __iomem *regbase;
172 const struct lantiq_ssc_hwcfg *hwcfg;
175 struct workqueue_struct *wq;
176 struct work_struct work;
180 unsigned int tx_todo;
181 unsigned int rx_todo;
182 unsigned int bits_per_word;
183 unsigned int speed_hz;
184 unsigned int tx_fifo_size;
185 unsigned int rx_fifo_size;
186 unsigned int base_cs;
189 static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
191 return __raw_readl(spi->regbase + reg);
194 static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
197 __raw_writel(val, spi->regbase + reg);
200 static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
203 u32 val = __raw_readl(spi->regbase + reg);
207 __raw_writel(val, spi->regbase + reg);
210 static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
212 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
214 return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S;
217 static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
219 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
221 return fstat & LTQ_SPI_FSTAT_RXFFL_M;
224 static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
226 return spi->tx_fifo_size - tx_fifo_level(spi);
229 static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
231 u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S;
233 val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
234 lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);
237 static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
239 u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S;
241 val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
242 lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);
245 static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
247 lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
250 static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
252 lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
255 static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
257 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
260 static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
262 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
265 static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
266 unsigned int max_speed_hz)
271 * SPI module clock is derived from FPI bus clock dependent on
272 * divider value in CLC.RMS which is always set to 1.
275 * baudrate = --------------
278 spi_clk = clk_get_rate(spi->fpi_clk) / 2;
280 if (max_speed_hz > spi_clk)
283 brt = spi_clk / max_speed_hz - 1;
288 dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
289 spi_clk, max_speed_hz, brt);
291 lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);
294 static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
295 unsigned int bits_per_word)
299 /* CON.BM value = bits_per_word - 1 */
300 bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S;
302 lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON);
305 static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
308 u32 con_set = 0, con_clr = 0;
311 * SPI mode mapping in CON register:
312 * Mode CPOL CPHA CON.PO CON.PH
319 con_clr |= LTQ_SPI_CON_PH;
321 con_set |= LTQ_SPI_CON_PH;
324 con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
326 con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
328 /* Set heading control */
329 if (mode & SPI_LSB_FIRST)
330 con_clr |= LTQ_SPI_CON_HB;
332 con_set |= LTQ_SPI_CON_HB;
334 /* Set loopback mode */
336 con_set |= LTQ_SPI_CON_LB;
338 con_clr |= LTQ_SPI_CON_LB;
340 lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON);
343 static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
345 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
348 * Set clock divider for run mode to 1 to
349 * run at same frequency as FPI bus
351 lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);
353 /* Put controller into config mode */
354 hw_enter_config_mode(spi);
356 /* Clear error flags */
357 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
359 /* Enable error checking, disable TX/RX */
360 lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
361 LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF |
362 LTQ_SPI_CON_RXOFF, LTQ_SPI_CON);
364 /* Setup default SPI mode */
365 hw_setup_bits_per_word(spi, spi->bits_per_word);
366 hw_setup_clock_mode(spi, SPI_MODE_0);
368 /* Enable master mode and clear error flags */
369 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |
370 LTQ_SPI_WHBSTATE_CLR_ERRORS,
373 /* Reset GPIO/CS registers */
374 lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);
375 lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);
377 /* Enable and flush FIFOs */
381 /* Enable interrupts */
382 lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |
383 LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
386 static int lantiq_ssc_setup(struct spi_device *spidev)
388 struct spi_master *master = spidev->master;
389 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
390 unsigned int cs = spidev->chip_select;
393 /* GPIOs are used for CS */
394 if (gpio_is_valid(spidev->cs_gpio))
397 dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
399 if (cs < spi->base_cs) {
401 "chipselect %i too small (min %i)\n", cs, spi->base_cs);
405 /* set GPO pin to CS mode */
406 gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S);
409 if (spidev->mode & SPI_CS_HIGH)
410 gpocon |= 1 << (cs - spi->base_cs);
412 lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON);
417 static int lantiq_ssc_prepare_message(struct spi_master *master,
418 struct spi_message *message)
420 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
422 hw_enter_config_mode(spi);
423 hw_setup_clock_mode(spi, message->spi->mode);
424 hw_enter_active_mode(spi);
429 static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
430 struct spi_device *spidev, struct spi_transfer *t)
432 unsigned int speed_hz = t->speed_hz;
433 unsigned int bits_per_word = t->bits_per_word;
436 if (bits_per_word != spi->bits_per_word ||
437 speed_hz != spi->speed_hz) {
438 hw_enter_config_mode(spi);
439 hw_setup_speed_hz(spi, speed_hz);
440 hw_setup_bits_per_word(spi, bits_per_word);
441 hw_enter_active_mode(spi);
443 spi->speed_hz = speed_hz;
444 spi->bits_per_word = bits_per_word;
447 /* Configure transmitter and receiver */
448 con = lantiq_ssc_readl(spi, LTQ_SPI_CON);
450 con &= ~LTQ_SPI_CON_TXOFF;
452 con |= LTQ_SPI_CON_TXOFF;
455 con &= ~LTQ_SPI_CON_RXOFF;
457 con |= LTQ_SPI_CON_RXOFF;
459 lantiq_ssc_writel(spi, con, LTQ_SPI_CON);
462 static int lantiq_ssc_unprepare_message(struct spi_master *master,
463 struct spi_message *message)
465 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
467 flush_workqueue(spi->wq);
469 /* Disable transmitter and receiver while idle */
470 lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF,
476 static void tx_fifo_write(struct lantiq_ssc_spi *spi)
482 unsigned int tx_free = tx_fifo_free(spi);
484 while (spi->tx_todo && tx_free) {
485 switch (spi->bits_per_word) {
493 tx16 = (u16 *) spi->tx;
499 tx32 = (u32 *) spi->tx;
510 lantiq_ssc_writel(spi, data, LTQ_SPI_TB);
515 static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
521 unsigned int rx_fill = rx_fifo_level(spi);
524 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
526 switch (spi->bits_per_word) {
534 rx16 = (u16 *) spi->rx;
540 rx32 = (u32 *) spi->rx;
554 static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
558 unsigned int rxbv, shift;
559 unsigned int rx_fill = rx_fifo_level(spi);
562 * In RX-only mode the bits per word value is ignored by HW. A value
563 * of 32 is used instead. Thus all 4 bytes per FIFO must be read.
564 * If remaining RX bytes are less than 4, the FIFO must be read
565 * differently. The amount of received and valid bytes is indicated
566 * by STAT.RXBV register value.
569 if (spi->rx_todo < 4) {
570 rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &
571 LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S;
572 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
574 shift = (rxbv - 1) * 8;
578 *rx8++ = (data >> shift) & 0xFF;
585 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
586 rx32 = (u32 *) spi->rx;
596 static void rx_request(struct lantiq_ssc_spi *spi)
598 unsigned int rxreq, rxreq_max;
601 * To avoid receive overflows at high clocks it is better to request
602 * only the amount of bytes that fits into all FIFOs. This value
603 * depends on the FIFO size implemented in hardware.
605 rxreq = spi->rx_todo;
606 rxreq_max = spi->rx_fifo_size * 4;
607 if (rxreq > rxreq_max)
610 lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);
613 static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
615 struct lantiq_ssc_spi *spi = data;
618 if (spi->rx && spi->rx_todo)
619 rx_fifo_read_full_duplex(spi);
623 else if (!tx_fifo_level(spi))
625 } else if (spi->rx) {
627 rx_fifo_read_half_duplex(spi);
641 queue_work(spi->wq, &spi->work);
646 static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
648 struct lantiq_ssc_spi *spi = data;
649 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
651 if (!(stat & LTQ_SPI_STAT_ERRORS))
654 if (stat & LTQ_SPI_STAT_RUE)
655 dev_err(spi->dev, "receive underflow error\n");
656 if (stat & LTQ_SPI_STAT_TUE)
657 dev_err(spi->dev, "transmit underflow error\n");
658 if (stat & LTQ_SPI_STAT_AE)
659 dev_err(spi->dev, "abort error\n");
660 if (stat & LTQ_SPI_STAT_RE)
661 dev_err(spi->dev, "receive overflow error\n");
662 if (stat & LTQ_SPI_STAT_TE)
663 dev_err(spi->dev, "transmit overflow error\n");
664 if (stat & LTQ_SPI_STAT_ME)
665 dev_err(spi->dev, "mode error\n");
667 /* Clear error flags */
668 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
670 /* set bad status so it can be retried */
671 if (spi->master->cur_msg)
672 spi->master->cur_msg->status = -EIO;
673 queue_work(spi->wq, &spi->work);
678 static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
679 struct spi_transfer *t)
683 spin_lock_irqsave(&spi->lock, flags);
689 spi->tx_todo = t->len;
691 /* initially fill TX FIFO */
696 spi->rx_todo = t->len;
698 /* start shift clock in RX-only mode */
703 spin_unlock_irqrestore(&spi->lock, flags);
709 * The driver only gets an interrupt when the FIFO is empty, but there
710 * is an additional shift register from which the data is written to
711 * the wire. We get the last interrupt when the controller starts to
712 * write the last word to the wire, not when it is finished. Do busy
713 * waiting till it finishes.
715 static void lantiq_ssc_bussy_work(struct work_struct *work)
717 struct lantiq_ssc_spi *spi;
718 unsigned long long timeout = 8LL * 1000LL;
721 spi = container_of(work, typeof(*spi), work);
723 do_div(timeout, spi->speed_hz);
724 timeout += timeout + 100; /* some tolerance */
726 end = jiffies + msecs_to_jiffies(timeout);
728 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
730 if (!(stat & LTQ_SPI_STAT_BSY)) {
731 spi_finalize_current_transfer(spi->master);
736 } while (!time_after_eq(jiffies, end));
738 if (spi->master->cur_msg)
739 spi->master->cur_msg->status = -EIO;
740 spi_finalize_current_transfer(spi->master);
743 static void lantiq_ssc_handle_err(struct spi_master *master,
744 struct spi_message *message)
746 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
748 /* flush FIFOs on timeout */
753 static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
755 struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
756 unsigned int cs = spidev->chip_select;
759 if (!!(spidev->mode & SPI_CS_HIGH) == enable)
760 fgpo = (1 << (cs - spi->base_cs));
762 fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S));
764 lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);
767 static int lantiq_ssc_transfer_one(struct spi_master *master,
768 struct spi_device *spidev,
769 struct spi_transfer *t)
771 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
773 hw_setup_transfer(spi, spidev, t);
775 return transfer_start(spi, spidev, t);
778 static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
779 .irnen_r = LTQ_SPI_IRNEN_R_XWAY,
780 .irnen_t = LTQ_SPI_IRNEN_T_XWAY,
783 static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
784 .irnen_r = LTQ_SPI_IRNEN_R_XRX,
785 .irnen_t = LTQ_SPI_IRNEN_T_XRX,
788 static const struct of_device_id lantiq_ssc_match[] = {
789 { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
790 { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
791 { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
794 MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
796 static int lantiq_ssc_probe(struct platform_device *pdev)
798 struct device *dev = &pdev->dev;
799 struct spi_master *master;
800 struct resource *res;
801 struct lantiq_ssc_spi *spi;
802 const struct lantiq_ssc_hwcfg *hwcfg;
803 const struct of_device_id *match;
804 int err, rx_irq, tx_irq, err_irq;
805 u32 id, supports_dma, revision;
808 match = of_match_device(lantiq_ssc_match, dev);
810 dev_err(dev, "no device match\n");
815 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
817 dev_err(dev, "failed to get resources\n");
821 rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
825 tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
829 err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
833 master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
837 spi = spi_master_get_devdata(master);
838 spi->master = master;
841 platform_set_drvdata(pdev, spi);
843 spi->regbase = devm_ioremap_resource(dev, res);
844 if (IS_ERR(spi->regbase)) {
845 err = PTR_ERR(spi->regbase);
849 err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt,
850 0, LTQ_SPI_RX_IRQ_NAME, spi);
854 err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt,
855 0, LTQ_SPI_TX_IRQ_NAME, spi);
859 err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt,
860 0, LTQ_SPI_ERR_IRQ_NAME, spi);
864 spi->spi_clk = devm_clk_get(dev, "gate");
865 if (IS_ERR(spi->spi_clk)) {
866 err = PTR_ERR(spi->spi_clk);
869 err = clk_prepare_enable(spi->spi_clk);
874 * Use the old clk_get_fpi() function on Lantiq platform, till it
875 * supports common clk.
877 #if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK)
878 spi->fpi_clk = clk_get_fpi();
880 spi->fpi_clk = clk_get(dev, "freq");
882 if (IS_ERR(spi->fpi_clk)) {
883 err = PTR_ERR(spi->fpi_clk);
884 goto err_clk_disable;
888 of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
891 of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
893 spin_lock_init(&spi->lock);
894 spi->bits_per_word = 8;
897 master->dev.of_node = pdev->dev.of_node;
898 master->num_chipselect = num_cs;
899 master->setup = lantiq_ssc_setup;
900 master->set_cs = lantiq_ssc_set_cs;
901 master->handle_err = lantiq_ssc_handle_err;
902 master->prepare_message = lantiq_ssc_prepare_message;
903 master->unprepare_message = lantiq_ssc_unprepare_message;
904 master->transfer_one = lantiq_ssc_transfer_one;
905 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
907 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
908 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
910 spi->wq = alloc_ordered_workqueue(dev_name(dev), 0);
915 INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
917 id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
918 spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S;
919 spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S;
920 supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S;
921 revision = id & LTQ_SPI_ID_REV_M;
923 lantiq_ssc_hw_init(spi);
926 "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
927 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
929 err = devm_spi_register_master(dev, master);
931 dev_err(dev, "failed to register spi_master\n");
938 destroy_workqueue(spi->wq);
940 clk_put(spi->fpi_clk);
942 clk_disable_unprepare(spi->spi_clk);
944 spi_master_put(master);
949 static int lantiq_ssc_remove(struct platform_device *pdev)
951 struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
953 lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);
954 lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);
957 hw_enter_config_mode(spi);
959 destroy_workqueue(spi->wq);
960 clk_disable_unprepare(spi->spi_clk);
961 clk_put(spi->fpi_clk);
966 static struct platform_driver lantiq_ssc_driver = {
967 .probe = lantiq_ssc_probe,
968 .remove = lantiq_ssc_remove,
970 .name = "spi-lantiq-ssc",
971 .of_match_table = lantiq_ssc_match,
974 module_platform_driver(lantiq_ssc_driver);
976 MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
977 MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>");
978 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
979 MODULE_LICENSE("GPL");
980 MODULE_ALIAS("platform:spi-lantiq-ssc");