drivers/spi/spi-imx.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2008 Juergen Beisert
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the
  16  * Free Software Foundation
  17  * 51 Franklin Street, Fifth Floor
  18  * Boston, MA  02110-1301, USA.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/completion.h>
  23 #include <linux/delay.h>
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/slab.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/spi/spi_bitbang.h>
  37 #include <linux/types.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/of_gpio.h>
  41
  42 #include <linux/platform_data/dma-imx.h>
  43 #include <linux/platform_data/spi-imx.h>
  44
  45 #define DRIVER_NAME "spi_imx"
  46
  47 #define MXC_CSPIRXDATA          0x00
  48 #define MXC_CSPITXDATA          0x04
  49 #define MXC_CSPICTRL            0x08
  50 #define MXC_CSPIINT             0x0c
  51 #define MXC_RESET               0x1c
  52
  53 /* generic defines to abstract from the different register layouts */
  54 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
  55 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
  56
  57 /* The maximum  bytes that a sdma BD can transfer.*/
  58 #define MAX_SDMA_BD_BYTES  (1 << 15)
  59 #define MX51_ECSPI_CTRL_MAX_BURST       512
  60 struct spi_imx_config {
  61         unsigned int speed_hz;
  62         unsigned int bpw;
  63         unsigned int len;
  64 };
  65
  66 enum spi_imx_devtype {
  67         IMX1_CSPI,
  68         IMX21_CSPI,
  69         IMX27_CSPI,
  70         IMX31_CSPI,
  71         IMX35_CSPI,     /* CSPI on all i.mx except above */
  72         IMX51_ECSPI,    /* ECSPI on i.mx51 and later */
  73 };
  74
  75 struct spi_imx_data;
  76
  77 struct spi_imx_devtype_data {
  78         void (*intctrl)(struct spi_imx_data *, int);
  79         int (*config)(struct spi_device *, struct spi_imx_config *);
  80         void (*trigger)(struct spi_imx_data *);
  81         int (*rx_available)(struct spi_imx_data *);
  82         void (*reset)(struct spi_imx_data *);
  83         enum spi_imx_devtype devtype;
  84 };
  85
  86 struct spi_imx_data {
  87         struct spi_bitbang bitbang;
  88         struct device *dev;
  89
  90         struct completion xfer_done;
  91         void __iomem *base;
  92         unsigned long base_phys;
  93
  94         struct clk *clk_per;
  95         struct clk *clk_ipg;
  96         unsigned long spi_clk;
  97         unsigned int spi_bus_clk;
  98
  99         unsigned int bytes_per_word;
 100         unsigned int spi_drctl;
 101
 102         unsigned int count, count_index;
 103         void (*tx)(struct spi_imx_data *);
 104         void (*rx)(struct spi_imx_data *);
 105         void *rx_buf;
 106         const void *tx_buf;
 107         unsigned int txfifo; /* number of words pushed in tx FIFO */
 108         unsigned int dynamic_burst, bpw_rx;
 109         unsigned int bpw_w;
 110
 111         /* DMA */
 112         bool usedma;
 113         u32 wml;
 114         struct completion dma_rx_completion;
 115         struct completion dma_tx_completion;
 116
 117         const struct spi_imx_devtype_data *devtype_data;
 118 };
 119
 120 static inline int is_imx27_cspi(struct spi_imx_data *d)
 121 {
 122         return d->devtype_data->devtype == IMX27_CSPI;
 123 }
 124
 125 static inline int is_imx35_cspi(struct spi_imx_data *d)
 126 {
 127         return d->devtype_data->devtype == IMX35_CSPI;
 128 }
 129
 130 static inline int is_imx51_ecspi(struct spi_imx_data *d)
 131 {
 132         return d->devtype_data->devtype == IMX51_ECSPI;
 133 }
 134
 135 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
 136 {
 137         return is_imx51_ecspi(d) ? 64 : 8;
 138 }
 139
 140 #define MXC_SPI_BUF_RX(type)                                            \
 141 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
 142 {                                                                       \
 143         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
 144                                                                         \
 145         if (spi_imx->rx_buf) {                                          \
 146                 *(type *)spi_imx->rx_buf = val;                         \
 147                 spi_imx->rx_buf += sizeof(type);                        \
 148         }                                                               \
 149 }
 150
 151 #define MXC_SPI_BUF_TX(type)                                            \
 152 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
 153 {                                                                       \
 154         type val = 0;                                                   \
 155                                                                         \
 156         if (spi_imx->tx_buf) {                                          \
 157                 val = *(type *)spi_imx->tx_buf;                         \
 158                 spi_imx->tx_buf += sizeof(type);                        \
 159         }                                                               \
 160                                                                         \
 161         spi_imx->count -= sizeof(type);                                 \
 162                                                                         \
 163         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
 164 }
 165
 166 MXC_SPI_BUF_RX(u8)
 167 MXC_SPI_BUF_TX(u8)
 168 MXC_SPI_BUF_RX(u16)
 169 MXC_SPI_BUF_TX(u16)
 170 MXC_SPI_BUF_RX(u32)
 171 MXC_SPI_BUF_TX(u32)
 172
 173 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 174  * (which is currently not the case in this driver)
 175  */
 176 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 177         256, 384, 512, 768, 1024};
 178
 179 /* MX21, MX27 */
 180 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 181                 unsigned int fspi, unsigned int max, unsigned int *fres)
 182 {
 183         int i;
 184
 185         for (i = 2; i < max; i++)
 186                 if (fspi * mxc_clkdivs[i] >= fin)
 187                         break;
 188
 189         *fres = fin / mxc_clkdivs[i];
 190         return i;
 191 }
 192
 193 /* MX1, MX31, MX35, MX51 CSPI */
 194 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 195                 unsigned int fspi, unsigned int *fres)
 196 {
 197         int i, div = 4;
 198
 199         for (i = 0; i < 7; i++) {
 200                 if (fspi * div >= fin)
 201                         goto out;
 202                 div <<= 1;
 203         }
 204
 205 out:
 206         *fres = fin / div;
 207         return i;
 208 }
 209
 210 static int spi_imx_bytes_per_word(const int bpw)
 211 {
 212         return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
 213 }
 214
 215 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
 216                          struct spi_transfer *transfer)
 217 {
 218         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
 219         unsigned int bpw, i;
 220
 221         if (!master->dma_rx)
 222                 return false;
 223
 224         if (!transfer)
 225                 return false;
 226
 227         bpw = transfer->bits_per_word;
 228         if (!bpw)
 229                 bpw = spi->bits_per_word;
 230
 231         bpw = spi_imx_bytes_per_word(bpw);
 232
 233         if (bpw != 1 && bpw != 2 && bpw != 4)
 234                 return false;
 235
 236         for (i = spi_imx_get_fifosize(spi_imx) / 2; i > 0; i--) {
 237                 if (!(transfer->len % (i * bpw)))
 238                         break;
 239         }
 240
 241         if (i == 0)
 242                 return false;
 243
 244         spi_imx->wml = i;
 245
 246         return true;
 247 }
 248
 249 #define MX51_ECSPI_CTRL         0x08
 250 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
 251 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
 252 #define MX51_ECSPI_CTRL_SMC             (1 << 3)
 253 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
 254 #define MX51_ECSPI_CTRL_DRCTL(drctl)    ((drctl) << 16)
 255 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
 256 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
 257 #define MX51_ECSPI_CTRL_CS(cs)          ((cs) << 18)
 258 #define MX51_ECSPI_CTRL_BL_OFFSET       20
 259 #define MX51_ECSPI_CTRL_BL_MASK         (0xfff << 20)
 260
 261 #define MX51_ECSPI_CONFIG       0x0c
 262 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs) +  0))
 263 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs) +  4))
 264 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs) +  8))
 265 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs) + 12))
 266 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)   (1 << ((cs) + 20))
 267
 268 #define MX51_ECSPI_INT          0x10
 269 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
 270 #define MX51_ECSPI_INT_RREN             (1 <<  3)
 271
 272 #define MX51_ECSPI_DMA      0x14
 273 #define MX51_ECSPI_DMA_TX_WML(wml)      ((wml) & 0x3f)
 274 #define MX51_ECSPI_DMA_RX_WML(wml)      (((wml) & 0x3f) << 16)
 275 #define MX51_ECSPI_DMA_RXT_WML(wml)     (((wml) & 0x3f) << 24)
 276
 277 #define MX51_ECSPI_DMA_TEDEN            (1 << 7)
 278 #define MX51_ECSPI_DMA_RXDEN            (1 << 23)
 279 #define MX51_ECSPI_DMA_RXTDEN           (1 << 31)
 280
 281 #define MX51_ECSPI_STAT         0x18
 282 #define MX51_ECSPI_STAT_RR              (1 <<  3)
 283
 284 #define MX51_ECSPI_TESTREG      0x20
 285 #define MX51_ECSPI_TESTREG_LBC  BIT(31)
 286
 287 static void spi_imx_u32_swap_u8(struct spi_transfer *transfer, u32 *buf)
 288 {
 289         int i;
 290
 291         if (!buf)
 292                 return;
 293
 294         for (i = 0; i < transfer->len / 4; i++)
 295                 *(buf + i) = cpu_to_be32(*(buf + i));
 296 }
 297
 298 static void spi_imx_u32_swap_u16(struct spi_transfer *transfer, u32 *buf)
 299 {
 300         int i;
 301
 302         if (!buf)
 303                 return;
 304
 305         for (i = 0; i < transfer->len / 4; i++) {
 306                 u16 *temp = (u16 *)buf;
 307
 308                 *(temp + i * 2) = cpu_to_be16(*(temp + i * 2));
 309                 *(temp + i * 2 + 1) = cpu_to_be16(*(temp + i * 2 + 1));
 310
 311                 *(buf + i) = cpu_to_be32(*(buf + i));
 312         }
 313 }
 314
 315 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
 316 {
 317         if (!spi_imx->bpw_rx) {
 318                 spi_imx_buf_rx_u32(spi_imx);
 319                 return;
 320         }
 321
 322         if (spi_imx->bpw_w == 1)
 323                 spi_imx_buf_rx_u8(spi_imx);
 324         else if (spi_imx->bpw_w == 2)
 325                 spi_imx_buf_rx_u16(spi_imx);
 326 }
 327
 328 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
 329 {
 330         u32 ctrl, val;
 331
 332         if (spi_imx->count == spi_imx->count_index) {
 333                 spi_imx->count_index = spi_imx->count > sizeof(u32) ?
 334                                         spi_imx->count % sizeof(u32) : 0;
 335                 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 336                 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
 337                 if (spi_imx->count >= sizeof(u32)) {
 338                         val = spi_imx->count - spi_imx->count_index;
 339                 } else {
 340                         val = spi_imx->bpw_w;
 341                         spi_imx->bpw_rx = 1;
 342                 }
 343                 ctrl |= ((val * 8 - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
 344                 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 345         }
 346
 347         if (spi_imx->count >= sizeof(u32)) {
 348                 spi_imx_buf_tx_u32(spi_imx);
 349                 return;
 350         }
 351
 352         if (spi_imx->bpw_w == 1)
 353                 spi_imx_buf_tx_u8(spi_imx);
 354         else if (spi_imx->bpw_w == 2)
 355                 spi_imx_buf_tx_u16(spi_imx);
 356 }
 357
 358 /* MX51 eCSPI */
 359 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
 360                                       unsigned int fspi, unsigned int *fres)
 361 {
 362         /*
 363          * there are two 4-bit dividers, the pre-divider divides by
 364          * $pre, the post-divider by 2^$post
 365          */
 366         unsigned int pre, post;
 367         unsigned int fin = spi_imx->spi_clk;
 368
 369         if (unlikely(fspi > fin))
 370                 return 0;
 371
 372         post = fls(fin) - fls(fspi);
 373         if (fin > fspi << post)
 374                 post++;
 375
 376         /* now we have: (fin <= fspi << post) with post being minimal */
 377
 378         post = max(4U, post) - 4;
 379         if (unlikely(post > 0xf)) {
 380                 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
 381                                 fspi, fin);
 382                 return 0xff;
 383         }
 384
 385         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
 386
 387         dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
 388                         __func__, fin, fspi, post, pre);
 389
 390         /* Resulting frequency for the SCLK line. */
 391         *fres = (fin / (pre + 1)) >> post;
 392
 393         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
 394                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
 395 }
 396
 397 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
 398 {
 399         unsigned val = 0;
 400
 401         if (enable & MXC_INT_TE)
 402                 val |= MX51_ECSPI_INT_TEEN;
 403
 404         if (enable & MXC_INT_RR)
 405                 val |= MX51_ECSPI_INT_RREN;
 406
 407         writel(val, spi_imx->base + MX51_ECSPI_INT);
 408 }
 409
 410 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
 411 {
 412         u32 reg;
 413
 414         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
 415         reg |= MX51_ECSPI_CTRL_XCH;
 416         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
 417 }
 418
 419 static int mx51_ecspi_config(struct spi_device *spi,
 420                              struct spi_imx_config *config)
 421 {
 422         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 423         u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
 424         u32 clk = config->speed_hz, delay, reg;
 425         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 426
 427         /*
 428          * The hardware seems to have a race condition when changing modes. The
 429          * current assumption is that the selection of the channel arrives
 430          * earlier in the hardware than the mode bits when they are written at
 431          * the same time.
 432          * So set master mode for all channels as we do not support slave mode.
 433          */
 434         ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
 435
 436         /*
 437          * Enable SPI_RDY handling (falling edge/level triggered).
 438          */
 439         if (spi->mode & SPI_READY)
 440                 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
 441
 442         /* set clock speed */
 443         ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk);
 444         spi_imx->spi_bus_clk = clk;
 445
 446         /* set chip select to use */
 447         ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
 448
 449         if (spi_imx->dynamic_burst) {
 450                 if (config->len > MX51_ECSPI_CTRL_MAX_BURST)
 451                         ctrl |= MX51_ECSPI_CTRL_BL_MASK;
 452                 else
 453                         ctrl |= (((config->len - config->len % 4) * 8 - 1) <<
 454                                 MX51_ECSPI_CTRL_BL_OFFSET);
 455         } else {
 456                 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
 457         }
 458
 459         cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
 460
 461         if (spi->mode & SPI_CPHA)
 462                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
 463         else
 464                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
 465
 466         if (spi->mode & SPI_CPOL) {
 467                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 468                 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
 469         } else {
 470                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 471                 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
 472         }
 473         if (spi->mode & SPI_CS_HIGH)
 474                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
 475         else
 476                 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
 477
 478         if (spi_imx->usedma)
 479                 ctrl |= MX51_ECSPI_CTRL_SMC;
 480
 481         /* CTRL register always go first to bring out controller from reset */
 482         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 483
 484         reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
 485         if (spi->mode & SPI_LOOP)
 486                 reg |= MX51_ECSPI_TESTREG_LBC;
 487         else
 488                 reg &= ~MX51_ECSPI_TESTREG_LBC;
 489         writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
 490
 491         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 492
 493         /*
 494          * Wait until the changes in the configuration register CONFIGREG
 495          * propagate into the hardware. It takes exactly one tick of the
 496          * SCLK clock, but we will wait two SCLK clock just to be sure. The
 497          * effect of the delay it takes for the hardware to apply changes
 498          * is noticable if the SCLK clock run very slow. In such a case, if
 499          * the polarity of SCLK should be inverted, the GPIO ChipSelect might
 500          * be asserted before the SCLK polarity changes, which would disrupt
 501          * the SPI communication as the device on the other end would consider
 502          * the change of SCLK polarity as a clock tick already.
 503          */
 504         delay = (2 * 1000000) / clk;
 505         if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
 506                 udelay(delay);
 507         else                    /* SCLK is _very_ slow */
 508                 usleep_range(delay, delay + 10);
 509
 510         /*
 511          * Configure the DMA register: setup the watermark
 512          * and enable DMA request.
 513          */
 514
 515         writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
 516                 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
 517                 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
 518                 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
 519                 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
 520
 521         return 0;
 522 }
 523
 524 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
 525 {
 526         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
 527 }
 528
 529 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
 530 {
 531         /* drain receive buffer */
 532         while (mx51_ecspi_rx_available(spi_imx))
 533                 readl(spi_imx->base + MXC_CSPIRXDATA);
 534 }
 535
 536 #define MX31_INTREG_TEEN        (1 << 0)
 537 #define MX31_INTREG_RREN        (1 << 3)
 538
 539 #define MX31_CSPICTRL_ENABLE    (1 << 0)
 540 #define MX31_CSPICTRL_MASTER    (1 << 1)
 541 #define MX31_CSPICTRL_XCH       (1 << 2)
 542 #define MX31_CSPICTRL_SMC       (1 << 3)
 543 #define MX31_CSPICTRL_POL       (1 << 4)
 544 #define MX31_CSPICTRL_PHA       (1 << 5)
 545 #define MX31_CSPICTRL_SSCTL     (1 << 6)
 546 #define MX31_CSPICTRL_SSPOL     (1 << 7)
 547 #define MX31_CSPICTRL_BC_SHIFT  8
 548 #define MX35_CSPICTRL_BL_SHIFT  20
 549 #define MX31_CSPICTRL_CS_SHIFT  24
 550 #define MX35_CSPICTRL_CS_SHIFT  12
 551 #define MX31_CSPICTRL_DR_SHIFT  16
 552
 553 #define MX31_CSPI_DMAREG        0x10
 554 #define MX31_DMAREG_RH_DEN      (1<<4)
 555 #define MX31_DMAREG_TH_DEN      (1<<1)
 556
 557 #define MX31_CSPISTATUS         0x14
 558 #define MX31_STATUS_RR          (1 << 3)
 559
 560 #define MX31_CSPI_TESTREG       0x1C
 561 #define MX31_TEST_LBC           (1 << 14)
 562
 563 /* These functions also work for the i.MX35, but be aware that
 564  * the i.MX35 has a slightly different register layout for bits
 565  * we do not use here.
 566  */
 567 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 568 {
 569         unsigned int val = 0;
 570
 571         if (enable & MXC_INT_TE)
 572                 val |= MX31_INTREG_TEEN;
 573         if (enable & MXC_INT_RR)
 574                 val |= MX31_INTREG_RREN;
 575
 576         writel(val, spi_imx->base + MXC_CSPIINT);
 577 }
 578
 579 static void mx31_trigger(struct spi_imx_data *spi_imx)
 580 {
 581         unsigned int reg;
 582
 583         reg = readl(spi_imx->base + MXC_CSPICTRL);
 584         reg |= MX31_CSPICTRL_XCH;
 585         writel(reg, spi_imx->base + MXC_CSPICTRL);
 586 }
 587
 588 static int mx31_config(struct spi_device *spi, struct spi_imx_config *config)
 589 {
 590         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 591         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 592         unsigned int clk;
 593
 594         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz, &clk) <<
 595                 MX31_CSPICTRL_DR_SHIFT;
 596         spi_imx->spi_bus_clk = clk;
 597
 598         if (is_imx35_cspi(spi_imx)) {
 599                 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
 600                 reg |= MX31_CSPICTRL_SSCTL;
 601         } else {
 602                 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
 603         }
 604
 605         if (spi->mode & SPI_CPHA)
 606                 reg |= MX31_CSPICTRL_PHA;
 607         if (spi->mode & SPI_CPOL)
 608                 reg |= MX31_CSPICTRL_POL;
 609         if (spi->mode & SPI_CS_HIGH)
 610                 reg |= MX31_CSPICTRL_SSPOL;
 611         if (spi->cs_gpio < 0)
 612                 reg |= (spi->cs_gpio + 32) <<
 613                         (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
 614                                                   MX31_CSPICTRL_CS_SHIFT);
 615
 616         if (spi_imx->usedma)
 617                 reg |= MX31_CSPICTRL_SMC;
 618
 619         writel(reg, spi_imx->base + MXC_CSPICTRL);
 620
 621         reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
 622         if (spi->mode & SPI_LOOP)
 623                 reg |= MX31_TEST_LBC;
 624         else
 625                 reg &= ~MX31_TEST_LBC;
 626         writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
 627
 628         if (spi_imx->usedma) {
 629                 /* configure DMA requests when RXFIFO is half full and
 630                    when TXFIFO is half empty */
 631                 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
 632                         spi_imx->base + MX31_CSPI_DMAREG);
 633         }
 634
 635         return 0;
 636 }
 637
 638 static int mx31_rx_available(struct spi_imx_data *spi_imx)
 639 {
 640         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 641 }
 642
 643 static void mx31_reset(struct spi_imx_data *spi_imx)
 644 {
 645         /* drain receive buffer */
 646         while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
 647                 readl(spi_imx->base + MXC_CSPIRXDATA);
 648 }
 649
 650 #define MX21_INTREG_RR          (1 << 4)
 651 #define MX21_INTREG_TEEN        (1 << 9)
 652 #define MX21_INTREG_RREN        (1 << 13)
 653
 654 #define MX21_CSPICTRL_POL       (1 << 5)
 655 #define MX21_CSPICTRL_PHA       (1 << 6)
 656 #define MX21_CSPICTRL_SSPOL     (1 << 8)
 657 #define MX21_CSPICTRL_XCH       (1 << 9)
 658 #define MX21_CSPICTRL_ENABLE    (1 << 10)
 659 #define MX21_CSPICTRL_MASTER    (1 << 11)
 660 #define MX21_CSPICTRL_DR_SHIFT  14
 661 #define MX21_CSPICTRL_CS_SHIFT  19
 662
 663 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
 664 {
 665         unsigned int val = 0;
 666
 667         if (enable & MXC_INT_TE)
 668                 val |= MX21_INTREG_TEEN;
 669         if (enable & MXC_INT_RR)
 670                 val |= MX21_INTREG_RREN;
 671
 672         writel(val, spi_imx->base + MXC_CSPIINT);
 673 }
 674
 675 static void mx21_trigger(struct spi_imx_data *spi_imx)
 676 {
 677         unsigned int reg;
 678
 679         reg = readl(spi_imx->base + MXC_CSPICTRL);
 680         reg |= MX21_CSPICTRL_XCH;
 681         writel(reg, spi_imx->base + MXC_CSPICTRL);
 682 }
 683
 684 static int mx21_config(struct spi_device *spi, struct spi_imx_config *config)
 685 {
 686         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 687         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
 688         unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
 689         unsigned int clk;
 690
 691         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max, &clk)
 692                 << MX21_CSPICTRL_DR_SHIFT;
 693         spi_imx->spi_bus_clk = clk;
 694
 695         reg |= config->bpw - 1;
 696
 697         if (spi->mode & SPI_CPHA)
 698                 reg |= MX21_CSPICTRL_PHA;
 699         if (spi->mode & SPI_CPOL)
 700                 reg |= MX21_CSPICTRL_POL;
 701         if (spi->mode & SPI_CS_HIGH)
 702                 reg |= MX21_CSPICTRL_SSPOL;
 703         if (spi->cs_gpio < 0)
 704                 reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT;
 705
 706         writel(reg, spi_imx->base + MXC_CSPICTRL);
 707
 708         return 0;
 709 }
 710
 711 static int mx21_rx_available(struct spi_imx_data *spi_imx)
 712 {
 713         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
 714 }
 715
 716 static void mx21_reset(struct spi_imx_data *spi_imx)
 717 {
 718         writel(1, spi_imx->base + MXC_RESET);
 719 }
 720
 721 #define MX1_INTREG_RR           (1 << 3)
 722 #define MX1_INTREG_TEEN         (1 << 8)
 723 #define MX1_INTREG_RREN         (1 << 11)
 724
 725 #define MX1_CSPICTRL_POL        (1 << 4)
 726 #define MX1_CSPICTRL_PHA        (1 << 5)
 727 #define MX1_CSPICTRL_XCH        (1 << 8)
 728 #define MX1_CSPICTRL_ENABLE     (1 << 9)
 729 #define MX1_CSPICTRL_MASTER     (1 << 10)
 730 #define MX1_CSPICTRL_DR_SHIFT   13
 731
 732 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 733 {
 734         unsigned int val = 0;
 735
 736         if (enable & MXC_INT_TE)
 737                 val |= MX1_INTREG_TEEN;
 738         if (enable & MXC_INT_RR)
 739                 val |= MX1_INTREG_RREN;
 740
 741         writel(val, spi_imx->base + MXC_CSPIINT);
 742 }
 743
 744 static void mx1_trigger(struct spi_imx_data *spi_imx)
 745 {
 746         unsigned int reg;
 747
 748         reg = readl(spi_imx->base + MXC_CSPICTRL);
 749         reg |= MX1_CSPICTRL_XCH;
 750         writel(reg, spi_imx->base + MXC_CSPICTRL);
 751 }
 752
 753 static int mx1_config(struct spi_device *spi, struct spi_imx_config *config)
 754 {
 755         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 756         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
 757         unsigned int clk;
 758
 759         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz, &clk) <<
 760                 MX1_CSPICTRL_DR_SHIFT;
 761         spi_imx->spi_bus_clk = clk;
 762
 763         reg |= config->bpw - 1;
 764
 765         if (spi->mode & SPI_CPHA)
 766                 reg |= MX1_CSPICTRL_PHA;
 767         if (spi->mode & SPI_CPOL)
 768                 reg |= MX1_CSPICTRL_POL;
 769
 770         writel(reg, spi_imx->base + MXC_CSPICTRL);
 771
 772         return 0;
 773 }
 774
 775 static int mx1_rx_available(struct spi_imx_data *spi_imx)
 776 {
 777         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 778 }
 779
 780 static void mx1_reset(struct spi_imx_data *spi_imx)
 781 {
 782         writel(1, spi_imx->base + MXC_RESET);
 783 }
 784
 785 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
 786         .intctrl = mx1_intctrl,
 787         .config = mx1_config,
 788         .trigger = mx1_trigger,
 789         .rx_available = mx1_rx_available,
 790         .reset = mx1_reset,
 791         .devtype = IMX1_CSPI,
 792 };
 793
 794 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
 795         .intctrl = mx21_intctrl,
 796         .config = mx21_config,
 797         .trigger = mx21_trigger,
 798         .rx_available = mx21_rx_available,
 799         .reset = mx21_reset,
 800         .devtype = IMX21_CSPI,
 801 };
 802
 803 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
 804         /* i.mx27 cspi shares the functions with i.mx21 one */
 805         .intctrl = mx21_intctrl,
 806         .config = mx21_config,
 807         .trigger = mx21_trigger,
 808         .rx_available = mx21_rx_available,
 809         .reset = mx21_reset,
 810         .devtype = IMX27_CSPI,
 811 };
 812
 813 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
 814         .intctrl = mx31_intctrl,
 815         .config = mx31_config,
 816         .trigger = mx31_trigger,
 817         .rx_available = mx31_rx_available,
 818         .reset = mx31_reset,
 819         .devtype = IMX31_CSPI,
 820 };
 821
 822 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
 823         /* i.mx35 and later cspi shares the functions with i.mx31 one */
 824         .intctrl = mx31_intctrl,
 825         .config = mx31_config,
 826         .trigger = mx31_trigger,
 827         .rx_available = mx31_rx_available,
 828         .reset = mx31_reset,
 829         .devtype = IMX35_CSPI,
 830 };
 831
 832 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
 833         .intctrl = mx51_ecspi_intctrl,
 834         .config = mx51_ecspi_config,
 835         .trigger = mx51_ecspi_trigger,
 836         .rx_available = mx51_ecspi_rx_available,
 837         .reset = mx51_ecspi_reset,
 838         .devtype = IMX51_ECSPI,
 839 };
 840
 841 static const struct platform_device_id spi_imx_devtype[] = {
 842         {
 843                 .name = "imx1-cspi",
 844                 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
 845         }, {
 846                 .name = "imx21-cspi",
 847                 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
 848         }, {
 849                 .name = "imx27-cspi",
 850                 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
 851         }, {
 852                 .name = "imx31-cspi",
 853                 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
 854         }, {
 855                 .name = "imx35-cspi",
 856                 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
 857         }, {
 858                 .name = "imx51-ecspi",
 859                 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
 860         }, {
 861                 /* sentinel */
 862         }
 863 };
 864
 865 static const struct of_device_id spi_imx_dt_ids[] = {
 866         { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
 867         { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
 868         { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
 869         { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
 870         { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
 871         { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
 872         { /* sentinel */ }
 873 };
 874 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
 875
 876 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
 877 {
 878         int active = is_active != BITBANG_CS_INACTIVE;
 879         int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
 880
 881         if (!gpio_is_valid(spi->cs_gpio))
 882                 return;
 883
 884         gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
 885 }
 886
 887 static void spi_imx_push(struct spi_imx_data *spi_imx)
 888 {
 889         while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
 890                 if (!spi_imx->count)
 891                         break;
 892                 if (spi_imx->txfifo && (spi_imx->count == spi_imx->count_index))
 893                         break;
 894                 spi_imx->tx(spi_imx);
 895                 spi_imx->txfifo++;
 896         }
 897
 898         spi_imx->devtype_data->trigger(spi_imx);
 899 }
 900
 901 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
 902 {
 903         struct spi_imx_data *spi_imx = dev_id;
 904
 905         while (spi_imx->devtype_data->rx_available(spi_imx)) {
 906                 spi_imx->rx(spi_imx);
 907                 spi_imx->txfifo--;
 908         }
 909
 910         if (spi_imx->count) {
 911                 spi_imx_push(spi_imx);
 912                 return IRQ_HANDLED;
 913         }
 914
 915         if (spi_imx->txfifo) {
 916                 /* No data left to push, but still waiting for rx data,
 917                  * enable receive data available interrupt.
 918                  */
 919                 spi_imx->devtype_data->intctrl(
 920                                 spi_imx, MXC_INT_RR);
 921                 return IRQ_HANDLED;
 922         }
 923
 924         spi_imx->devtype_data->intctrl(spi_imx, 0);
 925         complete(&spi_imx->xfer_done);
 926
 927         return IRQ_HANDLED;
 928 }
 929
 930 static int spi_imx_dma_configure(struct spi_master *master,
 931                                  int bytes_per_word)
 932 {
 933         int ret;
 934         enum dma_slave_buswidth buswidth;
 935         struct dma_slave_config rx = {}, tx = {};
 936         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
 937
 938         switch (bytes_per_word) {
 939         case 4:
 940                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
 941                 break;
 942         case 2:
 943                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
 944                 break;
 945         case 1:
 946                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
 947                 break;
 948         default:
 949                 return -EINVAL;
 950         }
 951
 952         tx.direction = DMA_MEM_TO_DEV;
 953         tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
 954         tx.dst_addr_width = buswidth;
 955         tx.dst_maxburst = spi_imx->wml;
 956         ret = dmaengine_slave_config(master->dma_tx, &tx);
 957         if (ret) {
 958                 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
 959                 return ret;
 960         }
 961
 962         rx.direction = DMA_DEV_TO_MEM;
 963         rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
 964         rx.src_addr_width = buswidth;
 965         rx.src_maxburst = spi_imx->wml;
 966         ret = dmaengine_slave_config(master->dma_rx, &rx);
 967         if (ret) {
 968                 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
 969                 return ret;
 970         }
 971
 972         spi_imx->bytes_per_word = bytes_per_word;
 973
 974         return 0;
 975 }
 976
 977 static int spi_imx_setupxfer(struct spi_device *spi,
 978                                  struct spi_transfer *t)
 979 {
 980         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 981         struct spi_imx_config config;
 982         int ret;
 983
 984         spi_imx->dynamic_burst = 0;
 985         spi_imx->bpw_rx = 0;
 986
 987         config.bpw = t ? t->bits_per_word : spi->bits_per_word;
 988         config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
 989         config.len = t->len;
 990
 991         if (!config.speed_hz)
 992                 config.speed_hz = spi->max_speed_hz;
 993         if (!config.bpw)
 994                 config.bpw = spi->bits_per_word;
 995
 996         /* Initialize the functions for transfer */
 997         if (config.bpw <= 8) {
 998                 if (t->len >= sizeof(u32) && is_imx51_ecspi(spi_imx)) {
 999                         spi_imx->dynamic_burst = 1;
1000                         spi_imx->rx = spi_imx_buf_rx_swap;
1001                         spi_imx->tx = spi_imx_buf_tx_swap;
1002                 } else {
1003                         spi_imx->rx = spi_imx_buf_rx_u8;
1004                         spi_imx->tx = spi_imx_buf_tx_u8;
1005                 }
1006         } else if (config.bpw <= 16) {
1007                 if (t->len >= sizeof(u32) && is_imx51_ecspi(spi_imx)) {
1008                         spi_imx->dynamic_burst = 1;
1009                         spi_imx->rx = spi_imx_buf_rx_swap;
1010                         spi_imx->tx = spi_imx_buf_tx_swap;
1011                 } else {
1012                         spi_imx->rx = spi_imx_buf_rx_u16;
1013                         spi_imx->tx = spi_imx_buf_tx_u16;
1014                 }
1015         } else {
1016                 if (is_imx51_ecspi(spi_imx)) {
1017                         spi_imx->dynamic_burst = 1;
1018                         spi_imx->rx = spi_imx_buf_rx_swap;
1019                         spi_imx->tx = spi_imx_buf_tx_swap;
1020                 } else {
1021                         spi_imx->rx = spi_imx_buf_rx_u32;
1022                         spi_imx->tx = spi_imx_buf_tx_u32;
1023                 }
1024         }
1025
1026         if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1027                 spi_imx->usedma = 1;
1028         else
1029                 spi_imx->usedma = 0;
1030
1031         spi_imx->bpw_w = DIV_ROUND_UP(config.bpw, 8);
1032
1033         if (spi_imx->usedma) {
1034                 ret = spi_imx_dma_configure(spi->master,
1035                                             spi_imx_bytes_per_word(config.bpw));
1036                 if (ret)
1037                         return ret;
1038         }
1039
1040         spi_imx->devtype_data->config(spi, &config);
1041
1042         return 0;
1043 }
1044
1045 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1046 {
1047         struct spi_master *master = spi_imx->bitbang.master;
1048
1049         if (master->dma_rx) {
1050                 dma_release_channel(master->dma_rx);
1051                 master->dma_rx = NULL;
1052         }
1053
1054         if (master->dma_tx) {
1055                 dma_release_channel(master->dma_tx);
1056                 master->dma_tx = NULL;
1057         }
1058 }
1059
1060 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1061                              struct spi_master *master)
1062 {
1063         int ret;
1064
1065         /* use pio mode for i.mx6dl chip TKT238285 */
1066         if (of_machine_is_compatible("fsl,imx6dl"))
1067                 return 0;
1068
1069         spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2;
1070
1071         /* Prepare for TX DMA: */
1072         master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1073         if (IS_ERR(master->dma_tx)) {
1074                 ret = PTR_ERR(master->dma_tx);
1075                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1076                 master->dma_tx = NULL;
1077                 goto err;
1078         }
1079
1080         /* Prepare for RX : */
1081         master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1082         if (IS_ERR(master->dma_rx)) {
1083                 ret = PTR_ERR(master->dma_rx);
1084                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1085                 master->dma_rx = NULL;
1086                 goto err;
1087         }
1088
1089         spi_imx_dma_configure(master, 1);
1090
1091         init_completion(&spi_imx->dma_rx_completion);
1092         init_completion(&spi_imx->dma_tx_completion);
1093         master->can_dma = spi_imx_can_dma;
1094         master->max_dma_len = MAX_SDMA_BD_BYTES;
1095         spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1096                                          SPI_MASTER_MUST_TX;
1097
1098         return 0;
1099 err:
1100         spi_imx_sdma_exit(spi_imx);
1101         return ret;
1102 }
1103
1104 static void spi_imx_dma_rx_callback(void *cookie)
1105 {
1106         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1107
1108         complete(&spi_imx->dma_rx_completion);
1109 }
1110
1111 static void spi_imx_dma_tx_callback(void *cookie)
1112 {
1113         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1114
1115         complete(&spi_imx->dma_tx_completion);
1116 }
1117
1118 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1119 {
1120         unsigned long timeout = 0;
1121
1122         /* Time with actual data transfer and CS change delay related to HW */
1123         timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1124
1125         /* Add extra second for scheduler related activities */
1126         timeout += 1;
1127
1128         /* Double calculated timeout */
1129         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1130 }
1131
1132 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1133                                 struct spi_transfer *transfer)
1134 {
1135         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1136         unsigned long transfer_timeout;
1137         unsigned long timeout;
1138         struct spi_master *master = spi_imx->bitbang.master;
1139         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1140
1141         /*
1142          * The TX DMA setup starts the transfer, so make sure RX is configured
1143          * before TX.
1144          */
1145         desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1146                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1147                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1148         if (!desc_rx)
1149                 return -EINVAL;
1150
1151         desc_rx->callback = spi_imx_dma_rx_callback;
1152         desc_rx->callback_param = (void *)spi_imx;
1153         dmaengine_submit(desc_rx);
1154         reinit_completion(&spi_imx->dma_rx_completion);
1155         dma_async_issue_pending(master->dma_rx);
1156
1157         desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1158                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1159                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1160         if (!desc_tx) {
1161                 dmaengine_terminate_all(master->dma_tx);
1162                 return -EINVAL;
1163         }
1164
1165         desc_tx->callback = spi_imx_dma_tx_callback;
1166         desc_tx->callback_param = (void *)spi_imx;
1167         dmaengine_submit(desc_tx);
1168         reinit_completion(&spi_imx->dma_tx_completion);
1169         dma_async_issue_pending(master->dma_tx);
1170
1171         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1172
1173         /* Wait SDMA to finish the data transfer.*/
1174         timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1175                                                 transfer_timeout);
1176         if (!timeout) {
1177                 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1178                 dmaengine_terminate_all(master->dma_tx);
1179                 dmaengine_terminate_all(master->dma_rx);
1180                 return -ETIMEDOUT;
1181         }
1182
1183         timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1184                                               transfer_timeout);
1185         if (!timeout) {
1186                 dev_err(&master->dev, "I/O Error in DMA RX\n");
1187                 spi_imx->devtype_data->reset(spi_imx);
1188                 dmaengine_terminate_all(master->dma_rx);
1189                 return -ETIMEDOUT;
1190         }
1191
1192         return transfer->len;
1193 }
1194
1195 static int spi_imx_pio_transfer(struct spi_device *spi,
1196                                 struct spi_transfer *transfer)
1197 {
1198         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1199         unsigned long transfer_timeout;
1200         unsigned long timeout;
1201
1202         spi_imx->tx_buf = transfer->tx_buf;
1203         spi_imx->rx_buf = transfer->rx_buf;
1204         spi_imx->count = transfer->len;
1205         spi_imx->txfifo = 0;
1206
1207         if (spi_imx->dynamic_burst) {
1208                 if (spi_imx->count > MX51_ECSPI_CTRL_MAX_BURST)
1209                         spi_imx->count_index = spi_imx->count %
1210                                                MX51_ECSPI_CTRL_MAX_BURST;
1211                 else
1212                         spi_imx->count_index = spi_imx->count % sizeof(u32);
1213
1214                 switch (spi_imx->bpw_w) {
1215                 case 1:
1216                         spi_imx_u32_swap_u8(transfer,
1217                                             (u32 *)transfer->tx_buf);
1218                         break;
1219                 case 2:
1220                         spi_imx_u32_swap_u16(transfer,
1221                                              (u32 *)transfer->tx_buf);
1222                         break;
1223                 default:
1224                         break;
1225                 }
1226         }
1227
1228         reinit_completion(&spi_imx->xfer_done);
1229
1230         spi_imx_push(spi_imx);
1231
1232         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1233
1234         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1235
1236         timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1237                                               transfer_timeout);
1238         if (!timeout) {
1239                 dev_err(&spi->dev, "I/O Error in PIO\n");
1240                 spi_imx->devtype_data->reset(spi_imx);
1241                 return -ETIMEDOUT;
1242         }
1243
1244         if (spi_imx->dynamic_burst) {
1245                 switch (spi_imx->bpw_w) {
1246                 case 1:
1247                         spi_imx_u32_swap_u8(transfer,
1248                                             (u32 *)transfer->rx_buf);
1249                         break;
1250                 case 2:
1251                         spi_imx_u32_swap_u16(transfer,
1252                                              (u32 *)transfer->rx_buf);
1253                         break;
1254                 default:
1255                         break;
1256                 }
1257                 spi_imx->dynamic_burst = 0;
1258         }
1259
1260         return transfer->len;
1261 }
1262
1263 static int spi_imx_transfer(struct spi_device *spi,
1264                                 struct spi_transfer *transfer)
1265 {
1266         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1267
1268         if (spi_imx->usedma)
1269                 return spi_imx_dma_transfer(spi_imx, transfer);
1270         else
1271                 return spi_imx_pio_transfer(spi, transfer);
1272 }
1273
1274 static int spi_imx_setup(struct spi_device *spi)
1275 {
1276         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1277                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
1278
1279         if (gpio_is_valid(spi->cs_gpio))
1280                 gpio_direction_output(spi->cs_gpio,
1281                                       spi->mode & SPI_CS_HIGH ? 0 : 1);
1282
1283         spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1284
1285         return 0;
1286 }
1287
1288 static void spi_imx_cleanup(struct spi_device *spi)
1289 {
1290 }
1291
1292 static int
1293 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1294 {
1295         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1296         int ret;
1297
1298         ret = clk_enable(spi_imx->clk_per);
1299         if (ret)
1300                 return ret;
1301
1302         ret = clk_enable(spi_imx->clk_ipg);
1303         if (ret) {
1304                 clk_disable(spi_imx->clk_per);
1305                 return ret;
1306         }
1307
1308         return 0;
1309 }
1310
1311 static int
1312 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1313 {
1314         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1315
1316         clk_disable(spi_imx->clk_ipg);
1317         clk_disable(spi_imx->clk_per);
1318         return 0;
1319 }
1320
1321 static int spi_imx_probe(struct platform_device *pdev)
1322 {
1323         struct device_node *np = pdev->dev.of_node;
1324         const struct of_device_id *of_id =
1325                         of_match_device(spi_imx_dt_ids, &pdev->dev);
1326         struct spi_imx_master *mxc_platform_info =
1327                         dev_get_platdata(&pdev->dev);
1328         struct spi_master *master;
1329         struct spi_imx_data *spi_imx;
1330         struct resource *res;
1331         int i, ret, irq, spi_drctl;
1332
1333         if (!np && !mxc_platform_info) {
1334                 dev_err(&pdev->dev, "can't get the platform data\n");
1335                 return -EINVAL;
1336         }
1337
1338         master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
1339         ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1340         if ((ret < 0) || (spi_drctl >= 0x3)) {
1341                 /* '11' is reserved */
1342                 spi_drctl = 0;
1343         }
1344
1345         if (!master)
1346                 return -ENOMEM;
1347
1348         platform_set_drvdata(pdev, master);
1349
1350         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1351         master->bus_num = np ? -1 : pdev->id;
1352
1353         spi_imx = spi_master_get_devdata(master);
1354         spi_imx->bitbang.master = master;
1355         spi_imx->dev = &pdev->dev;
1356
1357         spi_imx->devtype_data = of_id ? of_id->data :
1358                 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1359
1360         if (mxc_platform_info) {
1361                 master->num_chipselect = mxc_platform_info->num_chipselect;
1362                 master->cs_gpios = devm_kzalloc(&master->dev,
1363                         sizeof(int) * master->num_chipselect, GFP_KERNEL);
1364                 if (!master->cs_gpios)
1365                         return -ENOMEM;
1366
1367                 for (i = 0; i < master->num_chipselect; i++)
1368                         master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1369         }
1370
1371         spi_imx->bitbang.chipselect = spi_imx_chipselect;
1372         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1373         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1374         spi_imx->bitbang.master->setup = spi_imx_setup;
1375         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1376         spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1377         spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1378         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1379         if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx))
1380                 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1381
1382         spi_imx->spi_drctl = spi_drctl;
1383
1384         init_completion(&spi_imx->xfer_done);
1385
1386         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1387         spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1388         if (IS_ERR(spi_imx->base)) {
1389                 ret = PTR_ERR(spi_imx->base);
1390                 goto out_master_put;
1391         }
1392         spi_imx->base_phys = res->start;
1393
1394         irq = platform_get_irq(pdev, 0);
1395         if (irq < 0) {
1396                 ret = irq;
1397                 goto out_master_put;
1398         }
1399
1400         ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1401                                dev_name(&pdev->dev), spi_imx);
1402         if (ret) {
1403                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1404                 goto out_master_put;
1405         }
1406
1407         spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1408         if (IS_ERR(spi_imx->clk_ipg)) {
1409                 ret = PTR_ERR(spi_imx->clk_ipg);
1410                 goto out_master_put;
1411         }
1412
1413         spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1414         if (IS_ERR(spi_imx->clk_per)) {
1415                 ret = PTR_ERR(spi_imx->clk_per);
1416                 goto out_master_put;
1417         }
1418
1419         ret = clk_prepare_enable(spi_imx->clk_per);
1420         if (ret)
1421                 goto out_master_put;
1422
1423         ret = clk_prepare_enable(spi_imx->clk_ipg);
1424         if (ret)
1425                 goto out_put_per;
1426
1427         spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1428         /*
1429          * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1430          * if validated on other chips.
1431          */
1432         if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) {
1433                 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1434                 if (ret == -EPROBE_DEFER)
1435                         goto out_clk_put;
1436
1437                 if (ret < 0)
1438                         dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1439                                 ret);
1440         }
1441
1442         spi_imx->devtype_data->reset(spi_imx);
1443
1444         spi_imx->devtype_data->intctrl(spi_imx, 0);
1445
1446         master->dev.of_node = pdev->dev.of_node;
1447         ret = spi_bitbang_start(&spi_imx->bitbang);
1448         if (ret) {
1449                 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1450                 goto out_clk_put;
1451         }
1452
1453         if (!master->cs_gpios) {
1454                 dev_err(&pdev->dev, "No CS GPIOs available\n");
1455                 ret = -EINVAL;
1456                 goto out_clk_put;
1457         }
1458
1459         for (i = 0; i < master->num_chipselect; i++) {
1460                 if (!gpio_is_valid(master->cs_gpios[i]))
1461                         continue;
1462
1463                 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
1464                                         DRIVER_NAME);
1465                 if (ret) {
1466                         dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1467                                 master->cs_gpios[i]);
1468                         goto out_clk_put;
1469                 }
1470         }
1471
1472         dev_info(&pdev->dev, "probed\n");
1473
1474         clk_disable(spi_imx->clk_ipg);
1475         clk_disable(spi_imx->clk_per);
1476         return ret;
1477
1478 out_clk_put:
1479         clk_disable_unprepare(spi_imx->clk_ipg);
1480 out_put_per:
1481         clk_disable_unprepare(spi_imx->clk_per);
1482 out_master_put:
1483         spi_master_put(master);
1484
1485         return ret;
1486 }
1487
1488 static int spi_imx_remove(struct platform_device *pdev)
1489 {
1490         struct spi_master *master = platform_get_drvdata(pdev);
1491         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1492
1493         spi_bitbang_stop(&spi_imx->bitbang);
1494
1495         writel(0, spi_imx->base + MXC_CSPICTRL);
1496         clk_unprepare(spi_imx->clk_ipg);
1497         clk_unprepare(spi_imx->clk_per);
1498         spi_imx_sdma_exit(spi_imx);
1499         spi_master_put(master);
1500
1501         return 0;
1502 }
1503
1504 static struct platform_driver spi_imx_driver = {
1505         .driver = {
1506                    .name = DRIVER_NAME,
1507                    .of_match_table = spi_imx_dt_ids,
1508                    },
1509         .id_table = spi_imx_devtype,
1510         .probe = spi_imx_probe,
1511         .remove = spi_imx_remove,
1512 };
1513 module_platform_driver(spi_imx_driver);
1514
1515 MODULE_DESCRIPTION("SPI Master Controller driver");
1516 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1517 MODULE_LICENSE("GPL");
1518 MODULE_ALIAS("platform:" DRIVER_NAME);