drivers/spi/spi-imx.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2008 Juergen Beisert
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the
  16  * Free Software Foundation
  17  * 51 Franklin Street, Fifth Floor
  18  * Boston, MA  02110-1301, USA.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/completion.h>
  23 #include <linux/delay.h>
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/slab.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/spi/spi_bitbang.h>
  37 #include <linux/types.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/of_gpio.h>
  41
  42 #include <linux/platform_data/dma-imx.h>
  43 #include <linux/platform_data/spi-imx.h>
  44
  45 #define DRIVER_NAME "spi_imx"
  46
  47 #define MXC_CSPIRXDATA          0x00
  48 #define MXC_CSPITXDATA          0x04
  49 #define MXC_CSPICTRL            0x08
  50 #define MXC_CSPIINT             0x0c
  51 #define MXC_RESET               0x1c
  52
  53 /* generic defines to abstract from the different register layouts */
  54 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
  55 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
  56 #define MXC_INT_RDR     BIT(4) /* Receive date threshold interrupt */
  57
  58 /* The maximum  bytes that a sdma BD can transfer.*/
  59 #define MAX_SDMA_BD_BYTES  (1 << 15)
  60 #define MX51_ECSPI_CTRL_MAX_BURST       512
  61 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
  62 #define MX53_MAX_TRANSFER_BYTES         512
  63
  64 enum spi_imx_devtype {
  65         IMX1_CSPI,
  66         IMX21_CSPI,
  67         IMX27_CSPI,
  68         IMX31_CSPI,
  69         IMX35_CSPI,     /* CSPI on all i.mx except above */
  70         IMX51_ECSPI,    /* ECSPI on i.mx51 */
  71         IMX53_ECSPI,    /* ECSPI on i.mx53 and later */
  72 };
  73
  74 struct spi_imx_data;
  75
  76 struct spi_imx_devtype_data {
  77         void (*intctrl)(struct spi_imx_data *, int);
  78         int (*config)(struct spi_device *);
  79         void (*trigger)(struct spi_imx_data *);
  80         int (*rx_available)(struct spi_imx_data *);
  81         void (*reset)(struct spi_imx_data *);
  82         void (*disable)(struct spi_imx_data *);
  83         bool has_dmamode;
  84         bool has_slavemode;
  85         unsigned int fifo_size;
  86         bool dynamic_burst;
  87         enum spi_imx_devtype devtype;
  88 };
  89
  90 struct spi_imx_data {
  91         struct spi_bitbang bitbang;
  92         struct device *dev;
  93
  94         struct completion xfer_done;
  95         void __iomem *base;
  96         unsigned long base_phys;
  97
  98         struct clk *clk_per;
  99         struct clk *clk_ipg;
 100         unsigned long spi_clk;
 101         unsigned int spi_bus_clk;
 102
 103         unsigned int speed_hz;
 104         unsigned int bits_per_word;
 105         unsigned int spi_drctl;
 106
 107         unsigned int count, remainder;
 108         void (*tx)(struct spi_imx_data *);
 109         void (*rx)(struct spi_imx_data *);
 110         void *rx_buf;
 111         const void *tx_buf;
 112         unsigned int txfifo; /* number of words pushed in tx FIFO */
 113         unsigned int dynamic_burst, read_u32;
 114         unsigned int word_mask;
 115
 116         /* Slave mode */
 117         bool slave_mode;
 118         bool slave_aborted;
 119         unsigned int slave_burst;
 120
 121         /* DMA */
 122         bool usedma;
 123         u32 wml;
 124         struct completion dma_rx_completion;
 125         struct completion dma_tx_completion;
 126
 127         const struct spi_imx_devtype_data *devtype_data;
 128 };
 129
 130 static inline int is_imx27_cspi(struct spi_imx_data *d)
 131 {
 132         return d->devtype_data->devtype == IMX27_CSPI;
 133 }
 134
 135 static inline int is_imx35_cspi(struct spi_imx_data *d)
 136 {
 137         return d->devtype_data->devtype == IMX35_CSPI;
 138 }
 139
 140 static inline int is_imx51_ecspi(struct spi_imx_data *d)
 141 {
 142         return d->devtype_data->devtype == IMX51_ECSPI;
 143 }
 144
 145 static inline int is_imx53_ecspi(struct spi_imx_data *d)
 146 {
 147         return d->devtype_data->devtype == IMX53_ECSPI;
 148 }
 149
 150 #define MXC_SPI_BUF_RX(type)                                            \
 151 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
 152 {                                                                       \
 153         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
 154                                                                         \
 155         if (spi_imx->rx_buf) {                                          \
 156                 *(type *)spi_imx->rx_buf = val;                         \
 157                 spi_imx->rx_buf += sizeof(type);                        \
 158         }                                                               \
 159 }
 160
 161 #define MXC_SPI_BUF_TX(type)                                            \
 162 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
 163 {                                                                       \
 164         type val = 0;                                                   \
 165                                                                         \
 166         if (spi_imx->tx_buf) {                                          \
 167                 val = *(type *)spi_imx->tx_buf;                         \
 168                 spi_imx->tx_buf += sizeof(type);                        \
 169         }                                                               \
 170                                                                         \
 171         spi_imx->count -= sizeof(type);                                 \
 172                                                                         \
 173         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
 174 }
 175
 176 MXC_SPI_BUF_RX(u8)
 177 MXC_SPI_BUF_TX(u8)
 178 MXC_SPI_BUF_RX(u16)
 179 MXC_SPI_BUF_TX(u16)
 180 MXC_SPI_BUF_RX(u32)
 181 MXC_SPI_BUF_TX(u32)
 182
 183 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 184  * (which is currently not the case in this driver)
 185  */
 186 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 187         256, 384, 512, 768, 1024};
 188
 189 /* MX21, MX27 */
 190 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 191                 unsigned int fspi, unsigned int max, unsigned int *fres)
 192 {
 193         int i;
 194
 195         for (i = 2; i < max; i++)
 196                 if (fspi * mxc_clkdivs[i] >= fin)
 197                         break;
 198
 199         *fres = fin / mxc_clkdivs[i];
 200         return i;
 201 }
 202
 203 /* MX1, MX31, MX35, MX51 CSPI */
 204 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 205                 unsigned int fspi, unsigned int *fres)
 206 {
 207         int i, div = 4;
 208
 209         for (i = 0; i < 7; i++) {
 210                 if (fspi * div >= fin)
 211                         goto out;
 212                 div <<= 1;
 213         }
 214
 215 out:
 216         *fres = fin / div;
 217         return i;
 218 }
 219
 220 static int spi_imx_bytes_per_word(const int bits_per_word)
 221 {
 222         return DIV_ROUND_UP(bits_per_word, BITS_PER_BYTE);
 223 }
 224
 225 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
 226                          struct spi_transfer *transfer)
 227 {
 228         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
 229         unsigned int bytes_per_word, i;
 230
 231         if (!master->dma_rx)
 232                 return false;
 233
 234         if (spi_imx->slave_mode)
 235                 return false;
 236
 237         bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
 238
 239         if (bytes_per_word != 1 && bytes_per_word != 2 && bytes_per_word != 4)
 240                 return false;
 241
 242         for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
 243                 if (!(transfer->len % (i * bytes_per_word)))
 244                         break;
 245         }
 246
 247         if (i == 0)
 248                 return false;
 249
 250         spi_imx->wml = i;
 251         spi_imx->dynamic_burst = 0;
 252
 253         return true;
 254 }
 255
 256 #define MX51_ECSPI_CTRL         0x08
 257 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
 258 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
 259 #define MX51_ECSPI_CTRL_SMC             (1 << 3)
 260 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
 261 #define MX51_ECSPI_CTRL_DRCTL(drctl)    ((drctl) << 16)
 262 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
 263 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
 264 #define MX51_ECSPI_CTRL_CS(cs)          ((cs) << 18)
 265 #define MX51_ECSPI_CTRL_BL_OFFSET       20
 266 #define MX51_ECSPI_CTRL_BL_MASK         (0xfff << 20)
 267
 268 #define MX51_ECSPI_CONFIG       0x0c
 269 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs) +  0))
 270 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs) +  4))
 271 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs) +  8))
 272 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs) + 12))
 273 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)   (1 << ((cs) + 20))
 274
 275 #define MX51_ECSPI_INT          0x10
 276 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
 277 #define MX51_ECSPI_INT_RREN             (1 <<  3)
 278 #define MX51_ECSPI_INT_RDREN            (1 <<  4)
 279
 280 #define MX51_ECSPI_DMA      0x14
 281 #define MX51_ECSPI_DMA_TX_WML(wml)      ((wml) & 0x3f)
 282 #define MX51_ECSPI_DMA_RX_WML(wml)      (((wml) & 0x3f) << 16)
 283 #define MX51_ECSPI_DMA_RXT_WML(wml)     (((wml) & 0x3f) << 24)
 284
 285 #define MX51_ECSPI_DMA_TEDEN            (1 << 7)
 286 #define MX51_ECSPI_DMA_RXDEN            (1 << 23)
 287 #define MX51_ECSPI_DMA_RXTDEN           (1 << 31)
 288
 289 #define MX51_ECSPI_STAT         0x18
 290 #define MX51_ECSPI_STAT_RR              (1 <<  3)
 291
 292 #define MX51_ECSPI_TESTREG      0x20
 293 #define MX51_ECSPI_TESTREG_LBC  BIT(31)
 294
 295 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
 296 {
 297         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
 298 #ifdef __LITTLE_ENDIAN
 299         unsigned int bytes_per_word;
 300 #endif
 301
 302         if (spi_imx->rx_buf) {
 303 #ifdef __LITTLE_ENDIAN
 304                 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 305                 if (bytes_per_word == 1)
 306                         val = cpu_to_be32(val);
 307                 else if (bytes_per_word == 2)
 308                         val = (val << 16) | (val >> 16);
 309 #endif
 310                 val &= spi_imx->word_mask;
 311                 *(u32 *)spi_imx->rx_buf = val;
 312                 spi_imx->rx_buf += sizeof(u32);
 313         }
 314 }
 315
 316 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
 317 {
 318         unsigned int bytes_per_word;
 319
 320         bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 321         if (spi_imx->read_u32) {
 322                 spi_imx_buf_rx_swap_u32(spi_imx);
 323                 return;
 324         }
 325
 326         if (bytes_per_word == 1)
 327                 spi_imx_buf_rx_u8(spi_imx);
 328         else if (bytes_per_word == 2)
 329                 spi_imx_buf_rx_u16(spi_imx);
 330 }
 331
 332 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
 333 {
 334         u32 val = 0;
 335 #ifdef __LITTLE_ENDIAN
 336         unsigned int bytes_per_word;
 337 #endif
 338
 339         if (spi_imx->tx_buf) {
 340                 val = *(u32 *)spi_imx->tx_buf;
 341                 val &= spi_imx->word_mask;
 342                 spi_imx->tx_buf += sizeof(u32);
 343         }
 344
 345         spi_imx->count -= sizeof(u32);
 346 #ifdef __LITTLE_ENDIAN
 347         bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 348
 349         if (bytes_per_word == 1)
 350                 val = cpu_to_be32(val);
 351         else if (bytes_per_word == 2)
 352                 val = (val << 16) | (val >> 16);
 353 #endif
 354         writel(val, spi_imx->base + MXC_CSPITXDATA);
 355 }
 356
 357 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
 358 {
 359         u32 ctrl, val;
 360         unsigned int bytes_per_word;
 361
 362         if (spi_imx->count == spi_imx->remainder) {
 363                 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 364                 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
 365                 if (spi_imx->count > MX51_ECSPI_CTRL_MAX_BURST) {
 366                         spi_imx->remainder = spi_imx->count %
 367                                              MX51_ECSPI_CTRL_MAX_BURST;
 368                         val = MX51_ECSPI_CTRL_MAX_BURST * 8 - 1;
 369                 } else if (spi_imx->count >= sizeof(u32)) {
 370                         spi_imx->remainder = spi_imx->count % sizeof(u32);
 371                         val = (spi_imx->count - spi_imx->remainder) * 8 - 1;
 372                 } else {
 373                         spi_imx->remainder = 0;
 374                         val = spi_imx->bits_per_word - 1;
 375                         spi_imx->read_u32 = 0;
 376                 }
 377
 378                 ctrl |= (val << MX51_ECSPI_CTRL_BL_OFFSET);
 379                 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 380         }
 381
 382         if (spi_imx->count >= sizeof(u32)) {
 383                 spi_imx_buf_tx_swap_u32(spi_imx);
 384                 return;
 385         }
 386
 387         bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 388
 389         if (bytes_per_word == 1)
 390                 spi_imx_buf_tx_u8(spi_imx);
 391         else if (bytes_per_word == 2)
 392                 spi_imx_buf_tx_u16(spi_imx);
 393 }
 394
 395 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
 396 {
 397         u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
 398
 399         if (spi_imx->rx_buf) {
 400                 int n_bytes = spi_imx->slave_burst % sizeof(val);
 401
 402                 if (!n_bytes)
 403                         n_bytes = sizeof(val);
 404
 405                 memcpy(spi_imx->rx_buf,
 406                        ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
 407
 408                 spi_imx->rx_buf += n_bytes;
 409                 spi_imx->slave_burst -= n_bytes;
 410         }
 411 }
 412
 413 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
 414 {
 415         u32 val = 0;
 416         int n_bytes = spi_imx->count % sizeof(val);
 417
 418         if (!n_bytes)
 419                 n_bytes = sizeof(val);
 420
 421         if (spi_imx->tx_buf) {
 422                 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
 423                        spi_imx->tx_buf, n_bytes);
 424                 val = cpu_to_be32(val);
 425                 spi_imx->tx_buf += n_bytes;
 426         }
 427
 428         spi_imx->count -= n_bytes;
 429
 430         writel(val, spi_imx->base + MXC_CSPITXDATA);
 431 }
 432
 433 /* MX51 eCSPI */
 434 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
 435                                       unsigned int fspi, unsigned int *fres)
 436 {
 437         /*
 438          * there are two 4-bit dividers, the pre-divider divides by
 439          * $pre, the post-divider by 2^$post
 440          */
 441         unsigned int pre, post;
 442         unsigned int fin = spi_imx->spi_clk;
 443
 444         if (unlikely(fspi > fin))
 445                 return 0;
 446
 447         post = fls(fin) - fls(fspi);
 448         if (fin > fspi << post)
 449                 post++;
 450
 451         /* now we have: (fin <= fspi << post) with post being minimal */
 452
 453         post = max(4U, post) - 4;
 454         if (unlikely(post > 0xf)) {
 455                 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
 456                                 fspi, fin);
 457                 return 0xff;
 458         }
 459
 460         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
 461
 462         dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
 463                         __func__, fin, fspi, post, pre);
 464
 465         /* Resulting frequency for the SCLK line. */
 466         *fres = (fin / (pre + 1)) >> post;
 467
 468         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
 469                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
 470 }
 471
 472 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
 473 {
 474         unsigned val = 0;
 475
 476         if (enable & MXC_INT_TE)
 477                 val |= MX51_ECSPI_INT_TEEN;
 478
 479         if (enable & MXC_INT_RR)
 480                 val |= MX51_ECSPI_INT_RREN;
 481
 482         if (enable & MXC_INT_RDR)
 483                 val |= MX51_ECSPI_INT_RDREN;
 484
 485         writel(val, spi_imx->base + MX51_ECSPI_INT);
 486 }
 487
 488 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
 489 {
 490         u32 reg;
 491
 492         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
 493         reg |= MX51_ECSPI_CTRL_XCH;
 494         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
 495 }
 496
 497 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
 498 {
 499         u32 ctrl;
 500
 501         ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 502         ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
 503         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 504 }
 505
 506 static int mx51_ecspi_config(struct spi_device *spi)
 507 {
 508         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 509         u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
 510         u32 clk = spi_imx->speed_hz, delay, reg;
 511         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 512
 513         /* set Master or Slave mode */
 514         if (spi_imx->slave_mode)
 515                 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
 516         else
 517                 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
 518
 519         /*
 520          * Enable SPI_RDY handling (falling edge/level triggered).
 521          */
 522         if (spi->mode & SPI_READY)
 523                 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
 524
 525         /* set clock speed */
 526         ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
 527         spi_imx->spi_bus_clk = clk;
 528
 529         /* set chip select to use */
 530         ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
 531
 532         if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
 533                 ctrl |= (spi_imx->slave_burst * 8 - 1)
 534                         << MX51_ECSPI_CTRL_BL_OFFSET;
 535         else
 536                 ctrl |= (spi_imx->bits_per_word - 1)
 537                         << MX51_ECSPI_CTRL_BL_OFFSET;
 538
 539         /*
 540          * eCSPI burst completion by Chip Select signal in Slave mode
 541          * is not functional for imx53 Soc, config SPI burst completed when
 542          * BURST_LENGTH + 1 bits are received
 543          */
 544         if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
 545                 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
 546         else
 547                 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
 548
 549         if (spi->mode & SPI_CPHA)
 550                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
 551         else
 552                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
 553
 554         if (spi->mode & SPI_CPOL) {
 555                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 556                 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
 557         } else {
 558                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 559                 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
 560         }
 561         if (spi->mode & SPI_CS_HIGH)
 562                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
 563         else
 564                 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
 565
 566         if (spi_imx->usedma)
 567                 ctrl |= MX51_ECSPI_CTRL_SMC;
 568
 569         /* CTRL register always go first to bring out controller from reset */
 570         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 571
 572         reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
 573         if (spi->mode & SPI_LOOP)
 574                 reg |= MX51_ECSPI_TESTREG_LBC;
 575         else
 576                 reg &= ~MX51_ECSPI_TESTREG_LBC;
 577         writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
 578
 579         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 580
 581         /*
 582          * Wait until the changes in the configuration register CONFIGREG
 583          * propagate into the hardware. It takes exactly one tick of the
 584          * SCLK clock, but we will wait two SCLK clock just to be sure. The
 585          * effect of the delay it takes for the hardware to apply changes
 586          * is noticable if the SCLK clock run very slow. In such a case, if
 587          * the polarity of SCLK should be inverted, the GPIO ChipSelect might
 588          * be asserted before the SCLK polarity changes, which would disrupt
 589          * the SPI communication as the device on the other end would consider
 590          * the change of SCLK polarity as a clock tick already.
 591          */
 592         delay = (2 * 1000000) / clk;
 593         if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
 594                 udelay(delay);
 595         else                    /* SCLK is _very_ slow */
 596                 usleep_range(delay, delay + 10);
 597
 598         /*
 599          * Configure the DMA register: setup the watermark
 600          * and enable DMA request.
 601          */
 602
 603         writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
 604                 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
 605                 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
 606                 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
 607                 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
 608
 609         return 0;
 610 }
 611
 612 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
 613 {
 614         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
 615 }
 616
 617 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
 618 {
 619         /* drain receive buffer */
 620         while (mx51_ecspi_rx_available(spi_imx))
 621                 readl(spi_imx->base + MXC_CSPIRXDATA);
 622 }
 623
 624 #define MX31_INTREG_TEEN        (1 << 0)
 625 #define MX31_INTREG_RREN        (1 << 3)
 626
 627 #define MX31_CSPICTRL_ENABLE    (1 << 0)
 628 #define MX31_CSPICTRL_MASTER    (1 << 1)
 629 #define MX31_CSPICTRL_XCH       (1 << 2)
 630 #define MX31_CSPICTRL_SMC       (1 << 3)
 631 #define MX31_CSPICTRL_POL       (1 << 4)
 632 #define MX31_CSPICTRL_PHA       (1 << 5)
 633 #define MX31_CSPICTRL_SSCTL     (1 << 6)
 634 #define MX31_CSPICTRL_SSPOL     (1 << 7)
 635 #define MX31_CSPICTRL_BC_SHIFT  8
 636 #define MX35_CSPICTRL_BL_SHIFT  20
 637 #define MX31_CSPICTRL_CS_SHIFT  24
 638 #define MX35_CSPICTRL_CS_SHIFT  12
 639 #define MX31_CSPICTRL_DR_SHIFT  16
 640
 641 #define MX31_CSPI_DMAREG        0x10
 642 #define MX31_DMAREG_RH_DEN      (1<<4)
 643 #define MX31_DMAREG_TH_DEN      (1<<1)
 644
 645 #define MX31_CSPISTATUS         0x14
 646 #define MX31_STATUS_RR          (1 << 3)
 647
 648 #define MX31_CSPI_TESTREG       0x1C
 649 #define MX31_TEST_LBC           (1 << 14)
 650
 651 /* These functions also work for the i.MX35, but be aware that
 652  * the i.MX35 has a slightly different register layout for bits
 653  * we do not use here.
 654  */
 655 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 656 {
 657         unsigned int val = 0;
 658
 659         if (enable & MXC_INT_TE)
 660                 val |= MX31_INTREG_TEEN;
 661         if (enable & MXC_INT_RR)
 662                 val |= MX31_INTREG_RREN;
 663
 664         writel(val, spi_imx->base + MXC_CSPIINT);
 665 }
 666
 667 static void mx31_trigger(struct spi_imx_data *spi_imx)
 668 {
 669         unsigned int reg;
 670
 671         reg = readl(spi_imx->base + MXC_CSPICTRL);
 672         reg |= MX31_CSPICTRL_XCH;
 673         writel(reg, spi_imx->base + MXC_CSPICTRL);
 674 }
 675
 676 static int mx31_config(struct spi_device *spi)
 677 {
 678         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 679         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 680         unsigned int clk;
 681
 682         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
 683                 MX31_CSPICTRL_DR_SHIFT;
 684         spi_imx->spi_bus_clk = clk;
 685
 686         if (is_imx35_cspi(spi_imx)) {
 687                 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
 688                 reg |= MX31_CSPICTRL_SSCTL;
 689         } else {
 690                 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
 691         }
 692
 693         if (spi->mode & SPI_CPHA)
 694                 reg |= MX31_CSPICTRL_PHA;
 695         if (spi->mode & SPI_CPOL)
 696                 reg |= MX31_CSPICTRL_POL;
 697         if (spi->mode & SPI_CS_HIGH)
 698                 reg |= MX31_CSPICTRL_SSPOL;
 699         if (!gpio_is_valid(spi->cs_gpio))
 700                 reg |= (spi->chip_select) <<
 701                         (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
 702                                                   MX31_CSPICTRL_CS_SHIFT);
 703
 704         if (spi_imx->usedma)
 705                 reg |= MX31_CSPICTRL_SMC;
 706
 707         writel(reg, spi_imx->base + MXC_CSPICTRL);
 708
 709         reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
 710         if (spi->mode & SPI_LOOP)
 711                 reg |= MX31_TEST_LBC;
 712         else
 713                 reg &= ~MX31_TEST_LBC;
 714         writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
 715
 716         if (spi_imx->usedma) {
 717                 /* configure DMA requests when RXFIFO is half full and
 718                    when TXFIFO is half empty */
 719                 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
 720                         spi_imx->base + MX31_CSPI_DMAREG);
 721         }
 722
 723         return 0;
 724 }
 725
 726 static int mx31_rx_available(struct spi_imx_data *spi_imx)
 727 {
 728         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 729 }
 730
 731 static void mx31_reset(struct spi_imx_data *spi_imx)
 732 {
 733         /* drain receive buffer */
 734         while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
 735                 readl(spi_imx->base + MXC_CSPIRXDATA);
 736 }
 737
 738 #define MX21_INTREG_RR          (1 << 4)
 739 #define MX21_INTREG_TEEN        (1 << 9)
 740 #define MX21_INTREG_RREN        (1 << 13)
 741
 742 #define MX21_CSPICTRL_POL       (1 << 5)
 743 #define MX21_CSPICTRL_PHA       (1 << 6)
 744 #define MX21_CSPICTRL_SSPOL     (1 << 8)
 745 #define MX21_CSPICTRL_XCH       (1 << 9)
 746 #define MX21_CSPICTRL_ENABLE    (1 << 10)
 747 #define MX21_CSPICTRL_MASTER    (1 << 11)
 748 #define MX21_CSPICTRL_DR_SHIFT  14
 749 #define MX21_CSPICTRL_CS_SHIFT  19
 750
 751 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
 752 {
 753         unsigned int val = 0;
 754
 755         if (enable & MXC_INT_TE)
 756                 val |= MX21_INTREG_TEEN;
 757         if (enable & MXC_INT_RR)
 758                 val |= MX21_INTREG_RREN;
 759
 760         writel(val, spi_imx->base + MXC_CSPIINT);
 761 }
 762
 763 static void mx21_trigger(struct spi_imx_data *spi_imx)
 764 {
 765         unsigned int reg;
 766
 767         reg = readl(spi_imx->base + MXC_CSPICTRL);
 768         reg |= MX21_CSPICTRL_XCH;
 769         writel(reg, spi_imx->base + MXC_CSPICTRL);
 770 }
 771
 772 static int mx21_config(struct spi_device *spi)
 773 {
 774         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 775         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
 776         unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
 777         unsigned int clk;
 778
 779         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->speed_hz, max, &clk)
 780                 << MX21_CSPICTRL_DR_SHIFT;
 781         spi_imx->spi_bus_clk = clk;
 782
 783         reg |= spi_imx->bits_per_word - 1;
 784
 785         if (spi->mode & SPI_CPHA)
 786                 reg |= MX21_CSPICTRL_PHA;
 787         if (spi->mode & SPI_CPOL)
 788                 reg |= MX21_CSPICTRL_POL;
 789         if (spi->mode & SPI_CS_HIGH)
 790                 reg |= MX21_CSPICTRL_SSPOL;
 791         if (!gpio_is_valid(spi->cs_gpio))
 792                 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
 793
 794         writel(reg, spi_imx->base + MXC_CSPICTRL);
 795
 796         return 0;
 797 }
 798
 799 static int mx21_rx_available(struct spi_imx_data *spi_imx)
 800 {
 801         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
 802 }
 803
 804 static void mx21_reset(struct spi_imx_data *spi_imx)
 805 {
 806         writel(1, spi_imx->base + MXC_RESET);
 807 }
 808
 809 #define MX1_INTREG_RR           (1 << 3)
 810 #define MX1_INTREG_TEEN         (1 << 8)
 811 #define MX1_INTREG_RREN         (1 << 11)
 812
 813 #define MX1_CSPICTRL_POL        (1 << 4)
 814 #define MX1_CSPICTRL_PHA        (1 << 5)
 815 #define MX1_CSPICTRL_XCH        (1 << 8)
 816 #define MX1_CSPICTRL_ENABLE     (1 << 9)
 817 #define MX1_CSPICTRL_MASTER     (1 << 10)
 818 #define MX1_CSPICTRL_DR_SHIFT   13
 819
 820 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 821 {
 822         unsigned int val = 0;
 823
 824         if (enable & MXC_INT_TE)
 825                 val |= MX1_INTREG_TEEN;
 826         if (enable & MXC_INT_RR)
 827                 val |= MX1_INTREG_RREN;
 828
 829         writel(val, spi_imx->base + MXC_CSPIINT);
 830 }
 831
 832 static void mx1_trigger(struct spi_imx_data *spi_imx)
 833 {
 834         unsigned int reg;
 835
 836         reg = readl(spi_imx->base + MXC_CSPICTRL);
 837         reg |= MX1_CSPICTRL_XCH;
 838         writel(reg, spi_imx->base + MXC_CSPICTRL);
 839 }
 840
 841 static int mx1_config(struct spi_device *spi)
 842 {
 843         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 844         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
 845         unsigned int clk;
 846
 847         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
 848                 MX1_CSPICTRL_DR_SHIFT;
 849         spi_imx->spi_bus_clk = clk;
 850
 851         reg |= spi_imx->bits_per_word - 1;
 852
 853         if (spi->mode & SPI_CPHA)
 854                 reg |= MX1_CSPICTRL_PHA;
 855         if (spi->mode & SPI_CPOL)
 856                 reg |= MX1_CSPICTRL_POL;
 857
 858         writel(reg, spi_imx->base + MXC_CSPICTRL);
 859
 860         return 0;
 861 }
 862
 863 static int mx1_rx_available(struct spi_imx_data *spi_imx)
 864 {
 865         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 866 }
 867
 868 static void mx1_reset(struct spi_imx_data *spi_imx)
 869 {
 870         writel(1, spi_imx->base + MXC_RESET);
 871 }
 872
 873 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
 874         .intctrl = mx1_intctrl,
 875         .config = mx1_config,
 876         .trigger = mx1_trigger,
 877         .rx_available = mx1_rx_available,
 878         .reset = mx1_reset,
 879         .fifo_size = 8,
 880         .has_dmamode = false,
 881         .dynamic_burst = false,
 882         .has_slavemode = false,
 883         .devtype = IMX1_CSPI,
 884 };
 885
 886 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
 887         .intctrl = mx21_intctrl,
 888         .config = mx21_config,
 889         .trigger = mx21_trigger,
 890         .rx_available = mx21_rx_available,
 891         .reset = mx21_reset,
 892         .fifo_size = 8,
 893         .has_dmamode = false,
 894         .dynamic_burst = false,
 895         .has_slavemode = false,
 896         .devtype = IMX21_CSPI,
 897 };
 898
 899 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
 900         /* i.mx27 cspi shares the functions with i.mx21 one */
 901         .intctrl = mx21_intctrl,
 902         .config = mx21_config,
 903         .trigger = mx21_trigger,
 904         .rx_available = mx21_rx_available,
 905         .reset = mx21_reset,
 906         .fifo_size = 8,
 907         .has_dmamode = false,
 908         .dynamic_burst = false,
 909         .has_slavemode = false,
 910         .devtype = IMX27_CSPI,
 911 };
 912
 913 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
 914         .intctrl = mx31_intctrl,
 915         .config = mx31_config,
 916         .trigger = mx31_trigger,
 917         .rx_available = mx31_rx_available,
 918         .reset = mx31_reset,
 919         .fifo_size = 8,
 920         .has_dmamode = false,
 921         .dynamic_burst = false,
 922         .has_slavemode = false,
 923         .devtype = IMX31_CSPI,
 924 };
 925
 926 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
 927         /* i.mx35 and later cspi shares the functions with i.mx31 one */
 928         .intctrl = mx31_intctrl,
 929         .config = mx31_config,
 930         .trigger = mx31_trigger,
 931         .rx_available = mx31_rx_available,
 932         .reset = mx31_reset,
 933         .fifo_size = 8,
 934         .has_dmamode = true,
 935         .dynamic_burst = false,
 936         .has_slavemode = false,
 937         .devtype = IMX35_CSPI,
 938 };
 939
 940 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
 941         .intctrl = mx51_ecspi_intctrl,
 942         .config = mx51_ecspi_config,
 943         .trigger = mx51_ecspi_trigger,
 944         .rx_available = mx51_ecspi_rx_available,
 945         .reset = mx51_ecspi_reset,
 946         .fifo_size = 64,
 947         .has_dmamode = true,
 948         .dynamic_burst = true,
 949         .has_slavemode = true,
 950         .disable = mx51_ecspi_disable,
 951         .devtype = IMX51_ECSPI,
 952 };
 953
 954 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
 955         .intctrl = mx51_ecspi_intctrl,
 956         .config = mx51_ecspi_config,
 957         .trigger = mx51_ecspi_trigger,
 958         .rx_available = mx51_ecspi_rx_available,
 959         .reset = mx51_ecspi_reset,
 960         .fifo_size = 64,
 961         .has_dmamode = true,
 962         .has_slavemode = true,
 963         .disable = mx51_ecspi_disable,
 964         .devtype = IMX53_ECSPI,
 965 };
 966
 967 static const struct platform_device_id spi_imx_devtype[] = {
 968         {
 969                 .name = "imx1-cspi",
 970                 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
 971         }, {
 972                 .name = "imx21-cspi",
 973                 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
 974         }, {
 975                 .name = "imx27-cspi",
 976                 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
 977         }, {
 978                 .name = "imx31-cspi",
 979                 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
 980         }, {
 981                 .name = "imx35-cspi",
 982                 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
 983         }, {
 984                 .name = "imx51-ecspi",
 985                 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
 986         }, {
 987                 .name = "imx53-ecspi",
 988                 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
 989         }, {
 990                 /* sentinel */
 991         }
 992 };
 993
 994 static const struct of_device_id spi_imx_dt_ids[] = {
 995         { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
 996         { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
 997         { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
 998         { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
 999         { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1000         { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1001         { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1002         { /* sentinel */ }
1003 };
1004 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1005
1006 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
1007 {
1008         int active = is_active != BITBANG_CS_INACTIVE;
1009         int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
1010
1011         if (spi->mode & SPI_NO_CS)
1012                 return;
1013
1014         if (!gpio_is_valid(spi->cs_gpio))
1015                 return;
1016
1017         gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
1018 }
1019
1020 static void spi_imx_push(struct spi_imx_data *spi_imx)
1021 {
1022         while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1023                 if (!spi_imx->count)
1024                         break;
1025                 if (spi_imx->txfifo && (spi_imx->count == spi_imx->remainder))
1026                         break;
1027                 spi_imx->tx(spi_imx);
1028                 spi_imx->txfifo++;
1029         }
1030
1031         if (!spi_imx->slave_mode)
1032                 spi_imx->devtype_data->trigger(spi_imx);
1033 }
1034
1035 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1036 {
1037         struct spi_imx_data *spi_imx = dev_id;
1038
1039         while (spi_imx->txfifo &&
1040                spi_imx->devtype_data->rx_available(spi_imx)) {
1041                 spi_imx->rx(spi_imx);
1042                 spi_imx->txfifo--;
1043         }
1044
1045         if (spi_imx->count) {
1046                 spi_imx_push(spi_imx);
1047                 return IRQ_HANDLED;
1048         }
1049
1050         if (spi_imx->txfifo) {
1051                 /* No data left to push, but still waiting for rx data,
1052                  * enable receive data available interrupt.
1053                  */
1054                 spi_imx->devtype_data->intctrl(
1055                                 spi_imx, MXC_INT_RR);
1056                 return IRQ_HANDLED;
1057         }
1058
1059         spi_imx->devtype_data->intctrl(spi_imx, 0);
1060         complete(&spi_imx->xfer_done);
1061
1062         return IRQ_HANDLED;
1063 }
1064
1065 static int spi_imx_dma_configure(struct spi_master *master)
1066 {
1067         int ret;
1068         enum dma_slave_buswidth buswidth;
1069         struct dma_slave_config rx = {}, tx = {};
1070         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1071
1072         switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1073         case 4:
1074                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1075                 break;
1076         case 2:
1077                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1078                 break;
1079         case 1:
1080                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1081                 break;
1082         default:
1083                 return -EINVAL;
1084         }
1085
1086         tx.direction = DMA_MEM_TO_DEV;
1087         tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1088         tx.dst_addr_width = buswidth;
1089         tx.dst_maxburst = spi_imx->wml;
1090         ret = dmaengine_slave_config(master->dma_tx, &tx);
1091         if (ret) {
1092                 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1093                 return ret;
1094         }
1095
1096         rx.direction = DMA_DEV_TO_MEM;
1097         rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1098         rx.src_addr_width = buswidth;
1099         rx.src_maxburst = spi_imx->wml;
1100         ret = dmaengine_slave_config(master->dma_rx, &rx);
1101         if (ret) {
1102                 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1103                 return ret;
1104         }
1105
1106         return 0;
1107 }
1108
1109 static int spi_imx_setupxfer(struct spi_device *spi,
1110                                  struct spi_transfer *t)
1111 {
1112         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1113         int ret;
1114
1115         if (!t)
1116                 return 0;
1117
1118         spi_imx->bits_per_word = t->bits_per_word;
1119         spi_imx->speed_hz  = t->speed_hz;
1120
1121         /* Initialize the functions for transfer */
1122         if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode) {
1123                 u32 mask;
1124
1125                 spi_imx->dynamic_burst = 0;
1126                 spi_imx->remainder = 0;
1127                 spi_imx->read_u32  = 1;
1128
1129                 mask = (1 << spi_imx->bits_per_word) - 1;
1130                 spi_imx->rx = spi_imx_buf_rx_swap;
1131                 spi_imx->tx = spi_imx_buf_tx_swap;
1132                 spi_imx->dynamic_burst = 1;
1133                 spi_imx->remainder = t->len;
1134
1135                 if (spi_imx->bits_per_word <= 8)
1136                         spi_imx->word_mask = mask << 24 | mask << 16
1137                                              | mask << 8 | mask;
1138                 else if (spi_imx->bits_per_word <= 16)
1139                         spi_imx->word_mask = mask << 16 | mask;
1140                 else
1141                         spi_imx->word_mask = mask;
1142         } else {
1143                 if (spi_imx->bits_per_word <= 8) {
1144                         spi_imx->rx = spi_imx_buf_rx_u8;
1145                         spi_imx->tx = spi_imx_buf_tx_u8;
1146                 } else if (spi_imx->bits_per_word <= 16) {
1147                         spi_imx->rx = spi_imx_buf_rx_u16;
1148                         spi_imx->tx = spi_imx_buf_tx_u16;
1149                 } else {
1150                         spi_imx->rx = spi_imx_buf_rx_u32;
1151                         spi_imx->tx = spi_imx_buf_tx_u32;
1152                 }
1153         }
1154
1155         if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1156                 spi_imx->usedma = 1;
1157         else
1158                 spi_imx->usedma = 0;
1159
1160         if (spi_imx->usedma) {
1161                 ret = spi_imx_dma_configure(spi->master);
1162                 if (ret)
1163                         return ret;
1164         }
1165
1166         if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1167                 spi_imx->rx = mx53_ecspi_rx_slave;
1168                 spi_imx->tx = mx53_ecspi_tx_slave;
1169                 spi_imx->slave_burst = t->len;
1170         }
1171
1172         spi_imx->devtype_data->config(spi);
1173
1174         return 0;
1175 }
1176
1177 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1178 {
1179         struct spi_master *master = spi_imx->bitbang.master;
1180
1181         if (master->dma_rx) {
1182                 dma_release_channel(master->dma_rx);
1183                 master->dma_rx = NULL;
1184         }
1185
1186         if (master->dma_tx) {
1187                 dma_release_channel(master->dma_tx);
1188                 master->dma_tx = NULL;
1189         }
1190 }
1191
1192 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1193                              struct spi_master *master)
1194 {
1195         int ret;
1196
1197         /* use pio mode for i.mx6dl chip TKT238285 */
1198         if (of_machine_is_compatible("fsl,imx6dl"))
1199                 return 0;
1200
1201         spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1202
1203         /* Prepare for TX DMA: */
1204         master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1205         if (IS_ERR(master->dma_tx)) {
1206                 ret = PTR_ERR(master->dma_tx);
1207                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1208                 master->dma_tx = NULL;
1209                 goto err;
1210         }
1211
1212         /* Prepare for RX : */
1213         master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1214         if (IS_ERR(master->dma_rx)) {
1215                 ret = PTR_ERR(master->dma_rx);
1216                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1217                 master->dma_rx = NULL;
1218                 goto err;
1219         }
1220
1221         init_completion(&spi_imx->dma_rx_completion);
1222         init_completion(&spi_imx->dma_tx_completion);
1223         master->can_dma = spi_imx_can_dma;
1224         master->max_dma_len = MAX_SDMA_BD_BYTES;
1225         spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1226                                          SPI_MASTER_MUST_TX;
1227
1228         return 0;
1229 err:
1230         spi_imx_sdma_exit(spi_imx);
1231         return ret;
1232 }
1233
1234 static void spi_imx_dma_rx_callback(void *cookie)
1235 {
1236         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1237
1238         complete(&spi_imx->dma_rx_completion);
1239 }
1240
1241 static void spi_imx_dma_tx_callback(void *cookie)
1242 {
1243         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1244
1245         complete(&spi_imx->dma_tx_completion);
1246 }
1247
1248 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1249 {
1250         unsigned long timeout = 0;
1251
1252         /* Time with actual data transfer and CS change delay related to HW */
1253         timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1254
1255         /* Add extra second for scheduler related activities */
1256         timeout += 1;
1257
1258         /* Double calculated timeout */
1259         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1260 }
1261
1262 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1263                                 struct spi_transfer *transfer)
1264 {
1265         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1266         unsigned long transfer_timeout;
1267         unsigned long timeout;
1268         struct spi_master *master = spi_imx->bitbang.master;
1269         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1270
1271         /*
1272          * The TX DMA setup starts the transfer, so make sure RX is configured
1273          * before TX.
1274          */
1275         desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1276                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1277                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1278         if (!desc_rx)
1279                 return -EINVAL;
1280
1281         desc_rx->callback = spi_imx_dma_rx_callback;
1282         desc_rx->callback_param = (void *)spi_imx;
1283         dmaengine_submit(desc_rx);
1284         reinit_completion(&spi_imx->dma_rx_completion);
1285         dma_async_issue_pending(master->dma_rx);
1286
1287         desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1288                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1289                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1290         if (!desc_tx) {
1291                 dmaengine_terminate_all(master->dma_tx);
1292                 return -EINVAL;
1293         }
1294
1295         desc_tx->callback = spi_imx_dma_tx_callback;
1296         desc_tx->callback_param = (void *)spi_imx;
1297         dmaengine_submit(desc_tx);
1298         reinit_completion(&spi_imx->dma_tx_completion);
1299         dma_async_issue_pending(master->dma_tx);
1300
1301         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1302
1303         /* Wait SDMA to finish the data transfer.*/
1304         timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1305                                                 transfer_timeout);
1306         if (!timeout) {
1307                 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1308                 dmaengine_terminate_all(master->dma_tx);
1309                 dmaengine_terminate_all(master->dma_rx);
1310                 return -ETIMEDOUT;
1311         }
1312
1313         timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1314                                               transfer_timeout);
1315         if (!timeout) {
1316                 dev_err(&master->dev, "I/O Error in DMA RX\n");
1317                 spi_imx->devtype_data->reset(spi_imx);
1318                 dmaengine_terminate_all(master->dma_rx);
1319                 return -ETIMEDOUT;
1320         }
1321
1322         return transfer->len;
1323 }
1324
1325 static int spi_imx_pio_transfer(struct spi_device *spi,
1326                                 struct spi_transfer *transfer)
1327 {
1328         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1329         unsigned long transfer_timeout;
1330         unsigned long timeout;
1331
1332         spi_imx->tx_buf = transfer->tx_buf;
1333         spi_imx->rx_buf = transfer->rx_buf;
1334         spi_imx->count = transfer->len;
1335         spi_imx->txfifo = 0;
1336
1337         reinit_completion(&spi_imx->xfer_done);
1338
1339         spi_imx_push(spi_imx);
1340
1341         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1342
1343         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1344
1345         timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1346                                               transfer_timeout);
1347         if (!timeout) {
1348                 dev_err(&spi->dev, "I/O Error in PIO\n");
1349                 spi_imx->devtype_data->reset(spi_imx);
1350                 return -ETIMEDOUT;
1351         }
1352
1353         return transfer->len;
1354 }
1355
1356 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1357                                       struct spi_transfer *transfer)
1358 {
1359         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1360         int ret = transfer->len;
1361
1362         if (is_imx53_ecspi(spi_imx) &&
1363             transfer->len > MX53_MAX_TRANSFER_BYTES) {
1364                 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1365                         MX53_MAX_TRANSFER_BYTES);
1366                 return -EMSGSIZE;
1367         }
1368
1369         spi_imx->tx_buf = transfer->tx_buf;
1370         spi_imx->rx_buf = transfer->rx_buf;
1371         spi_imx->count = transfer->len;
1372         spi_imx->txfifo = 0;
1373
1374         reinit_completion(&spi_imx->xfer_done);
1375         spi_imx->slave_aborted = false;
1376
1377         spi_imx_push(spi_imx);
1378
1379         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1380
1381         if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1382             spi_imx->slave_aborted) {
1383                 dev_dbg(&spi->dev, "interrupted\n");
1384                 ret = -EINTR;
1385         }
1386
1387         /* ecspi has a HW issue when works in Slave mode,
1388          * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1389          * ECSPI_TXDATA keeps shift out the last word data,
1390          * so we have to disable ECSPI when in slave mode after the
1391          * transfer completes
1392          */
1393         if (spi_imx->devtype_data->disable)
1394                 spi_imx->devtype_data->disable(spi_imx);
1395
1396         return ret;
1397 }
1398
1399 static int spi_imx_transfer(struct spi_device *spi,
1400                                 struct spi_transfer *transfer)
1401 {
1402         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1403
1404         /* flush rxfifo before transfer */
1405         while (spi_imx->devtype_data->rx_available(spi_imx))
1406                 spi_imx->rx(spi_imx);
1407
1408         if (spi_imx->slave_mode)
1409                 return spi_imx_pio_transfer_slave(spi, transfer);
1410
1411         if (spi_imx->usedma)
1412                 return spi_imx_dma_transfer(spi_imx, transfer);
1413         else
1414                 return spi_imx_pio_transfer(spi, transfer);
1415 }
1416
1417 static int spi_imx_setup(struct spi_device *spi)
1418 {
1419         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1420                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
1421
1422         if (spi->mode & SPI_NO_CS)
1423                 return 0;
1424
1425         if (gpio_is_valid(spi->cs_gpio))
1426                 gpio_direction_output(spi->cs_gpio,
1427                                       spi->mode & SPI_CS_HIGH ? 0 : 1);
1428
1429         spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1430
1431         return 0;
1432 }
1433
1434 static void spi_imx_cleanup(struct spi_device *spi)
1435 {
1436 }
1437
1438 static int
1439 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1440 {
1441         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1442         int ret;
1443
1444         ret = clk_enable(spi_imx->clk_per);
1445         if (ret)
1446                 return ret;
1447
1448         ret = clk_enable(spi_imx->clk_ipg);
1449         if (ret) {
1450                 clk_disable(spi_imx->clk_per);
1451                 return ret;
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int
1458 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1459 {
1460         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1461
1462         clk_disable(spi_imx->clk_ipg);
1463         clk_disable(spi_imx->clk_per);
1464         return 0;
1465 }
1466
1467 static int spi_imx_slave_abort(struct spi_master *master)
1468 {
1469         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1470
1471         spi_imx->slave_aborted = true;
1472         complete(&spi_imx->xfer_done);
1473
1474         return 0;
1475 }
1476
1477 static int spi_imx_probe(struct platform_device *pdev)
1478 {
1479         struct device_node *np = pdev->dev.of_node;
1480         const struct of_device_id *of_id =
1481                         of_match_device(spi_imx_dt_ids, &pdev->dev);
1482         struct spi_imx_master *mxc_platform_info =
1483                         dev_get_platdata(&pdev->dev);
1484         struct spi_master *master;
1485         struct spi_imx_data *spi_imx;
1486         struct resource *res;
1487         int i, ret, irq, spi_drctl;
1488         const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1489                 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1490         bool slave_mode;
1491
1492         if (!np && !mxc_platform_info) {
1493                 dev_err(&pdev->dev, "can't get the platform data\n");
1494                 return -EINVAL;
1495         }
1496
1497         slave_mode = devtype_data->has_slavemode &&
1498                         of_property_read_bool(np, "spi-slave");
1499         if (slave_mode)
1500                 master = spi_alloc_slave(&pdev->dev,
1501                                          sizeof(struct spi_imx_data));
1502         else
1503                 master = spi_alloc_master(&pdev->dev,
1504                                           sizeof(struct spi_imx_data));
1505         if (!master)
1506                 return -ENOMEM;
1507
1508         ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1509         if ((ret < 0) || (spi_drctl >= 0x3)) {
1510                 /* '11' is reserved */
1511                 spi_drctl = 0;
1512         }
1513
1514         platform_set_drvdata(pdev, master);
1515
1516         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1517         master->bus_num = np ? -1 : pdev->id;
1518
1519         spi_imx = spi_master_get_devdata(master);
1520         spi_imx->bitbang.master = master;
1521         spi_imx->dev = &pdev->dev;
1522         spi_imx->slave_mode = slave_mode;
1523
1524         spi_imx->devtype_data = devtype_data;
1525
1526         /* Get number of chip selects, either platform data or OF */
1527         if (mxc_platform_info) {
1528                 master->num_chipselect = mxc_platform_info->num_chipselect;
1529                 if (mxc_platform_info->chipselect) {
1530                         master->cs_gpios = devm_kzalloc(&master->dev,
1531                                 sizeof(int) * master->num_chipselect, GFP_KERNEL);
1532                         if (!master->cs_gpios)
1533                                 return -ENOMEM;
1534
1535                         for (i = 0; i < master->num_chipselect; i++)
1536                                 master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1537                 }
1538         } else {
1539                 u32 num_cs;
1540
1541                 if (!of_property_read_u32(np, "num-cs", &num_cs))
1542                         master->num_chipselect = num_cs;
1543                 /* If not preset, default value of 1 is used */
1544         }
1545
1546         spi_imx->bitbang.chipselect = spi_imx_chipselect;
1547         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1548         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1549         spi_imx->bitbang.master->setup = spi_imx_setup;
1550         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1551         spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1552         spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1553         spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1554         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1555                                              | SPI_NO_CS;
1556         if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1557             is_imx53_ecspi(spi_imx))
1558                 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1559
1560         spi_imx->spi_drctl = spi_drctl;
1561
1562         init_completion(&spi_imx->xfer_done);
1563
1564         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1565         spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1566         if (IS_ERR(spi_imx->base)) {
1567                 ret = PTR_ERR(spi_imx->base);
1568                 goto out_master_put;
1569         }
1570         spi_imx->base_phys = res->start;
1571
1572         irq = platform_get_irq(pdev, 0);
1573         if (irq < 0) {
1574                 ret = irq;
1575                 goto out_master_put;
1576         }
1577
1578         ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1579                                dev_name(&pdev->dev), spi_imx);
1580         if (ret) {
1581                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1582                 goto out_master_put;
1583         }
1584
1585         spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1586         if (IS_ERR(spi_imx->clk_ipg)) {
1587                 ret = PTR_ERR(spi_imx->clk_ipg);
1588                 goto out_master_put;
1589         }
1590
1591         spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1592         if (IS_ERR(spi_imx->clk_per)) {
1593                 ret = PTR_ERR(spi_imx->clk_per);
1594                 goto out_master_put;
1595         }
1596
1597         ret = clk_prepare_enable(spi_imx->clk_per);
1598         if (ret)
1599                 goto out_master_put;
1600
1601         ret = clk_prepare_enable(spi_imx->clk_ipg);
1602         if (ret)
1603                 goto out_put_per;
1604
1605         spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1606         /*
1607          * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1608          * if validated on other chips.
1609          */
1610         if (spi_imx->devtype_data->has_dmamode) {
1611                 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1612                 if (ret == -EPROBE_DEFER)
1613                         goto out_clk_put;
1614
1615                 if (ret < 0)
1616                         dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1617                                 ret);
1618         }
1619
1620         spi_imx->devtype_data->reset(spi_imx);
1621
1622         spi_imx->devtype_data->intctrl(spi_imx, 0);
1623
1624         master->dev.of_node = pdev->dev.of_node;
1625
1626         /* Request GPIO CS lines, if any */
1627         if (!spi_imx->slave_mode && master->cs_gpios) {
1628                 for (i = 0; i < master->num_chipselect; i++) {
1629                         if (!gpio_is_valid(master->cs_gpios[i]))
1630                                 continue;
1631
1632                         ret = devm_gpio_request(&pdev->dev,
1633                                                 master->cs_gpios[i],
1634                                                 DRIVER_NAME);
1635                         if (ret) {
1636                                 dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1637                                         master->cs_gpios[i]);
1638                                 goto out_spi_bitbang;
1639                         }
1640                 }
1641         }
1642
1643         ret = spi_bitbang_start(&spi_imx->bitbang);
1644         if (ret) {
1645                 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1646                 goto out_clk_put;
1647         }
1648
1649         dev_info(&pdev->dev, "probed\n");
1650
1651         clk_disable(spi_imx->clk_ipg);
1652         clk_disable(spi_imx->clk_per);
1653         return ret;
1654
1655 out_spi_bitbang:
1656         spi_bitbang_stop(&spi_imx->bitbang);
1657 out_clk_put:
1658         clk_disable_unprepare(spi_imx->clk_ipg);
1659 out_put_per:
1660         clk_disable_unprepare(spi_imx->clk_per);
1661 out_master_put:
1662         spi_master_put(master);
1663
1664         return ret;
1665 }
1666
1667 static int spi_imx_remove(struct platform_device *pdev)
1668 {
1669         struct spi_master *master = platform_get_drvdata(pdev);
1670         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1671
1672         spi_bitbang_stop(&spi_imx->bitbang);
1673
1674         writel(0, spi_imx->base + MXC_CSPICTRL);
1675         clk_unprepare(spi_imx->clk_ipg);
1676         clk_unprepare(spi_imx->clk_per);
1677         spi_imx_sdma_exit(spi_imx);
1678         spi_master_put(master);
1679
1680         return 0;
1681 }
1682
1683 static struct platform_driver spi_imx_driver = {
1684         .driver = {
1685                    .name = DRIVER_NAME,
1686                    .of_match_table = spi_imx_dt_ids,
1687                    },
1688         .id_table = spi_imx_devtype,
1689         .probe = spi_imx_probe,
1690         .remove = spi_imx_remove,
1691 };
1692 module_platform_driver(spi_imx_driver);
1693
1694 MODULE_DESCRIPTION("SPI Master Controller driver");
1695 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1696 MODULE_LICENSE("GPL");
1697 MODULE_ALIAS("platform:" DRIVER_NAME);