1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
5 #include <linux/interrupt.h>
7 #include <linux/log2.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/pm_opp.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/qcom-geni-se.h>
13 #include <linux/spi/spi.h>
14 #include <linux/spinlock.h>
16 /* SPI SE specific registers and respective register fields */
17 #define SE_SPI_CPHA 0x224
20 #define SE_SPI_LOOPBACK 0x22c
21 #define LOOPBACK_ENABLE 0x1
22 #define NORMAL_MODE 0x0
23 #define LOOPBACK_MSK GENMASK(1, 0)
25 #define SE_SPI_CPOL 0x230
28 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c
29 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
31 #define SE_SPI_DEMUX_SEL 0x250
32 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)
34 #define SE_SPI_TRANS_CFG 0x25c
35 #define CS_TOGGLE BIT(0)
37 #define SE_SPI_WORD_LEN 0x268
38 #define WORD_LEN_MSK GENMASK(9, 0)
39 #define MIN_WORD_LEN 4
41 #define SE_SPI_TX_TRANS_LEN 0x26c
42 #define SE_SPI_RX_TRANS_LEN 0x270
43 #define TRANS_LEN_MSK GENMASK(23, 0)
45 #define SE_SPI_PRE_POST_CMD_DLY 0x274
47 #define SE_SPI_DELAY_COUNTERS 0x278
48 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
49 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
50 #define SPI_CS_CLK_DELAY_SHFT 10
52 /* M_CMD OP codes for SPI */
55 #define SPI_FULL_DUPLEX 3
57 #define SPI_CS_ASSERT 8
58 #define SPI_CS_DEASSERT 9
59 #define SPI_SCK_ONLY 10
60 /* M_CMD params for SPI */
61 #define SPI_PRE_CMD_DELAY BIT(0)
62 #define TIMESTAMP_BEFORE BIT(1)
63 #define FRAGMENTATION BIT(2)
64 #define TIMESTAMP_AFTER BIT(3)
65 #define POST_CMD_DELAY BIT(4)
67 enum spi_m_cmd_opcode {
74 struct spi_geni_master {
81 unsigned long cur_speed_hz;
82 unsigned long cur_sclk_hz;
83 unsigned int cur_bits_per_word;
84 unsigned int tx_rem_bytes;
85 unsigned int rx_rem_bytes;
86 const struct spi_transfer *cur_xfer;
87 struct completion xfer_done;
88 unsigned int oversampling;
90 enum spi_m_cmd_opcode cur_mcmd;
94 static int get_spi_clk_cfg(unsigned int speed_hz,
95 struct spi_geni_master *mas,
96 unsigned int *clk_idx,
97 unsigned int *clk_div)
99 unsigned long sclk_freq;
100 unsigned int actual_hz;
103 ret = geni_se_clk_freq_match(&mas->se,
104 speed_hz * mas->oversampling,
105 clk_idx, &sclk_freq, false);
107 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
112 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
113 actual_hz = sclk_freq / (mas->oversampling * *clk_div);
115 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
116 actual_hz, sclk_freq, *clk_idx, *clk_div);
117 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
119 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
121 mas->cur_sclk_hz = sclk_freq;
126 static void handle_fifo_timeout(struct spi_master *spi,
127 struct spi_message *msg)
129 struct spi_geni_master *mas = spi_master_get_devdata(spi);
130 unsigned long time_left, flags;
131 struct geni_se *se = &mas->se;
133 spin_lock_irqsave(&mas->lock, flags);
134 reinit_completion(&mas->xfer_done);
135 mas->cur_mcmd = CMD_CANCEL;
136 geni_se_cancel_m_cmd(se);
137 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
138 spin_unlock_irqrestore(&mas->lock, flags);
139 time_left = wait_for_completion_timeout(&mas->xfer_done, HZ);
143 spin_lock_irqsave(&mas->lock, flags);
144 reinit_completion(&mas->xfer_done);
145 geni_se_abort_m_cmd(se);
146 spin_unlock_irqrestore(&mas->lock, flags);
147 time_left = wait_for_completion_timeout(&mas->xfer_done, HZ);
149 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
152 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
154 struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
155 struct spi_master *spi = dev_get_drvdata(mas->dev);
156 struct geni_se *se = &mas->se;
157 unsigned long time_left;
159 reinit_completion(&mas->xfer_done);
160 pm_runtime_get_sync(mas->dev);
161 if (!(slv->mode & SPI_CS_HIGH))
162 set_flag = !set_flag;
164 mas->cur_mcmd = CMD_CS;
166 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
168 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
170 time_left = wait_for_completion_timeout(&mas->xfer_done, HZ);
172 handle_fifo_timeout(spi, NULL);
174 pm_runtime_put(mas->dev);
177 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
178 unsigned int bits_per_word)
180 unsigned int pack_words;
181 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
182 struct geni_se *se = &mas->se;
186 * If bits_per_word isn't a byte aligned value, set the packing to be
187 * 1 SPI word per FIFO word.
189 if (!(mas->fifo_width_bits % bits_per_word))
190 pack_words = mas->fifo_width_bits / bits_per_word;
193 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
195 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK;
196 writel(word_len, se->base + SE_SPI_WORD_LEN);
199 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
200 unsigned long clk_hz)
202 u32 clk_sel, m_clk_cfg, idx, div;
203 struct geni_se *se = &mas->se;
206 if (clk_hz == mas->cur_speed_hz)
209 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
211 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
216 * SPI core clock gets configured with the requested frequency
217 * or the frequency closer to the requested frequency.
218 * For that reason requested frequency is stored in the
219 * cur_speed_hz and referred in the consecutive transfer instead
220 * of calling clk_get_rate() API.
222 mas->cur_speed_hz = clk_hz;
224 clk_sel = idx & CLK_SEL_MSK;
225 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
226 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
227 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
229 /* Set BW quota for CPU as driver supports FIFO mode only. */
230 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
231 ret = geni_icc_set_bw(se);
238 static int setup_fifo_params(struct spi_device *spi_slv,
239 struct spi_master *spi)
241 struct spi_geni_master *mas = spi_master_get_devdata(spi);
242 struct geni_se *se = &mas->se;
243 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0;
246 if (mas->last_mode != spi_slv->mode) {
247 if (spi_slv->mode & SPI_LOOP)
248 loopback_cfg = LOOPBACK_ENABLE;
250 if (spi_slv->mode & SPI_CPOL)
253 if (spi_slv->mode & SPI_CPHA)
256 if (spi_slv->mode & SPI_CS_HIGH)
257 demux_output_inv = BIT(spi_slv->chip_select);
259 demux_sel = spi_slv->chip_select;
260 mas->cur_bits_per_word = spi_slv->bits_per_word;
262 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
263 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
264 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
265 writel(cpha, se->base + SE_SPI_CPHA);
266 writel(cpol, se->base + SE_SPI_CPOL);
267 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
269 mas->last_mode = spi_slv->mode;
272 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
275 static int spi_geni_prepare_message(struct spi_master *spi,
276 struct spi_message *spi_msg)
279 struct spi_geni_master *mas = spi_master_get_devdata(spi);
281 ret = setup_fifo_params(spi_msg->spi, spi);
283 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
287 static int spi_geni_init(struct spi_geni_master *mas)
289 struct geni_se *se = &mas->se;
290 unsigned int proto, major, minor, ver;
292 pm_runtime_get_sync(mas->dev);
294 proto = geni_se_read_proto(se);
295 if (proto != GENI_SE_SPI) {
296 dev_err(mas->dev, "Invalid proto %d\n", proto);
297 pm_runtime_put(mas->dev);
300 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
302 /* Width of Tx and Rx FIFO is same */
303 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
306 * Hardware programming guide suggests to configure
307 * RX FIFO RFR level to fifo_depth-2.
309 geni_se_init(se, 0x0, mas->tx_fifo_depth - 2);
310 /* Transmit an entire FIFO worth of data per IRQ */
312 ver = geni_se_get_qup_hw_version(se);
313 major = GENI_SE_VERSION_MAJOR(ver);
314 minor = GENI_SE_VERSION_MINOR(ver);
316 if (major == 1 && minor == 0)
317 mas->oversampling = 2;
319 mas->oversampling = 1;
321 geni_se_select_mode(se, GENI_SE_FIFO);
323 pm_runtime_put(mas->dev);
327 static void setup_fifo_xfer(struct spi_transfer *xfer,
328 struct spi_geni_master *mas,
329 u16 mode, struct spi_master *spi)
333 struct geni_se *se = &mas->se;
336 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
337 if (xfer->bits_per_word != mas->cur_bits_per_word) {
338 spi_setup_word_len(mas, mode, xfer->bits_per_word);
339 mas->cur_bits_per_word = xfer->bits_per_word;
342 /* Speed and bits per word can be overridden per transfer */
343 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
347 mas->tx_rem_bytes = 0;
348 mas->rx_rem_bytes = 0;
349 if (xfer->tx_buf && xfer->rx_buf)
350 m_cmd = SPI_FULL_DUPLEX;
351 else if (xfer->tx_buf)
353 else if (xfer->rx_buf)
356 spi_tx_cfg &= ~CS_TOGGLE;
358 if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
359 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
361 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
362 len &= TRANS_LEN_MSK;
364 mas->cur_xfer = xfer;
365 if (m_cmd & SPI_TX_ONLY) {
366 mas->tx_rem_bytes = xfer->len;
367 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
370 if (m_cmd & SPI_RX_ONLY) {
371 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
372 mas->rx_rem_bytes = xfer->len;
374 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
375 mas->cur_mcmd = CMD_XFER;
376 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
379 * TX_WATERMARK_REG should be set after SPI configuration and
380 * setting up GENI SE engine, as driver starts data transfer
381 * for the watermark interrupt.
383 if (m_cmd & SPI_TX_ONLY)
384 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
387 static int spi_geni_transfer_one(struct spi_master *spi,
388 struct spi_device *slv,
389 struct spi_transfer *xfer)
391 struct spi_geni_master *mas = spi_master_get_devdata(spi);
393 /* Terminate and return success for 0 byte length transfer */
397 setup_fifo_xfer(xfer, mas, slv->mode, spi);
401 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
404 * Calculate how many bytes we'll put in each FIFO word. If the
405 * transfer words don't pack cleanly into a FIFO word we'll just put
406 * one transfer word in each FIFO word. If they do pack we'll pack 'em.
408 if (mas->fifo_width_bits % mas->cur_bits_per_word)
409 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
412 return mas->fifo_width_bits / BITS_PER_BYTE;
415 static void geni_spi_handle_tx(struct spi_geni_master *mas)
417 struct geni_se *se = &mas->se;
418 unsigned int max_bytes;
420 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
423 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
424 if (mas->tx_rem_bytes < max_bytes)
425 max_bytes = mas->tx_rem_bytes;
427 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
428 while (i < max_bytes) {
430 unsigned int bytes_to_write;
432 u8 *fifo_byte = (u8 *)&fifo_word;
434 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
435 for (j = 0; j < bytes_to_write; j++)
436 fifo_byte[j] = tx_buf[i++];
437 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
439 mas->tx_rem_bytes -= max_bytes;
440 if (!mas->tx_rem_bytes)
441 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
444 static void geni_spi_handle_rx(struct spi_geni_master *mas)
446 struct geni_se *se = &mas->se;
448 unsigned int rx_bytes;
449 unsigned int rx_last_byte_valid;
451 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
454 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
455 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
456 if (rx_fifo_status & RX_LAST) {
457 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
458 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
459 if (rx_last_byte_valid && rx_last_byte_valid < 4)
460 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
462 if (mas->rx_rem_bytes < rx_bytes)
463 rx_bytes = mas->rx_rem_bytes;
465 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
466 while (i < rx_bytes) {
468 u8 *fifo_byte = (u8 *)&fifo_word;
469 unsigned int bytes_to_read;
472 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
473 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
474 for (j = 0; j < bytes_to_read; j++)
475 rx_buf[i++] = fifo_byte[j];
477 mas->rx_rem_bytes -= rx_bytes;
480 static irqreturn_t geni_spi_isr(int irq, void *data)
482 struct spi_master *spi = data;
483 struct spi_geni_master *mas = spi_master_get_devdata(spi);
484 struct geni_se *se = &mas->se;
488 if (mas->cur_mcmd == CMD_NONE)
491 spin_lock_irqsave(&mas->lock, flags);
492 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
494 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
495 geni_spi_handle_rx(mas);
497 if (m_irq & M_TX_FIFO_WATERMARK_EN)
498 geni_spi_handle_tx(mas);
500 if (m_irq & M_CMD_DONE_EN) {
501 if (mas->cur_mcmd == CMD_XFER)
502 spi_finalize_current_transfer(spi);
503 else if (mas->cur_mcmd == CMD_CS)
504 complete(&mas->xfer_done);
505 mas->cur_mcmd = CMD_NONE;
507 * If this happens, then a CMD_DONE came before all the Tx
508 * buffer bytes were sent out. This is unusual, log this
509 * condition and disable the WM interrupt to prevent the
510 * system from stalling due an interrupt storm.
511 * If this happens when all Rx bytes haven't been received, log
513 * The only known time this can happen is if bits_per_word != 8
514 * and some registers that expect xfer lengths in num spi_words
515 * weren't written correctly.
517 if (mas->tx_rem_bytes) {
518 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
519 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
520 mas->tx_rem_bytes, mas->cur_bits_per_word);
522 if (mas->rx_rem_bytes)
523 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
524 mas->rx_rem_bytes, mas->cur_bits_per_word);
527 if ((m_irq & M_CMD_CANCEL_EN) || (m_irq & M_CMD_ABORT_EN)) {
528 mas->cur_mcmd = CMD_NONE;
529 complete(&mas->xfer_done);
532 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
533 spin_unlock_irqrestore(&mas->lock, flags);
537 static int spi_geni_probe(struct platform_device *pdev)
540 struct spi_master *spi;
541 struct spi_geni_master *mas;
544 struct device *dev = &pdev->dev;
546 irq = platform_get_irq(pdev, 0);
550 base = devm_platform_ioremap_resource(pdev, 0);
552 return PTR_ERR(base);
554 clk = devm_clk_get(dev, "se");
558 spi = spi_alloc_master(dev, sizeof(*mas));
562 platform_set_drvdata(pdev, spi);
563 mas = spi_master_get_devdata(spi);
567 mas->se.wrapper = dev_get_drvdata(dev->parent);
570 mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
571 if (IS_ERR(mas->se.opp_table))
572 return PTR_ERR(mas->se.opp_table);
573 /* OPP table is optional */
574 ret = dev_pm_opp_of_add_table(&pdev->dev);
576 mas->se.has_opp_table = true;
577 } else if (ret != -ENODEV) {
578 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
583 spi->dev.of_node = dev->of_node;
584 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
585 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
586 spi->num_chipselect = 4;
587 spi->max_speed_hz = 50000000;
588 spi->prepare_message = spi_geni_prepare_message;
589 spi->transfer_one = spi_geni_transfer_one;
590 spi->auto_runtime_pm = true;
591 spi->handle_err = handle_fifo_timeout;
592 spi->set_cs = spi_geni_set_cs;
594 init_completion(&mas->xfer_done);
595 spin_lock_init(&mas->lock);
596 pm_runtime_enable(dev);
598 ret = geni_icc_get(&mas->se, NULL);
600 goto spi_geni_probe_runtime_disable;
601 /* Set the bus quota to a reasonable value for register access */
602 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
603 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
605 ret = geni_icc_set_bw(&mas->se);
607 goto spi_geni_probe_runtime_disable;
609 ret = spi_geni_init(mas);
611 goto spi_geni_probe_runtime_disable;
613 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
615 goto spi_geni_probe_runtime_disable;
617 ret = spi_register_master(spi);
619 goto spi_geni_probe_free_irq;
622 spi_geni_probe_free_irq:
623 free_irq(mas->irq, spi);
624 spi_geni_probe_runtime_disable:
625 pm_runtime_disable(dev);
627 if (mas->se.has_opp_table)
628 dev_pm_opp_of_remove_table(&pdev->dev);
629 dev_pm_opp_put_clkname(mas->se.opp_table);
633 static int spi_geni_remove(struct platform_device *pdev)
635 struct spi_master *spi = platform_get_drvdata(pdev);
636 struct spi_geni_master *mas = spi_master_get_devdata(spi);
638 /* Unregister _before_ disabling pm_runtime() so we stop transfers */
639 spi_unregister_master(spi);
641 free_irq(mas->irq, spi);
642 pm_runtime_disable(&pdev->dev);
643 if (mas->se.has_opp_table)
644 dev_pm_opp_of_remove_table(&pdev->dev);
645 dev_pm_opp_put_clkname(mas->se.opp_table);
649 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
651 struct spi_master *spi = dev_get_drvdata(dev);
652 struct spi_geni_master *mas = spi_master_get_devdata(spi);
655 /* Drop the performance state vote */
656 dev_pm_opp_set_rate(dev, 0);
658 ret = geni_se_resources_off(&mas->se);
662 return geni_icc_disable(&mas->se);
665 static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
667 struct spi_master *spi = dev_get_drvdata(dev);
668 struct spi_geni_master *mas = spi_master_get_devdata(spi);
671 ret = geni_icc_enable(&mas->se);
675 ret = geni_se_resources_on(&mas->se);
679 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);
682 static int __maybe_unused spi_geni_suspend(struct device *dev)
684 struct spi_master *spi = dev_get_drvdata(dev);
687 ret = spi_master_suspend(spi);
691 ret = pm_runtime_force_suspend(dev);
693 spi_master_resume(spi);
698 static int __maybe_unused spi_geni_resume(struct device *dev)
700 struct spi_master *spi = dev_get_drvdata(dev);
703 ret = pm_runtime_force_resume(dev);
707 ret = spi_master_resume(spi);
709 pm_runtime_force_suspend(dev);
714 static const struct dev_pm_ops spi_geni_pm_ops = {
715 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
716 spi_geni_runtime_resume, NULL)
717 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
720 static const struct of_device_id spi_geni_dt_match[] = {
721 { .compatible = "qcom,geni-spi" },
724 MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
726 static struct platform_driver spi_geni_driver = {
727 .probe = spi_geni_probe,
728 .remove = spi_geni_remove,
731 .pm = &spi_geni_pm_ops,
732 .of_match_table = spi_geni_dt_match,
735 module_platform_driver(spi_geni_driver);
737 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
738 MODULE_LICENSE("GPL v2");