1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
5 #include <linux/interrupt.h>
7 #include <linux/log2.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/qcom-geni-se.h>
12 #include <linux/spi/spi.h>
13 #include <linux/spinlock.h>
15 /* SPI SE specific registers and respective register fields */
16 #define SE_SPI_CPHA 0x224
19 #define SE_SPI_LOOPBACK 0x22c
20 #define LOOPBACK_ENABLE 0x1
21 #define NORMAL_MODE 0x0
22 #define LOOPBACK_MSK GENMASK(1, 0)
24 #define SE_SPI_CPOL 0x230
27 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c
28 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
30 #define SE_SPI_DEMUX_SEL 0x250
31 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)
33 #define SE_SPI_TRANS_CFG 0x25c
34 #define CS_TOGGLE BIT(0)
36 #define SE_SPI_WORD_LEN 0x268
37 #define WORD_LEN_MSK GENMASK(9, 0)
38 #define MIN_WORD_LEN 4
40 #define SE_SPI_TX_TRANS_LEN 0x26c
41 #define SE_SPI_RX_TRANS_LEN 0x270
42 #define TRANS_LEN_MSK GENMASK(23, 0)
44 #define SE_SPI_PRE_POST_CMD_DLY 0x274
46 #define SE_SPI_DELAY_COUNTERS 0x278
47 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
48 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
49 #define SPI_CS_CLK_DELAY_SHFT 10
51 /* M_CMD OP codes for SPI */
55 #define SPI_CS_ASSERT 8
56 #define SPI_CS_DEASSERT 9
57 #define SPI_SCK_ONLY 10
58 /* M_CMD params for SPI */
59 #define SPI_PRE_CMD_DELAY BIT(0)
60 #define TIMESTAMP_BEFORE BIT(1)
61 #define FRAGMENTATION BIT(2)
62 #define TIMESTAMP_AFTER BIT(3)
63 #define POST_CMD_DELAY BIT(4)
65 struct spi_geni_master {
71 unsigned long cur_speed_hz;
72 unsigned int cur_bits_per_word;
73 unsigned int tx_rem_bytes;
74 unsigned int rx_rem_bytes;
75 const struct spi_transfer *cur_xfer;
76 struct completion cs_done;
77 struct completion cancel_done;
78 struct completion abort_done;
79 unsigned int oversampling;
84 static int get_spi_clk_cfg(unsigned int speed_hz,
85 struct spi_geni_master *mas,
86 unsigned int *clk_idx,
87 unsigned int *clk_div)
89 unsigned long sclk_freq;
90 unsigned int actual_hz;
91 struct geni_se *se = &mas->se;
94 ret = geni_se_clk_freq_match(&mas->se,
95 speed_hz * mas->oversampling,
96 clk_idx, &sclk_freq, false);
98 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
103 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
104 actual_hz = sclk_freq / (mas->oversampling * *clk_div);
106 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
107 actual_hz, sclk_freq, *clk_idx, *clk_div);
108 ret = clk_set_rate(se->clk, sclk_freq);
110 dev_err(mas->dev, "clk_set_rate failed %d\n", ret);
114 static void handle_fifo_timeout(struct spi_master *spi,
115 struct spi_message *msg)
117 struct spi_geni_master *mas = spi_master_get_devdata(spi);
118 unsigned long time_left;
119 struct geni_se *se = &mas->se;
121 spin_lock_irq(&mas->lock);
122 reinit_completion(&mas->cancel_done);
123 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
124 mas->cur_xfer = NULL;
125 mas->tx_rem_bytes = mas->rx_rem_bytes = 0;
126 geni_se_cancel_m_cmd(se);
127 spin_unlock_irq(&mas->lock);
129 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
133 spin_lock_irq(&mas->lock);
134 reinit_completion(&mas->abort_done);
135 geni_se_abort_m_cmd(se);
136 spin_unlock_irq(&mas->lock);
138 time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
140 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
143 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
145 struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
146 struct spi_master *spi = dev_get_drvdata(mas->dev);
147 struct geni_se *se = &mas->se;
148 unsigned long time_left;
150 pm_runtime_get_sync(mas->dev);
151 if (!(slv->mode & SPI_CS_HIGH))
152 set_flag = !set_flag;
154 spin_lock_irq(&mas->lock);
155 reinit_completion(&mas->cs_done);
157 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
159 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
160 spin_unlock_irq(&mas->lock);
162 time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
164 handle_fifo_timeout(spi, NULL);
166 pm_runtime_put(mas->dev);
169 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
170 unsigned int bits_per_word)
172 unsigned int pack_words;
173 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
174 struct geni_se *se = &mas->se;
177 word_len = readl(se->base + SE_SPI_WORD_LEN);
180 * If bits_per_word isn't a byte aligned value, set the packing to be
181 * 1 SPI word per FIFO word.
183 if (!(mas->fifo_width_bits % bits_per_word))
184 pack_words = mas->fifo_width_bits / bits_per_word;
187 word_len &= ~WORD_LEN_MSK;
188 word_len |= ((bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK);
189 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
191 writel(word_len, se->base + SE_SPI_WORD_LEN);
194 static int setup_fifo_params(struct spi_device *spi_slv,
195 struct spi_master *spi)
197 struct spi_geni_master *mas = spi_master_get_devdata(spi);
198 struct geni_se *se = &mas->se;
199 u32 loopback_cfg, cpol, cpha, demux_output_inv;
200 u32 demux_sel, clk_sel, m_clk_cfg, idx, div;
203 loopback_cfg = readl(se->base + SE_SPI_LOOPBACK);
204 cpol = readl(se->base + SE_SPI_CPOL);
205 cpha = readl(se->base + SE_SPI_CPHA);
206 demux_output_inv = 0;
207 loopback_cfg &= ~LOOPBACK_MSK;
211 if (spi_slv->mode & SPI_LOOP)
212 loopback_cfg |= LOOPBACK_ENABLE;
214 if (spi_slv->mode & SPI_CPOL)
217 if (spi_slv->mode & SPI_CPHA)
220 if (spi_slv->mode & SPI_CS_HIGH)
221 demux_output_inv = BIT(spi_slv->chip_select);
223 demux_sel = spi_slv->chip_select;
224 mas->cur_speed_hz = spi_slv->max_speed_hz;
225 mas->cur_bits_per_word = spi_slv->bits_per_word;
227 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, &idx, &div);
229 dev_err(mas->dev, "Err setting clks ret(%d) for %ld\n",
230 ret, mas->cur_speed_hz);
234 clk_sel = idx & CLK_SEL_MSK;
235 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
236 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
237 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
238 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
239 writel(cpha, se->base + SE_SPI_CPHA);
240 writel(cpol, se->base + SE_SPI_CPOL);
241 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
242 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
243 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
247 static int spi_geni_prepare_message(struct spi_master *spi,
248 struct spi_message *spi_msg)
251 struct spi_geni_master *mas = spi_master_get_devdata(spi);
252 struct geni_se *se = &mas->se;
254 geni_se_select_mode(se, GENI_SE_FIFO);
255 ret = setup_fifo_params(spi_msg->spi, spi);
257 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
261 static int spi_geni_init(struct spi_geni_master *mas)
263 struct geni_se *se = &mas->se;
264 unsigned int proto, major, minor, ver;
266 pm_runtime_get_sync(mas->dev);
268 proto = geni_se_read_proto(se);
269 if (proto != GENI_SE_SPI) {
270 dev_err(mas->dev, "Invalid proto %d\n", proto);
271 pm_runtime_put(mas->dev);
274 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
276 /* Width of Tx and Rx FIFO is same */
277 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
280 * Hardware programming guide suggests to configure
281 * RX FIFO RFR level to fifo_depth-2.
283 geni_se_init(se, mas->tx_fifo_depth / 2, mas->tx_fifo_depth - 2);
284 /* Transmit an entire FIFO worth of data per IRQ */
286 ver = geni_se_get_qup_hw_version(se);
287 major = GENI_SE_VERSION_MAJOR(ver);
288 minor = GENI_SE_VERSION_MINOR(ver);
290 if (major == 1 && minor == 0)
291 mas->oversampling = 2;
293 mas->oversampling = 1;
295 pm_runtime_put(mas->dev);
299 static void setup_fifo_xfer(struct spi_transfer *xfer,
300 struct spi_geni_master *mas,
301 u16 mode, struct spi_master *spi)
305 struct geni_se *se = &mas->se;
308 * Ensure that our interrupt handler isn't still running from some
309 * prior command before we start messing with the hardware behind
310 * its back. We don't need to _keep_ the lock here since we're only
311 * worried about racing with out interrupt handler. The SPI core
312 * already handles making sure that we're not trying to do two
313 * transfers at once or setting a chip select and doing a transfer
316 * NOTE: we actually _can't_ hold the lock here because possibly we
317 * might call clk_set_rate() which needs to be able to sleep.
319 spin_lock_irq(&mas->lock);
320 spin_unlock_irq(&mas->lock);
322 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
323 if (xfer->bits_per_word != mas->cur_bits_per_word) {
324 spi_setup_word_len(mas, mode, xfer->bits_per_word);
325 mas->cur_bits_per_word = xfer->bits_per_word;
328 /* Speed and bits per word can be overridden per transfer */
329 if (xfer->speed_hz != mas->cur_speed_hz) {
331 u32 clk_sel, m_clk_cfg;
332 unsigned int idx, div;
334 ret = get_spi_clk_cfg(xfer->speed_hz, mas, &idx, &div);
336 dev_err(mas->dev, "Err setting clks:%d\n", ret);
340 * SPI core clock gets configured with the requested frequency
341 * or the frequency closer to the requested frequency.
342 * For that reason requested frequency is stored in the
343 * cur_speed_hz and referred in the consecutive transfer instead
344 * of calling clk_get_rate() API.
346 mas->cur_speed_hz = xfer->speed_hz;
347 clk_sel = idx & CLK_SEL_MSK;
348 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
349 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
350 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
353 mas->tx_rem_bytes = 0;
354 mas->rx_rem_bytes = 0;
356 spi_tx_cfg &= ~CS_TOGGLE;
358 if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
359 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
361 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
362 len &= TRANS_LEN_MSK;
364 mas->cur_xfer = xfer;
366 m_cmd |= SPI_TX_ONLY;
367 mas->tx_rem_bytes = xfer->len;
368 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
372 m_cmd |= SPI_RX_ONLY;
373 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
374 mas->rx_rem_bytes = xfer->len;
376 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
379 * Lock around right before we start the transfer since our
380 * interrupt could come in at any time now.
382 spin_lock_irq(&mas->lock);
383 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
386 * TX_WATERMARK_REG should be set after SPI configuration and
387 * setting up GENI SE engine, as driver starts data transfer
388 * for the watermark interrupt.
390 if (m_cmd & SPI_TX_ONLY)
391 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
392 spin_unlock_irq(&mas->lock);
395 static int spi_geni_transfer_one(struct spi_master *spi,
396 struct spi_device *slv,
397 struct spi_transfer *xfer)
399 struct spi_geni_master *mas = spi_master_get_devdata(spi);
401 /* Terminate and return success for 0 byte length transfer */
405 setup_fifo_xfer(xfer, mas, slv->mode, spi);
409 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
412 * Calculate how many bytes we'll put in each FIFO word. If the
413 * transfer words don't pack cleanly into a FIFO word we'll just put
414 * one transfer word in each FIFO word. If they do pack we'll pack 'em.
416 if (mas->fifo_width_bits % mas->cur_bits_per_word)
417 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
420 return mas->fifo_width_bits / BITS_PER_BYTE;
423 static void geni_spi_handle_tx(struct spi_geni_master *mas)
425 struct geni_se *se = &mas->se;
426 unsigned int max_bytes;
428 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
431 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
432 if (mas->tx_rem_bytes < max_bytes)
433 max_bytes = mas->tx_rem_bytes;
435 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
436 while (i < max_bytes) {
438 unsigned int bytes_to_write;
440 u8 *fifo_byte = (u8 *)&fifo_word;
442 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
443 for (j = 0; j < bytes_to_write; j++)
444 fifo_byte[j] = tx_buf[i++];
445 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
447 mas->tx_rem_bytes -= max_bytes;
448 if (!mas->tx_rem_bytes)
449 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
452 static void geni_spi_handle_rx(struct spi_geni_master *mas)
454 struct geni_se *se = &mas->se;
456 unsigned int rx_bytes;
457 unsigned int rx_last_byte_valid;
459 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
462 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
463 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
464 if (rx_fifo_status & RX_LAST) {
465 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
466 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
467 if (rx_last_byte_valid && rx_last_byte_valid < 4)
468 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
470 if (mas->rx_rem_bytes < rx_bytes)
471 rx_bytes = mas->rx_rem_bytes;
473 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
474 while (i < rx_bytes) {
476 u8 *fifo_byte = (u8 *)&fifo_word;
477 unsigned int bytes_to_read;
480 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
481 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
482 for (j = 0; j < bytes_to_read; j++)
483 rx_buf[i++] = fifo_byte[j];
485 mas->rx_rem_bytes -= rx_bytes;
488 static irqreturn_t geni_spi_isr(int irq, void *data)
490 struct spi_master *spi = data;
491 struct spi_geni_master *mas = spi_master_get_devdata(spi);
492 struct geni_se *se = &mas->se;
495 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
499 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
500 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
501 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN))
502 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
504 spin_lock(&mas->lock);
506 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
507 geni_spi_handle_rx(mas);
509 if (m_irq & M_TX_FIFO_WATERMARK_EN)
510 geni_spi_handle_tx(mas);
512 if (m_irq & M_CMD_DONE_EN) {
514 spi_finalize_current_transfer(spi);
515 mas->cur_xfer = NULL;
517 complete(&mas->cs_done);
521 * If this happens, then a CMD_DONE came before all the Tx
522 * buffer bytes were sent out. This is unusual, log this
523 * condition and disable the WM interrupt to prevent the
524 * system from stalling due an interrupt storm.
525 * If this happens when all Rx bytes haven't been received, log
527 * The only known time this can happen is if bits_per_word != 8
528 * and some registers that expect xfer lengths in num spi_words
529 * weren't written correctly.
531 if (mas->tx_rem_bytes) {
532 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
533 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
534 mas->tx_rem_bytes, mas->cur_bits_per_word);
536 if (mas->rx_rem_bytes)
537 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
538 mas->rx_rem_bytes, mas->cur_bits_per_word);
541 if (m_irq & M_CMD_CANCEL_EN)
542 complete(&mas->cancel_done);
543 if (m_irq & M_CMD_ABORT_EN)
544 complete(&mas->abort_done);
547 * It's safe or a good idea to Ack all of our our interrupts at the
548 * end of the function. Specifically:
549 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and
550 * clearing Acks. Clearing at the end relies on nobody else having
551 * started a new transfer yet or else we could be clearing _their_
552 * done bit, but everyone grabs the spinlock before starting a new
554 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear
555 * to be "latched level" interrupts so it's important to clear them
556 * _after_ you've handled the condition and always safe to do so
557 * since they'll re-assert if they're still happening.
559 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
561 spin_unlock(&mas->lock);
566 static int spi_geni_probe(struct platform_device *pdev)
569 struct spi_master *spi;
570 struct spi_geni_master *mas;
573 struct device *dev = &pdev->dev;
575 irq = platform_get_irq(pdev, 0);
579 base = devm_platform_ioremap_resource(pdev, 0);
581 return PTR_ERR(base);
583 clk = devm_clk_get(dev, "se");
587 spi = spi_alloc_master(dev, sizeof(*mas));
591 platform_set_drvdata(pdev, spi);
592 mas = spi_master_get_devdata(spi);
596 mas->se.wrapper = dev_get_drvdata(dev->parent);
601 spi->dev.of_node = dev->of_node;
602 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
603 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
604 spi->num_chipselect = 4;
605 spi->max_speed_hz = 50000000;
606 spi->prepare_message = spi_geni_prepare_message;
607 spi->transfer_one = spi_geni_transfer_one;
608 spi->auto_runtime_pm = true;
609 spi->handle_err = handle_fifo_timeout;
610 spi->set_cs = spi_geni_set_cs;
612 init_completion(&mas->cs_done);
613 init_completion(&mas->cancel_done);
614 init_completion(&mas->abort_done);
615 spin_lock_init(&mas->lock);
616 pm_runtime_enable(dev);
618 ret = spi_geni_init(mas);
620 goto spi_geni_probe_runtime_disable;
622 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
624 goto spi_geni_probe_runtime_disable;
626 ret = spi_register_master(spi);
628 goto spi_geni_probe_free_irq;
631 spi_geni_probe_free_irq:
632 free_irq(mas->irq, spi);
633 spi_geni_probe_runtime_disable:
634 pm_runtime_disable(dev);
639 static int spi_geni_remove(struct platform_device *pdev)
641 struct spi_master *spi = platform_get_drvdata(pdev);
642 struct spi_geni_master *mas = spi_master_get_devdata(spi);
644 /* Unregister _before_ disabling pm_runtime() so we stop transfers */
645 spi_unregister_master(spi);
647 free_irq(mas->irq, spi);
648 pm_runtime_disable(&pdev->dev);
652 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
654 struct spi_master *spi = dev_get_drvdata(dev);
655 struct spi_geni_master *mas = spi_master_get_devdata(spi);
657 return geni_se_resources_off(&mas->se);
660 static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
662 struct spi_master *spi = dev_get_drvdata(dev);
663 struct spi_geni_master *mas = spi_master_get_devdata(spi);
665 return geni_se_resources_on(&mas->se);
668 static int __maybe_unused spi_geni_suspend(struct device *dev)
670 struct spi_master *spi = dev_get_drvdata(dev);
673 ret = spi_master_suspend(spi);
677 ret = pm_runtime_force_suspend(dev);
679 spi_master_resume(spi);
684 static int __maybe_unused spi_geni_resume(struct device *dev)
686 struct spi_master *spi = dev_get_drvdata(dev);
689 ret = pm_runtime_force_resume(dev);
693 ret = spi_master_resume(spi);
695 pm_runtime_force_suspend(dev);
700 static const struct dev_pm_ops spi_geni_pm_ops = {
701 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
702 spi_geni_runtime_resume, NULL)
703 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
706 static const struct of_device_id spi_geni_dt_match[] = {
707 { .compatible = "qcom,geni-spi" },
710 MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
712 static struct platform_driver spi_geni_driver = {
713 .probe = spi_geni_probe,
714 .remove = spi_geni_remove,
717 .pm = &spi_geni_pm_ops,
718 .of_match_table = spi_geni_dt_match,
721 module_platform_driver(spi_geni_driver);
723 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
724 MODULE_LICENSE("GPL v2");