2 * Freescale SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
7 * Copyright 2010 Freescale Semiconductor, Inc.
9 * CPM SPI and QE buffer descriptors mode support:
10 * Copyright (c) 2009 MontaVista Software, Inc.
11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #ifndef __SPI_FSL_SPI_H__
20 #define __SPI_FSL_SPI_H__
22 /* SPI Controller registers */
33 /* SPI Controller mode register definitions */
34 #define SPMODE_LOOP (1 << 30)
35 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
36 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
37 #define SPMODE_DIV16 (1 << 27)
38 #define SPMODE_REV (1 << 26)
39 #define SPMODE_MS (1 << 25)
40 #define SPMODE_ENABLE (1 << 24)
41 #define SPMODE_LEN(x) ((x) << 20)
42 #define SPMODE_PM(x) ((x) << 16)
43 #define SPMODE_OP (1 << 14)
44 #define SPMODE_CG(x) ((x) << 7)
47 * Default for SPI Mode:
48 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
50 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
51 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
53 /* SPIE register values */
54 #define SPIE_NE 0x00000200 /* Not empty */
55 #define SPIE_NF 0x00000100 /* Not full */
57 /* SPIM register values */
58 #define SPIM_NE 0x00000200 /* Not empty */
59 #define SPIM_NF 0x00000100 /* Not full */
61 #endif /* __SPI_FSL_SPI_H__ */