drivers/spi/spi-fsl-lpspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Freescale i.MX7ULP LPSPI driver
   4 //
   5 // Copyright 2016 Freescale Semiconductor, Inc.
   6 // Copyright 2018 NXP Semiconductors
   7
   8 #include <linux/clk.h>
   9 #include <linux/completion.h>
  10 #include <linux/delay.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/gpio.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_gpio.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/platform_data/dma-imx.h>
  26 #include <linux/platform_data/spi-imx.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/slab.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/spi/spi_bitbang.h>
  31 #include <linux/types.h>
  32
  33 #define DRIVER_NAME "fsl_lpspi"
  34
  35 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
  36
  37 /* The maximum bytes that edma can transfer once.*/
  38 #define FSL_LPSPI_MAX_EDMA_BYTES  ((1 << 15) - 1)
  39
  40 /* i.MX7ULP LPSPI registers */
  41 #define IMX7ULP_VERID   0x0
  42 #define IMX7ULP_PARAM   0x4
  43 #define IMX7ULP_CR      0x10
  44 #define IMX7ULP_SR      0x14
  45 #define IMX7ULP_IER     0x18
  46 #define IMX7ULP_DER     0x1c
  47 #define IMX7ULP_CFGR0   0x20
  48 #define IMX7ULP_CFGR1   0x24
  49 #define IMX7ULP_DMR0    0x30
  50 #define IMX7ULP_DMR1    0x34
  51 #define IMX7ULP_CCR     0x40
  52 #define IMX7ULP_FCR     0x58
  53 #define IMX7ULP_FSR     0x5c
  54 #define IMX7ULP_TCR     0x60
  55 #define IMX7ULP_TDR     0x64
  56 #define IMX7ULP_RSR     0x70
  57 #define IMX7ULP_RDR     0x74
  58
  59 /* General control register field define */
  60 #define CR_RRF          BIT(9)
  61 #define CR_RTF          BIT(8)
  62 #define CR_RST          BIT(1)
  63 #define CR_MEN          BIT(0)
  64 #define SR_MBF          BIT(24)
  65 #define SR_TCF          BIT(10)
  66 #define SR_FCF          BIT(9)
  67 #define SR_RDF          BIT(1)
  68 #define SR_TDF          BIT(0)
  69 #define IER_TCIE        BIT(10)
  70 #define IER_FCIE        BIT(9)
  71 #define IER_RDIE        BIT(1)
  72 #define IER_TDIE        BIT(0)
  73 #define DER_RDDE        BIT(1)
  74 #define DER_TDDE        BIT(0)
  75 #define CFGR1_PCSCFG    BIT(27)
  76 #define CFGR1_PINCFG    (BIT(24)|BIT(25))
  77 #define CFGR1_PCSPOL    BIT(8)
  78 #define CFGR1_NOSTALL   BIT(3)
  79 #define CFGR1_MASTER    BIT(0)
  80 #define FSR_RXCOUNT     (BIT(16)|BIT(17)|BIT(18))
  81 #define RSR_RXEMPTY     BIT(1)
  82 #define TCR_CPOL        BIT(31)
  83 #define TCR_CPHA        BIT(30)
  84 #define TCR_CONT        BIT(21)
  85 #define TCR_CONTC       BIT(20)
  86 #define TCR_RXMSK       BIT(19)
  87 #define TCR_TXMSK       BIT(18)
  88
  89 static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};
  90
  91 struct lpspi_config {
  92         u8 bpw;
  93         u8 chip_select;
  94         u8 prescale;
  95         u16 mode;
  96         u32 speed_hz;
  97 };
  98
  99 struct fsl_lpspi_data {
 100         struct device *dev;
 101         void __iomem *base;
 102         unsigned long base_phys;
 103         struct clk *clk_ipg;
 104         struct clk *clk_per;
 105         bool is_slave;
 106         bool is_first_byte;
 107
 108         void *rx_buf;
 109         const void *tx_buf;
 110         void (*tx)(struct fsl_lpspi_data *);
 111         void (*rx)(struct fsl_lpspi_data *);
 112
 113         u32 remain;
 114         u8 watermark;
 115         u8 txfifosize;
 116         u8 rxfifosize;
 117
 118         struct lpspi_config config;
 119         struct completion xfer_done;
 120
 121         bool slave_aborted;
 122
 123         /* DMA */
 124         bool usedma;
 125         struct completion dma_rx_completion;
 126         struct completion dma_tx_completion;
 127
 128         int chipselect[0];
 129 };
 130
 131 static const struct of_device_id fsl_lpspi_dt_ids[] = {
 132         { .compatible = "fsl,imx7ulp-spi", },
 133         { /* sentinel */ }
 134 };
 135 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
 136
 137 #define LPSPI_BUF_RX(type)                                              \
 138 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 139 {                                                                       \
 140         unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR);        \
 141                                                                         \
 142         if (fsl_lpspi->rx_buf) {                                        \
 143                 *(type *)fsl_lpspi->rx_buf = val;                       \
 144                 fsl_lpspi->rx_buf += sizeof(type);                      \
 145         }                                                               \
 146 }
 147
 148 #define LPSPI_BUF_TX(type)                                              \
 149 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 150 {                                                                       \
 151         type val = 0;                                                   \
 152                                                                         \
 153         if (fsl_lpspi->tx_buf) {                                        \
 154                 val = *(type *)fsl_lpspi->tx_buf;                       \
 155                 fsl_lpspi->tx_buf += sizeof(type);                      \
 156         }                                                               \
 157                                                                         \
 158         fsl_lpspi->remain -= sizeof(type);                              \
 159         writel(val, fsl_lpspi->base + IMX7ULP_TDR);                     \
 160 }
 161
 162 LPSPI_BUF_RX(u8)
 163 LPSPI_BUF_TX(u8)
 164 LPSPI_BUF_RX(u16)
 165 LPSPI_BUF_TX(u16)
 166 LPSPI_BUF_RX(u32)
 167 LPSPI_BUF_TX(u32)
 168
 169 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
 170                               unsigned int enable)
 171 {
 172         writel(enable, fsl_lpspi->base + IMX7ULP_IER);
 173 }
 174
 175 static int fsl_lpspi_bytes_per_word(const int bpw)
 176 {
 177         return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
 178 }
 179
 180 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
 181                               struct spi_device *spi,
 182                               struct spi_transfer *transfer)
 183 {
 184         unsigned int bytes_per_word;
 185
 186         if (!controller->dma_rx)
 187                 return false;
 188
 189         bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
 190
 191         switch (bytes_per_word)
 192         {
 193                 case 1:
 194                 case 2:
 195                 case 4:
 196                         break;
 197                 default:
 198                         return false;
 199         }
 200
 201         return true;
 202 }
 203
 204 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
 205 {
 206         struct fsl_lpspi_data *fsl_lpspi =
 207                                 spi_controller_get_devdata(controller);
 208         int ret;
 209
 210         ret = pm_runtime_get_sync(fsl_lpspi->dev);
 211         if (ret < 0) {
 212                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 213                 return ret;
 214         }
 215
 216         return 0;
 217 }
 218
 219 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
 220 {
 221         struct fsl_lpspi_data *fsl_lpspi =
 222                                 spi_controller_get_devdata(controller);
 223
 224         pm_runtime_mark_last_busy(fsl_lpspi->dev);
 225         pm_runtime_put_autosuspend(fsl_lpspi->dev);
 226
 227         return 0;
 228 }
 229
 230 static int fsl_lpspi_prepare_message(struct spi_controller *controller,
 231                                      struct spi_message *msg)
 232 {
 233         struct fsl_lpspi_data *fsl_lpspi =
 234                                         spi_controller_get_devdata(controller);
 235         struct spi_device *spi = msg->spi;
 236         int gpio = fsl_lpspi->chipselect[spi->chip_select];
 237
 238         if (gpio_is_valid(gpio))
 239                 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 240
 241         return 0;
 242 }
 243
 244 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 245 {
 246         u8 txfifo_cnt;
 247         u32 temp;
 248
 249         txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
 250
 251         while (txfifo_cnt < fsl_lpspi->txfifosize) {
 252                 if (!fsl_lpspi->remain)
 253                         break;
 254                 fsl_lpspi->tx(fsl_lpspi);
 255                 txfifo_cnt++;
 256         }
 257
 258         if (txfifo_cnt < fsl_lpspi->txfifosize) {
 259                 if (!fsl_lpspi->is_slave) {
 260                         temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
 261                         temp &= ~TCR_CONTC;
 262                         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 263                 }
 264
 265                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 266         } else
 267                 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
 268 }
 269
 270 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 271 {
 272         while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
 273                 fsl_lpspi->rx(fsl_lpspi);
 274 }
 275
 276 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
 277 {
 278         u32 temp = 0;
 279
 280         temp |= fsl_lpspi->config.bpw - 1;
 281         temp |= (fsl_lpspi->config.mode & 0x3) << 30;
 282         if (!fsl_lpspi->is_slave) {
 283                 temp |= fsl_lpspi->config.prescale << 27;
 284                 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
 285
 286                 /*
 287                  * Set TCR_CONT will keep SS asserted after current transfer.
 288                  * For the first transfer, clear TCR_CONTC to assert SS.
 289                  * For subsequent transfer, set TCR_CONTC to keep SS asserted.
 290                  */
 291                 if (!fsl_lpspi->usedma) {
 292                         temp |= TCR_CONT;
 293                         if (fsl_lpspi->is_first_byte)
 294                                 temp &= ~TCR_CONTC;
 295                         else
 296                                 temp |= TCR_CONTC;
 297                 }
 298         }
 299         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 300
 301         dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
 302 }
 303
 304 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
 305 {
 306         u32 temp;
 307
 308         if (!fsl_lpspi->usedma)
 309                 temp = fsl_lpspi->watermark >> 1 |
 310                        (fsl_lpspi->watermark >> 1) << 16;
 311         else
 312                 temp = fsl_lpspi->watermark >> 1;
 313
 314         writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
 315
 316         dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
 317 }
 318
 319 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
 320 {
 321         struct lpspi_config config = fsl_lpspi->config;
 322         unsigned int perclk_rate, scldiv;
 323         u8 prescale;
 324
 325         perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
 326
 327         if (config.speed_hz > perclk_rate / 2) {
 328                 dev_err(fsl_lpspi->dev,
 329                       "per-clk should be at least two times of transfer speed");
 330                 return -EINVAL;
 331         }
 332
 333         for (prescale = 0; prescale < 8; prescale++) {
 334                 scldiv = perclk_rate /
 335                          (clkdivs[prescale] * config.speed_hz) - 2;
 336                 if (scldiv < 256) {
 337                         fsl_lpspi->config.prescale = prescale;
 338                         break;
 339                 }
 340         }
 341
 342         if (prescale == 8 && scldiv >= 256)
 343                 return -EINVAL;
 344
 345         writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
 346                                         fsl_lpspi->base + IMX7ULP_CCR);
 347
 348         dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
 349                 perclk_rate, config.speed_hz, prescale, scldiv);
 350
 351         return 0;
 352 }
 353
 354 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
 355 {
 356         int ret;
 357         enum dma_slave_buswidth buswidth;
 358         struct dma_slave_config rx = {}, tx = {};
 359         struct fsl_lpspi_data *fsl_lpspi =
 360                                 spi_controller_get_devdata(controller);
 361
 362         switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
 363         case 4:
 364                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
 365                 break;
 366         case 2:
 367                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
 368                 break;
 369         case 1:
 370                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
 371                 break;
 372         default:
 373                 return -EINVAL;
 374         }
 375
 376         tx.direction = DMA_MEM_TO_DEV;
 377         tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
 378         tx.dst_addr_width = buswidth;
 379         tx.dst_maxburst = 1;
 380         ret = dmaengine_slave_config(controller->dma_tx, &tx);
 381         if (ret) {
 382                 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
 383                         ret);
 384                 return ret;
 385         }
 386
 387         rx.direction = DMA_DEV_TO_MEM;
 388         rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
 389         rx.src_addr_width = buswidth;
 390         rx.src_maxburst = 1;
 391         ret = dmaengine_slave_config(controller->dma_rx, &rx);
 392         if (ret) {
 393                 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
 394                         ret);
 395                 return ret;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
 402 {
 403         u32 temp;
 404         int ret;
 405
 406         if (!fsl_lpspi->is_slave) {
 407                 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
 408                 if (ret)
 409                         return ret;
 410         }
 411
 412         fsl_lpspi_set_watermark(fsl_lpspi);
 413
 414         if (!fsl_lpspi->is_slave)
 415                 temp = CFGR1_MASTER;
 416         else
 417                 temp = CFGR1_PINCFG;
 418         if (fsl_lpspi->config.mode & SPI_CS_HIGH)
 419                 temp |= CFGR1_PCSPOL;
 420         writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
 421
 422         temp = readl(fsl_lpspi->base + IMX7ULP_CR);
 423         temp |= CR_RRF | CR_RTF | CR_MEN;
 424         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 425
 426         temp = 0;
 427         if (fsl_lpspi->usedma)
 428                 temp = DER_TDDE | DER_RDDE;
 429         writel(temp, fsl_lpspi->base + IMX7ULP_DER);
 430
 431         return 0;
 432 }
 433
 434 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
 435                                      struct spi_device *spi,
 436                                      struct spi_transfer *t)
 437 {
 438         struct fsl_lpspi_data *fsl_lpspi =
 439                                 spi_controller_get_devdata(spi->controller);
 440
 441         if (t == NULL)
 442                 return -EINVAL;
 443
 444         fsl_lpspi->config.mode = spi->mode;
 445         fsl_lpspi->config.bpw = t->bits_per_word;
 446         fsl_lpspi->config.speed_hz = t->speed_hz;
 447         fsl_lpspi->config.chip_select = spi->chip_select;
 448
 449         if (!fsl_lpspi->config.speed_hz)
 450                 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
 451         if (!fsl_lpspi->config.bpw)
 452                 fsl_lpspi->config.bpw = spi->bits_per_word;
 453
 454         /* Initialize the functions for transfer */
 455         if (fsl_lpspi->config.bpw <= 8) {
 456                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
 457                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
 458         } else if (fsl_lpspi->config.bpw <= 16) {
 459                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
 460                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
 461         } else {
 462                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
 463                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
 464         }
 465
 466         if (t->len <= fsl_lpspi->txfifosize)
 467                 fsl_lpspi->watermark = t->len;
 468         else
 469                 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
 470
 471         if (fsl_lpspi_can_dma(controller, spi, t))
 472                 fsl_lpspi->usedma = 1;
 473         else
 474                 fsl_lpspi->usedma = 0;
 475
 476         return fsl_lpspi_config(fsl_lpspi);
 477 }
 478
 479 static int fsl_lpspi_slave_abort(struct spi_controller *controller)
 480 {
 481         struct fsl_lpspi_data *fsl_lpspi =
 482                                 spi_controller_get_devdata(controller);
 483
 484         fsl_lpspi->slave_aborted = true;
 485         complete(&fsl_lpspi->xfer_done);
 486         return 0;
 487 }
 488
 489 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
 490 {
 491         struct fsl_lpspi_data *fsl_lpspi =
 492                                 spi_controller_get_devdata(controller);
 493
 494         if (fsl_lpspi->is_slave) {
 495                 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
 496                         fsl_lpspi->slave_aborted) {
 497                         dev_dbg(fsl_lpspi->dev, "interrupted\n");
 498                         return -EINTR;
 499                 }
 500         } else {
 501                 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
 502                         dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
 503                         return -ETIMEDOUT;
 504                 }
 505         }
 506
 507         return 0;
 508 }
 509
 510 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
 511 {
 512         u32 temp;
 513
 514         if (!fsl_lpspi->usedma) {
 515                 /* Disable all interrupt */
 516                 fsl_lpspi_intctrl(fsl_lpspi, 0);
 517         }
 518
 519         /* W1C for all flags in SR */
 520         temp = 0x3F << 8;
 521         writel(temp, fsl_lpspi->base + IMX7ULP_SR);
 522
 523         /* Clear FIFO and disable module */
 524         temp = CR_RRF | CR_RTF;
 525         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 526
 527         return 0;
 528 }
 529
 530 static void fsl_lpspi_dma_rx_callback(void *cookie)
 531 {
 532         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 533
 534         complete(&fsl_lpspi->dma_rx_completion);
 535 }
 536
 537 static void fsl_lpspi_dma_tx_callback(void *cookie)
 538 {
 539         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 540
 541         complete(&fsl_lpspi->dma_tx_completion);
 542 }
 543
 544 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
 545                                        int size)
 546 {
 547         unsigned long timeout = 0;
 548
 549         /* Time with actual data transfer and CS change delay related to HW */
 550         timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
 551
 552         /* Add extra second for scheduler related activities */
 553         timeout += 1;
 554
 555         /* Double calculated timeout */
 556         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
 557 }
 558
 559 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
 560                                 struct fsl_lpspi_data *fsl_lpspi,
 561                                 struct spi_transfer *transfer)
 562 {
 563         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
 564         unsigned long transfer_timeout;
 565         unsigned long timeout;
 566         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
 567         int ret;
 568
 569         ret = fsl_lpspi_dma_configure(controller);
 570         if (ret)
 571                 return ret;
 572
 573         desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
 574                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
 575                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 576         if (!desc_rx)
 577                 return -EINVAL;
 578
 579         desc_rx->callback = fsl_lpspi_dma_rx_callback;
 580         desc_rx->callback_param = (void *)fsl_lpspi;
 581         dmaengine_submit(desc_rx);
 582         reinit_completion(&fsl_lpspi->dma_rx_completion);
 583         dma_async_issue_pending(controller->dma_rx);
 584
 585         desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
 586                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
 587                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 588         if (!desc_tx) {
 589                 dmaengine_terminate_all(controller->dma_tx);
 590                 return -EINVAL;
 591         }
 592
 593         desc_tx->callback = fsl_lpspi_dma_tx_callback;
 594         desc_tx->callback_param = (void *)fsl_lpspi;
 595         dmaengine_submit(desc_tx);
 596         reinit_completion(&fsl_lpspi->dma_tx_completion);
 597         dma_async_issue_pending(controller->dma_tx);
 598
 599         fsl_lpspi->slave_aborted = false;
 600
 601         if (!fsl_lpspi->is_slave) {
 602                 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
 603                                                                transfer->len);
 604
 605                 /* Wait eDMA to finish the data transfer.*/
 606                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
 607                                                       transfer_timeout);
 608                 if (!timeout) {
 609                         dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
 610                         dmaengine_terminate_all(controller->dma_tx);
 611                         dmaengine_terminate_all(controller->dma_rx);
 612                         fsl_lpspi_reset(fsl_lpspi);
 613                         return -ETIMEDOUT;
 614                 }
 615
 616                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
 617                                                       transfer_timeout);
 618                 if (!timeout) {
 619                         dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
 620                         dmaengine_terminate_all(controller->dma_tx);
 621                         dmaengine_terminate_all(controller->dma_rx);
 622                         fsl_lpspi_reset(fsl_lpspi);
 623                         return -ETIMEDOUT;
 624                 }
 625         } else {
 626                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
 627                         fsl_lpspi->slave_aborted) {
 628                         dev_dbg(fsl_lpspi->dev,
 629                                 "I/O Error in DMA TX interrupted\n");
 630                         dmaengine_terminate_all(controller->dma_tx);
 631                         dmaengine_terminate_all(controller->dma_rx);
 632                         fsl_lpspi_reset(fsl_lpspi);
 633                         return -EINTR;
 634                 }
 635
 636                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
 637                         fsl_lpspi->slave_aborted) {
 638                         dev_dbg(fsl_lpspi->dev,
 639                                 "I/O Error in DMA RX interrupted\n");
 640                         dmaengine_terminate_all(controller->dma_tx);
 641                         dmaengine_terminate_all(controller->dma_rx);
 642                         fsl_lpspi_reset(fsl_lpspi);
 643                         return -EINTR;
 644                 }
 645         }
 646
 647         fsl_lpspi_reset(fsl_lpspi);
 648
 649         return 0;
 650 }
 651
 652 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
 653 {
 654         if (controller->dma_rx) {
 655                 dma_release_channel(controller->dma_rx);
 656                 controller->dma_rx = NULL;
 657         }
 658
 659         if (controller->dma_tx) {
 660                 dma_release_channel(controller->dma_tx);
 661                 controller->dma_tx = NULL;
 662         }
 663 }
 664
 665 static int fsl_lpspi_dma_init(struct device *dev,
 666                               struct fsl_lpspi_data *fsl_lpspi,
 667                               struct spi_controller *controller)
 668 {
 669         int ret;
 670
 671         /* Prepare for TX DMA: */
 672         controller->dma_tx = dma_request_slave_channel_reason(dev, "tx");
 673         if (IS_ERR(controller->dma_tx)) {
 674                 ret = PTR_ERR(controller->dma_tx);
 675                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
 676                 controller->dma_tx = NULL;
 677                 goto err;
 678         }
 679
 680         /* Prepare for RX DMA: */
 681         controller->dma_rx = dma_request_slave_channel_reason(dev, "rx");
 682         if (IS_ERR(controller->dma_rx)) {
 683                 ret = PTR_ERR(controller->dma_rx);
 684                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
 685                 controller->dma_rx = NULL;
 686                 goto err;
 687         }
 688
 689         init_completion(&fsl_lpspi->dma_rx_completion);
 690         init_completion(&fsl_lpspi->dma_tx_completion);
 691         controller->can_dma = fsl_lpspi_can_dma;
 692         controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
 693
 694         return 0;
 695 err:
 696         fsl_lpspi_dma_exit(controller);
 697         return ret;
 698 }
 699
 700 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
 701                                   struct spi_transfer *t)
 702 {
 703         struct fsl_lpspi_data *fsl_lpspi =
 704                                 spi_controller_get_devdata(controller);
 705         int ret;
 706
 707         fsl_lpspi->tx_buf = t->tx_buf;
 708         fsl_lpspi->rx_buf = t->rx_buf;
 709         fsl_lpspi->remain = t->len;
 710
 711         reinit_completion(&fsl_lpspi->xfer_done);
 712         fsl_lpspi->slave_aborted = false;
 713
 714         fsl_lpspi_write_tx_fifo(fsl_lpspi);
 715
 716         ret = fsl_lpspi_wait_for_completion(controller);
 717         if (ret)
 718                 return ret;
 719
 720         fsl_lpspi_reset(fsl_lpspi);
 721
 722         return 0;
 723 }
 724
 725 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
 726                                   struct spi_device *spi,
 727                                   struct spi_transfer *t)
 728 {
 729         struct fsl_lpspi_data *fsl_lpspi =
 730                                         spi_controller_get_devdata(controller);
 731         int ret;
 732
 733         fsl_lpspi->is_first_byte = true;
 734         ret = fsl_lpspi_setup_transfer(controller, spi, t);
 735         if (ret < 0)
 736                 return ret;
 737
 738         fsl_lpspi_set_cmd(fsl_lpspi);
 739         fsl_lpspi->is_first_byte = false;
 740
 741         if (fsl_lpspi->usedma)
 742                 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
 743         else
 744                 ret = fsl_lpspi_pio_transfer(controller, t);
 745         if (ret < 0)
 746                 return ret;
 747
 748         return 0;
 749 }
 750
 751 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
 752 {
 753         u32 temp_SR, temp_IER;
 754         struct fsl_lpspi_data *fsl_lpspi = dev_id;
 755
 756         temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
 757         fsl_lpspi_intctrl(fsl_lpspi, 0);
 758         temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
 759
 760         fsl_lpspi_read_rx_fifo(fsl_lpspi);
 761
 762         if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
 763                 fsl_lpspi_write_tx_fifo(fsl_lpspi);
 764                 return IRQ_HANDLED;
 765         }
 766
 767         if (temp_SR & SR_MBF ||
 768             readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) {
 769                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 770                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 771                 return IRQ_HANDLED;
 772         }
 773
 774         if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
 775                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 776                         complete(&fsl_lpspi->xfer_done);
 777                 return IRQ_HANDLED;
 778         }
 779
 780         return IRQ_NONE;
 781 }
 782
 783 static int fsl_lpspi_runtime_resume(struct device *dev)
 784 {
 785         struct fsl_lpspi_data *fsl_lpspi = dev_get_drvdata(dev);
 786         int ret;
 787
 788         ret = clk_prepare_enable(fsl_lpspi->clk_per);
 789         if (ret)
 790                 return ret;
 791
 792         ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
 793         if (ret) {
 794                 clk_disable_unprepare(fsl_lpspi->clk_per);
 795                 return ret;
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int fsl_lpspi_runtime_suspend(struct device *dev)
 802 {
 803         struct fsl_lpspi_data *fsl_lpspi = dev_get_drvdata(dev);
 804
 805         clk_disable_unprepare(fsl_lpspi->clk_per);
 806         clk_disable_unprepare(fsl_lpspi->clk_ipg);
 807
 808         return 0;
 809 }
 810
 811 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
 812 {
 813         struct device *dev = fsl_lpspi->dev;
 814
 815         pm_runtime_enable(dev);
 816         pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
 817         pm_runtime_use_autosuspend(dev);
 818
 819         return 0;
 820 }
 821
 822 static int fsl_lpspi_probe(struct platform_device *pdev)
 823 {
 824         struct device_node *np = pdev->dev.of_node;
 825         struct fsl_lpspi_data *fsl_lpspi;
 826         struct spi_controller *controller;
 827         struct spi_imx_master *lpspi_platform_info =
 828                 dev_get_platdata(&pdev->dev);
 829         struct resource *res;
 830         int i, ret, irq;
 831         u32 temp;
 832
 833         if (of_property_read_bool((&pdev->dev)->of_node, "spi-slave"))
 834                 controller = spi_alloc_slave(&pdev->dev,
 835                                         sizeof(struct fsl_lpspi_data));
 836         else
 837                 controller = spi_alloc_master(&pdev->dev,
 838                                         sizeof(struct fsl_lpspi_data));
 839
 840         if (!controller)
 841                 return -ENOMEM;
 842
 843         platform_set_drvdata(pdev, controller);
 844
 845         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
 846         controller->bus_num = pdev->id;
 847
 848         fsl_lpspi = spi_controller_get_devdata(controller);
 849         fsl_lpspi->dev = &pdev->dev;
 850         dev_set_drvdata(&pdev->dev, fsl_lpspi);
 851         fsl_lpspi->is_slave = of_property_read_bool((&pdev->dev)->of_node,
 852                                                     "spi-slave");
 853
 854         if (!fsl_lpspi->is_slave) {
 855                 for (i = 0; i < controller->num_chipselect; i++) {
 856                         int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
 857
 858                         if (!gpio_is_valid(cs_gpio) && lpspi_platform_info)
 859                                 cs_gpio = lpspi_platform_info->chipselect[i];
 860
 861                         fsl_lpspi->chipselect[i] = cs_gpio;
 862                         if (!gpio_is_valid(cs_gpio))
 863                                 continue;
 864
 865                         ret = devm_gpio_request(&pdev->dev,
 866                                                 fsl_lpspi->chipselect[i],
 867                                                 DRIVER_NAME);
 868                         if (ret) {
 869                                 dev_err(&pdev->dev, "can't get cs gpios\n");
 870                                 goto out_controller_put;
 871                         }
 872                 }
 873                 controller->cs_gpios = fsl_lpspi->chipselect;
 874                 controller->prepare_message = fsl_lpspi_prepare_message;
 875         }
 876
 877         controller->transfer_one = fsl_lpspi_transfer_one;
 878         controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
 879         controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
 880         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 881         controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
 882         controller->dev.of_node = pdev->dev.of_node;
 883         controller->bus_num = pdev->id;
 884         controller->slave_abort = fsl_lpspi_slave_abort;
 885
 886         init_completion(&fsl_lpspi->xfer_done);
 887
 888         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 889         fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
 890         if (IS_ERR(fsl_lpspi->base)) {
 891                 ret = PTR_ERR(fsl_lpspi->base);
 892                 goto out_controller_put;
 893         }
 894         fsl_lpspi->base_phys = res->start;
 895
 896         irq = platform_get_irq(pdev, 0);
 897         if (irq < 0) {
 898                 ret = irq;
 899                 goto out_controller_put;
 900         }
 901
 902         ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
 903                                dev_name(&pdev->dev), fsl_lpspi);
 904         if (ret) {
 905                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
 906                 goto out_controller_put;
 907         }
 908
 909         fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
 910         if (IS_ERR(fsl_lpspi->clk_per)) {
 911                 ret = PTR_ERR(fsl_lpspi->clk_per);
 912                 goto out_controller_put;
 913         }
 914
 915         fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 916         if (IS_ERR(fsl_lpspi->clk_ipg)) {
 917                 ret = PTR_ERR(fsl_lpspi->clk_ipg);
 918                 goto out_controller_put;
 919         }
 920
 921         /* enable the clock */
 922         ret = fsl_lpspi_init_rpm(fsl_lpspi);
 923         if (ret)
 924                 goto out_controller_put;
 925
 926         ret = pm_runtime_get_sync(fsl_lpspi->dev);
 927         if (ret < 0) {
 928                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 929                 return ret;
 930         }
 931
 932         temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
 933         fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
 934         fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
 935
 936         ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
 937         if (ret == -EPROBE_DEFER)
 938                 goto out_controller_put;
 939
 940         if (ret < 0)
 941                 dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
 942
 943         ret = devm_spi_register_controller(&pdev->dev, controller);
 944         if (ret < 0) {
 945                 dev_err(&pdev->dev, "spi_register_controller error.\n");
 946                 goto out_controller_put;
 947         }
 948
 949         return 0;
 950
 951 out_controller_put:
 952         spi_controller_put(controller);
 953
 954         return ret;
 955 }
 956
 957 static int fsl_lpspi_remove(struct platform_device *pdev)
 958 {
 959         struct spi_controller *controller = platform_get_drvdata(pdev);
 960         struct fsl_lpspi_data *fsl_lpspi =
 961                                 spi_controller_get_devdata(controller);
 962
 963         pm_runtime_disable(fsl_lpspi->dev);
 964
 965         spi_master_put(controller);
 966
 967         return 0;
 968 }
 969
 970 #ifdef CONFIG_PM_SLEEP
 971 static int fsl_lpspi_suspend(struct device *dev)
 972 {
 973         int ret;
 974
 975         pinctrl_pm_select_sleep_state(dev);
 976         ret = pm_runtime_force_suspend(dev);
 977         return ret;
 978 }
 979
 980 static int fsl_lpspi_resume(struct device *dev)
 981 {
 982         int ret;
 983
 984         ret = pm_runtime_force_resume(dev);
 985         if (ret) {
 986                 dev_err(dev, "Error in resume: %d\n", ret);
 987                 return ret;
 988         }
 989
 990         pinctrl_pm_select_default_state(dev);
 991
 992         return 0;
 993 }
 994 #endif /* CONFIG_PM_SLEEP */
 995
 996 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
 997         SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
 998                                 fsl_lpspi_runtime_resume, NULL)
 999         SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
1000 };
1001
1002 static struct platform_driver fsl_lpspi_driver = {
1003         .driver = {
1004                 .name = DRIVER_NAME,
1005                 .of_match_table = fsl_lpspi_dt_ids,
1006                 .pm = &fsl_lpspi_pm_ops,
1007         },
1008         .probe = fsl_lpspi_probe,
1009         .remove = fsl_lpspi_remove,
1010 };
1011 module_platform_driver(fsl_lpspi_driver);
1012
1013 MODULE_DESCRIPTION("LPSPI Controller driver");
1014 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
1015 MODULE_LICENSE("GPL");