2 * Driver for Cirrus Logic EP93xx SPI controller.
4 * Copyright (C) 2010-2011 Mika Westerberg
6 * Explicit FIFO handling code was inspired by amba-pl022 driver.
8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
10 * For more information about the SPI controller see documentation on Cirrus
12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/clk.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dmaengine.h>
25 #include <linux/bitops.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/sched.h>
30 #include <linux/scatterlist.h>
31 #include <linux/gpio.h>
32 #include <linux/spi/spi.h>
34 #include <linux/platform_data/dma-ep93xx.h>
35 #include <linux/platform_data/spi-ep93xx.h>
38 #define SSPCR0_MODE_SHIFT 6
39 #define SSPCR0_SCR_SHIFT 8
42 #define SSPCR1_RIE BIT(0)
43 #define SSPCR1_TIE BIT(1)
44 #define SSPCR1_RORIE BIT(2)
45 #define SSPCR1_LBM BIT(3)
46 #define SSPCR1_SSE BIT(4)
47 #define SSPCR1_MS BIT(5)
48 #define SSPCR1_SOD BIT(6)
53 #define SSPSR_TFE BIT(0)
54 #define SSPSR_TNF BIT(1)
55 #define SSPSR_RNE BIT(2)
56 #define SSPSR_RFF BIT(3)
57 #define SSPSR_BSY BIT(4)
58 #define SSPCPSR 0x0010
61 #define SSPIIR_RIS BIT(0)
62 #define SSPIIR_TIS BIT(1)
63 #define SSPIIR_RORIS BIT(2)
66 /* timeout in milliseconds */
68 /* maximum depth of RX/TX FIFO */
69 #define SPI_FIFO_SIZE 8
72 * struct ep93xx_spi - EP93xx SPI controller structure
73 * @clk: clock for the controller
74 * @mmio: pointer to ioremap()'d registers
75 * @sspdr_phys: physical address of the SSPDR register
76 * @tx: current byte in transfer to transmit
77 * @rx: current byte in transfer to receive
78 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
79 * frame decreases this level and sending one frame increases it.
80 * @dma_rx: RX DMA channel
81 * @dma_tx: TX DMA channel
82 * @dma_rx_data: RX parameters passed to the DMA engine
83 * @dma_tx_data: TX parameters passed to the DMA engine
84 * @rx_sgt: sg table for RX transfers
85 * @tx_sgt: sg table for TX transfers
86 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
92 unsigned long sspdr_phys;
96 struct dma_chan *dma_rx;
97 struct dma_chan *dma_tx;
98 struct ep93xx_dma_data dma_rx_data;
99 struct ep93xx_dma_data dma_tx_data;
100 struct sg_table rx_sgt;
101 struct sg_table tx_sgt;
105 /* converts bits per word to CR0.DSS value */
106 #define bits_per_word_to_dss(bpw) ((bpw) - 1)
109 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
110 * @master: SPI master
111 * @rate: desired SPI output clock rate
112 * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
113 * @div_scr: pointer to return the scr divider
115 static int ep93xx_spi_calc_divisors(struct spi_master *master,
116 u32 rate, u8 *div_cpsr, u8 *div_scr)
118 struct ep93xx_spi *espi = spi_master_get_devdata(master);
119 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
123 * Make sure that max value is between values supported by the
126 rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
129 * Calculate divisors so that we can get speed according the
131 * rate = spi_clock_rate / (cpsr * (1 + scr))
133 * cpsr must be even number and starts from 2, scr can be any number
136 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
137 for (scr = 0; scr <= 255; scr++) {
138 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
140 *div_cpsr = (u8)cpsr;
149 static int ep93xx_spi_chip_setup(struct spi_master *master,
150 struct spi_device *spi,
151 struct spi_transfer *xfer)
153 struct ep93xx_spi *espi = spi_master_get_devdata(master);
154 u8 dss = bits_per_word_to_dss(xfer->bits_per_word);
160 err = ep93xx_spi_calc_divisors(master, xfer->speed_hz,
161 &div_cpsr, &div_scr);
165 cr0 = div_scr << SSPCR0_SCR_SHIFT;
166 cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT;
169 dev_dbg(&master->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
170 spi->mode, div_cpsr, div_scr, dss);
171 dev_dbg(&master->dev, "setup: cr0 %#x\n", cr0);
173 writel(div_cpsr, espi->mmio + SSPCPSR);
174 writel(cr0, espi->mmio + SSPCR0);
179 static void ep93xx_do_write(struct spi_master *master)
181 struct ep93xx_spi *espi = spi_master_get_devdata(master);
182 struct spi_transfer *xfer = master->cur_msg->state;
185 if (xfer->bits_per_word > 8) {
187 val = ((u16 *)xfer->tx_buf)[espi->tx];
191 val = ((u8 *)xfer->tx_buf)[espi->tx];
194 writel(val, espi->mmio + SSPDR);
197 static void ep93xx_do_read(struct spi_master *master)
199 struct ep93xx_spi *espi = spi_master_get_devdata(master);
200 struct spi_transfer *xfer = master->cur_msg->state;
203 val = readl(espi->mmio + SSPDR);
204 if (xfer->bits_per_word > 8) {
206 ((u16 *)xfer->rx_buf)[espi->rx] = val;
210 ((u8 *)xfer->rx_buf)[espi->rx] = val;
216 * ep93xx_spi_read_write() - perform next RX/TX transfer
217 * @espi: ep93xx SPI controller struct
219 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
220 * called several times, the whole transfer will be completed. Returns
221 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
223 * When this function is finished, RX FIFO should be empty and TX FIFO should be
226 static int ep93xx_spi_read_write(struct spi_master *master)
228 struct ep93xx_spi *espi = spi_master_get_devdata(master);
229 struct spi_transfer *xfer = master->cur_msg->state;
231 /* read as long as RX FIFO has frames in it */
232 while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) {
233 ep93xx_do_read(master);
237 /* write as long as TX FIFO has room */
238 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < xfer->len) {
239 ep93xx_do_write(master);
243 if (espi->rx == xfer->len)
250 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
251 * @master: SPI master
252 * @dir: DMA transfer direction
254 * Function configures the DMA, maps the buffer and prepares the DMA
255 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
256 * in case of failure.
258 static struct dma_async_tx_descriptor *
259 ep93xx_spi_dma_prepare(struct spi_master *master,
260 enum dma_transfer_direction dir)
262 struct ep93xx_spi *espi = spi_master_get_devdata(master);
263 struct spi_transfer *xfer = master->cur_msg->state;
264 struct dma_async_tx_descriptor *txd;
265 enum dma_slave_buswidth buswidth;
266 struct dma_slave_config conf;
267 struct scatterlist *sg;
268 struct sg_table *sgt;
269 struct dma_chan *chan;
270 const void *buf, *pbuf;
271 size_t len = xfer->len;
274 if (xfer->bits_per_word > 8)
275 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
277 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
279 memset(&conf, 0, sizeof(conf));
280 conf.direction = dir;
282 if (dir == DMA_DEV_TO_MEM) {
287 conf.src_addr = espi->sspdr_phys;
288 conf.src_addr_width = buswidth;
294 conf.dst_addr = espi->sspdr_phys;
295 conf.dst_addr_width = buswidth;
298 ret = dmaengine_slave_config(chan, &conf);
303 * We need to split the transfer into PAGE_SIZE'd chunks. This is
304 * because we are using @espi->zeropage to provide a zero RX buffer
305 * for the TX transfers and we have only allocated one page for that.
307 * For performance reasons we allocate a new sg_table only when
308 * needed. Otherwise we will re-use the current one. Eventually the
309 * last sg_table is released in ep93xx_spi_release_dma().
312 nents = DIV_ROUND_UP(len, PAGE_SIZE);
313 if (nents != sgt->nents) {
316 ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
322 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
323 size_t bytes = min_t(size_t, len, PAGE_SIZE);
326 sg_set_page(sg, virt_to_page(pbuf), bytes,
327 offset_in_page(pbuf));
329 sg_set_page(sg, virt_to_page(espi->zeropage),
338 dev_warn(&master->dev, "len = %zu expected 0!\n", len);
339 return ERR_PTR(-EINVAL);
342 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
344 return ERR_PTR(-ENOMEM);
346 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK);
348 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
349 return ERR_PTR(-ENOMEM);
355 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
356 * @master: SPI master
357 * @dir: DMA transfer direction
359 * Function finishes with the DMA transfer. After this, the DMA buffer is
362 static void ep93xx_spi_dma_finish(struct spi_master *master,
363 enum dma_transfer_direction dir)
365 struct ep93xx_spi *espi = spi_master_get_devdata(master);
366 struct dma_chan *chan;
367 struct sg_table *sgt;
369 if (dir == DMA_DEV_TO_MEM) {
377 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
380 static void ep93xx_spi_dma_callback(void *callback_param)
382 struct spi_master *master = callback_param;
384 ep93xx_spi_dma_finish(master, DMA_MEM_TO_DEV);
385 ep93xx_spi_dma_finish(master, DMA_DEV_TO_MEM);
387 spi_finalize_current_transfer(master);
390 static int ep93xx_spi_dma_transfer(struct spi_master *master)
392 struct ep93xx_spi *espi = spi_master_get_devdata(master);
393 struct dma_async_tx_descriptor *rxd, *txd;
395 rxd = ep93xx_spi_dma_prepare(master, DMA_DEV_TO_MEM);
397 dev_err(&master->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
401 txd = ep93xx_spi_dma_prepare(master, DMA_MEM_TO_DEV);
403 ep93xx_spi_dma_finish(master, DMA_DEV_TO_MEM);
404 dev_err(&master->dev, "DMA TX failed: %ld\n", PTR_ERR(txd));
408 /* We are ready when RX is done */
409 rxd->callback = ep93xx_spi_dma_callback;
410 rxd->callback_param = master;
412 /* Now submit both descriptors and start DMA */
413 dmaengine_submit(rxd);
414 dmaengine_submit(txd);
416 dma_async_issue_pending(espi->dma_rx);
417 dma_async_issue_pending(espi->dma_tx);
419 /* signal that we need to wait for completion */
423 static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
425 struct spi_master *master = dev_id;
426 struct ep93xx_spi *espi = spi_master_get_devdata(master);
430 * If we got ROR (receive overrun) interrupt we know that something is
431 * wrong. Just abort the message.
433 if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) {
434 /* clear the overrun interrupt */
435 writel(0, espi->mmio + SSPICR);
436 dev_warn(&master->dev,
437 "receive overrun, aborting the message\n");
438 master->cur_msg->status = -EIO;
441 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
442 * simply execute next data transfer.
444 if (ep93xx_spi_read_write(master)) {
446 * In normal case, there still is some processing left
447 * for current transfer. Let's wait for the next
455 * Current transfer is finished, either with error or with success. In
456 * any case we disable interrupts and notify the worker to handle
457 * any post-processing of the message.
459 val = readl(espi->mmio + SSPCR1);
460 val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
461 writel(val, espi->mmio + SSPCR1);
463 spi_finalize_current_transfer(master);
468 static int ep93xx_spi_transfer_one(struct spi_master *master,
469 struct spi_device *spi,
470 struct spi_transfer *xfer)
472 struct ep93xx_spi *espi = spi_master_get_devdata(master);
476 ret = ep93xx_spi_chip_setup(master, spi, xfer);
478 dev_err(&master->dev, "failed to setup chip for transfer\n");
482 master->cur_msg->state = xfer;
487 * There is no point of setting up DMA for the transfers which will
488 * fit into the FIFO and can be transferred with a single interrupt.
489 * So in these cases we will be using PIO and don't bother for DMA.
491 if (espi->dma_rx && xfer->len > SPI_FIFO_SIZE)
492 return ep93xx_spi_dma_transfer(master);
494 /* Using PIO so prime the TX FIFO and enable interrupts */
495 ep93xx_spi_read_write(master);
497 val = readl(espi->mmio + SSPCR1);
498 val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
499 writel(val, espi->mmio + SSPCR1);
501 /* signal that we need to wait for completion */
505 static int ep93xx_spi_prepare_message(struct spi_master *master,
506 struct spi_message *msg)
508 struct ep93xx_spi *espi = spi_master_get_devdata(master);
509 unsigned long timeout;
512 * Just to be sure: flush any data from RX FIFO.
514 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
515 while (readl(espi->mmio + SSPSR) & SSPSR_RNE) {
516 if (time_after(jiffies, timeout)) {
517 dev_warn(&master->dev,
518 "timeout while flushing RX FIFO\n");
521 readl(espi->mmio + SSPDR);
525 * We explicitly handle FIFO level. This way we don't have to check TX
526 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
528 espi->fifo_level = 0;
533 static int ep93xx_spi_prepare_hardware(struct spi_master *master)
535 struct ep93xx_spi *espi = spi_master_get_devdata(master);
539 ret = clk_enable(espi->clk);
543 val = readl(espi->mmio + SSPCR1);
545 writel(val, espi->mmio + SSPCR1);
550 static int ep93xx_spi_unprepare_hardware(struct spi_master *master)
552 struct ep93xx_spi *espi = spi_master_get_devdata(master);
555 val = readl(espi->mmio + SSPCR1);
557 writel(val, espi->mmio + SSPCR1);
559 clk_disable(espi->clk);
564 static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
566 if (ep93xx_dma_chan_is_m2p(chan))
569 chan->private = filter_param;
573 static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
578 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
583 dma_cap_set(DMA_SLAVE, mask);
585 espi->dma_rx_data.port = EP93XX_DMA_SSP;
586 espi->dma_rx_data.direction = DMA_DEV_TO_MEM;
587 espi->dma_rx_data.name = "ep93xx-spi-rx";
589 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
596 espi->dma_tx_data.port = EP93XX_DMA_SSP;
597 espi->dma_tx_data.direction = DMA_MEM_TO_DEV;
598 espi->dma_tx_data.name = "ep93xx-spi-tx";
600 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
604 goto fail_release_rx;
610 dma_release_channel(espi->dma_rx);
613 free_page((unsigned long)espi->zeropage);
618 static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
621 dma_release_channel(espi->dma_rx);
622 sg_free_table(&espi->rx_sgt);
625 dma_release_channel(espi->dma_tx);
626 sg_free_table(&espi->tx_sgt);
630 free_page((unsigned long)espi->zeropage);
633 static int ep93xx_spi_probe(struct platform_device *pdev)
635 struct spi_master *master;
636 struct ep93xx_spi_info *info;
637 struct ep93xx_spi *espi;
638 struct resource *res;
643 info = dev_get_platdata(&pdev->dev);
645 dev_err(&pdev->dev, "missing platform data\n");
649 irq = platform_get_irq(pdev, 0);
651 dev_err(&pdev->dev, "failed to get irq resources\n");
655 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
657 dev_err(&pdev->dev, "unable to get iomem resource\n");
661 master = spi_alloc_master(&pdev->dev, sizeof(*espi));
665 master->prepare_transfer_hardware = ep93xx_spi_prepare_hardware;
666 master->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware;
667 master->prepare_message = ep93xx_spi_prepare_message;
668 master->transfer_one = ep93xx_spi_transfer_one;
669 master->bus_num = pdev->id;
670 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
671 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
673 master->num_chipselect = info->num_chipselect;
674 master->cs_gpios = devm_kcalloc(&master->dev,
675 master->num_chipselect, sizeof(int),
677 if (!master->cs_gpios) {
679 goto fail_release_master;
682 for (i = 0; i < master->num_chipselect; i++) {
683 master->cs_gpios[i] = info->chipselect[i];
685 if (!gpio_is_valid(master->cs_gpios[i]))
688 error = devm_gpio_request_one(&pdev->dev, master->cs_gpios[i],
692 dev_err(&pdev->dev, "could not request cs gpio %d\n",
693 master->cs_gpios[i]);
694 goto fail_release_master;
698 platform_set_drvdata(pdev, master);
700 espi = spi_master_get_devdata(master);
702 espi->clk = devm_clk_get(&pdev->dev, NULL);
703 if (IS_ERR(espi->clk)) {
704 dev_err(&pdev->dev, "unable to get spi clock\n");
705 error = PTR_ERR(espi->clk);
706 goto fail_release_master;
710 * Calculate maximum and minimum supported clock rates
711 * for the controller.
713 master->max_speed_hz = clk_get_rate(espi->clk) / 2;
714 master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
716 espi->sspdr_phys = res->start + SSPDR;
718 espi->mmio = devm_ioremap_resource(&pdev->dev, res);
719 if (IS_ERR(espi->mmio)) {
720 error = PTR_ERR(espi->mmio);
721 goto fail_release_master;
724 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
725 0, "ep93xx-spi", master);
727 dev_err(&pdev->dev, "failed to request irq\n");
728 goto fail_release_master;
731 if (info->use_dma && ep93xx_spi_setup_dma(espi))
732 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
734 /* make sure that the hardware is disabled */
735 writel(0, espi->mmio + SSPCR1);
737 error = devm_spi_register_master(&pdev->dev, master);
739 dev_err(&pdev->dev, "failed to register SPI master\n");
743 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
744 (unsigned long)res->start, irq);
749 ep93xx_spi_release_dma(espi);
751 spi_master_put(master);
756 static int ep93xx_spi_remove(struct platform_device *pdev)
758 struct spi_master *master = platform_get_drvdata(pdev);
759 struct ep93xx_spi *espi = spi_master_get_devdata(master);
761 ep93xx_spi_release_dma(espi);
766 static struct platform_driver ep93xx_spi_driver = {
768 .name = "ep93xx-spi",
770 .probe = ep93xx_spi_probe,
771 .remove = ep93xx_spi_remove,
773 module_platform_driver(ep93xx_spi_driver);
775 MODULE_DESCRIPTION("EP93xx SPI Controller driver");
776 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
777 MODULE_LICENSE("GPL");
778 MODULE_ALIAS("platform:ep93xx-spi");