2 * Driver for Broadcom BCM2835 SPI Controllers
4 * Copyright (C) 2012 Chris Boot
5 * Copyright (C) 2013 Stephen Warren
6 * Copyright (C) 2015 Martin Sperl
8 * This driver is inspired by:
9 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
10 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 #include <linux/clk.h>
24 #include <linux/completion.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/dmaengine.h>
28 #include <linux/err.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
34 #include <linux/of_address.h>
35 #include <linux/of_device.h>
36 #include <linux/of_gpio.h>
37 #include <linux/of_irq.h>
38 #include <linux/spi/spi.h>
40 /* SPI register offsets */
41 #define BCM2835_SPI_CS 0x00
42 #define BCM2835_SPI_FIFO 0x04
43 #define BCM2835_SPI_CLK 0x08
44 #define BCM2835_SPI_DLEN 0x0c
45 #define BCM2835_SPI_LTOH 0x10
46 #define BCM2835_SPI_DC 0x14
49 #define BCM2835_SPI_CS_LEN_LONG 0x02000000
50 #define BCM2835_SPI_CS_DMA_LEN 0x01000000
51 #define BCM2835_SPI_CS_CSPOL2 0x00800000
52 #define BCM2835_SPI_CS_CSPOL1 0x00400000
53 #define BCM2835_SPI_CS_CSPOL0 0x00200000
54 #define BCM2835_SPI_CS_RXF 0x00100000
55 #define BCM2835_SPI_CS_RXR 0x00080000
56 #define BCM2835_SPI_CS_TXD 0x00040000
57 #define BCM2835_SPI_CS_RXD 0x00020000
58 #define BCM2835_SPI_CS_DONE 0x00010000
59 #define BCM2835_SPI_CS_LEN 0x00002000
60 #define BCM2835_SPI_CS_REN 0x00001000
61 #define BCM2835_SPI_CS_ADCS 0x00000800
62 #define BCM2835_SPI_CS_INTR 0x00000400
63 #define BCM2835_SPI_CS_INTD 0x00000200
64 #define BCM2835_SPI_CS_DMAEN 0x00000100
65 #define BCM2835_SPI_CS_TA 0x00000080
66 #define BCM2835_SPI_CS_CSPOL 0x00000040
67 #define BCM2835_SPI_CS_CLEAR_RX 0x00000020
68 #define BCM2835_SPI_CS_CLEAR_TX 0x00000010
69 #define BCM2835_SPI_CS_CPOL 0x00000008
70 #define BCM2835_SPI_CS_CPHA 0x00000004
71 #define BCM2835_SPI_CS_CS_10 0x00000002
72 #define BCM2835_SPI_CS_CS_01 0x00000001
74 #define BCM2835_SPI_FIFO_SIZE 64
75 #define BCM2835_SPI_FIFO_SIZE_3_4 48
76 #define BCM2835_SPI_POLLING_LIMIT_US 30
77 #define BCM2835_SPI_POLLING_JIFFIES 2
78 #define BCM2835_SPI_DMA_MIN_LENGTH 96
79 #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
80 | SPI_NO_CS | SPI_3WIRE)
82 #define DRV_NAME "spi-bcm2835"
85 * struct bcm2835_spi - BCM2835 SPI controller
86 * @regs: base address of register map
87 * @clk: core clock, divided to calculate serial clock
88 * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
89 * @tfr: SPI transfer currently processed
90 * @tx_buf: pointer whence next transmitted byte is read
91 * @rx_buf: pointer where next received byte is written
92 * @tx_len: remaining bytes to transmit
93 * @rx_len: remaining bytes to receive
94 * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's
95 * length is not a multiple of 4 (to overcome hardware limitation)
96 * @rx_prologue: bytes received without DMA if first RX sglist entry's
97 * length is not a multiple of 4 (to overcome hardware limitation)
98 * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry
99 * @dma_pending: whether a DMA transfer is in progress
105 struct spi_transfer *tfr;
112 unsigned int tx_spillover;
113 unsigned int dma_pending;
116 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
118 return readl(bs->regs + reg);
121 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
123 writel(val, bs->regs + reg);
126 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
130 while ((bs->rx_len) &&
131 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
132 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
134 *bs->rx_buf++ = byte;
139 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
143 while ((bs->tx_len) &&
144 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
145 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
146 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
152 * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO
153 * @bs: BCM2835 SPI controller
154 * @count: bytes to read from RX FIFO
156 * The caller must ensure that @bs->rx_len is greater than or equal to @count,
157 * that the RX FIFO contains at least @count bytes and that the DMA Enable flag
158 * in the CS register is set (such that a read from the FIFO register receives
159 * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL.
161 static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count)
169 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
171 memcpy(bs->rx_buf, &val, len);
178 * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO
179 * @bs: BCM2835 SPI controller
180 * @count: bytes to write to TX FIFO
182 * The caller must ensure that @bs->tx_len is greater than or equal to @count,
183 * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag
184 * in the CS register is set (such that a write to the FIFO register transmits
185 * 32-bit instead of just 8-bit).
187 static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count)
197 memcpy(&val, bs->tx_buf, len);
202 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
208 * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty
209 * @bs: BCM2835 SPI controller
211 * The caller must ensure that the RX FIFO can accommodate as many bytes
212 * as have been written to the TX FIFO: Transmission is halted once the
213 * RX FIFO is full, causing this function to spin forever.
215 static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs)
217 while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
222 * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO
223 * @bs: BCM2835 SPI controller
224 * @count: bytes available for reading in RX FIFO
226 static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count)
230 count = min(count, bs->rx_len);
234 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
242 * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO
243 * @bs: BCM2835 SPI controller
244 * @count: bytes available for writing in TX FIFO
246 static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count)
250 count = min(count, bs->tx_len);
254 val = bs->tx_buf ? *bs->tx_buf++ : 0;
255 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
260 static void bcm2835_spi_reset_hw(struct spi_master *master)
262 struct bcm2835_spi *bs = spi_master_get_devdata(master);
263 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
265 /* Disable SPI interrupts and transfer */
266 cs &= ~(BCM2835_SPI_CS_INTR |
267 BCM2835_SPI_CS_INTD |
268 BCM2835_SPI_CS_DMAEN |
270 /* and reset RX/TX FIFOS */
271 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
273 /* and reset the SPI_HW */
274 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
275 /* as well as DLEN */
276 bcm2835_wr(bs, BCM2835_SPI_DLEN, 0);
279 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
281 struct spi_master *master = dev_id;
282 struct bcm2835_spi *bs = spi_master_get_devdata(master);
283 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
286 * An interrupt is signaled either if DONE is set (TX FIFO empty)
287 * or if RXR is set (RX FIFO >= ¾ full).
289 if (cs & BCM2835_SPI_CS_RXF)
290 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
291 else if (cs & BCM2835_SPI_CS_RXR)
292 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4);
294 if (bs->tx_len && cs & BCM2835_SPI_CS_DONE)
295 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
297 /* Read as many bytes as possible from FIFO */
299 /* Write as many bytes as possible to FIFO */
303 /* Transfer complete - reset SPI HW */
304 bcm2835_spi_reset_hw(master);
305 /* wake up the framework */
306 complete(&master->xfer_completion);
312 static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
313 struct spi_device *spi,
314 struct spi_transfer *tfr,
315 u32 cs, bool fifo_empty)
317 struct bcm2835_spi *bs = spi_master_get_devdata(master);
320 * Enable HW block, but with interrupts still disabled.
321 * Otherwise the empty TX FIFO would immediately trigger an interrupt.
323 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
325 /* fill TX FIFO as much as possible */
327 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
330 /* enable interrupts */
331 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
332 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
334 /* signal that we need to wait for completion */
341 * this implementation has currently a few issues in so far as it does
342 * not work arrount limitations of the HW.
344 * the main one being that DMA transfers are limited to 16 bit
345 * (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN
347 * there may be a few more border-cases we may need to address as well
348 * but unfortunately this would mean splitting up the scatter-gather
349 * list making it slightly unpractical...
353 * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA
354 * @master: SPI master
356 * @bs: BCM2835 SPI controller
359 * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks.
360 * Only the final write access is permitted to transmit less than 4 bytes, the
361 * SPI controller deduces its intended size from the DLEN register.
363 * If a TX or RX sglist contains multiple entries, one per page, and the first
364 * entry starts in the middle of a page, that first entry's length may not be
365 * a multiple of 4. Subsequent entries are fine because they span an entire
366 * page, hence do have a length that's a multiple of 4.
368 * This cannot happen with kmalloc'ed buffers (which is what most clients use)
369 * because they are contiguous in physical memory and therefore not split on
370 * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed
373 * The DMA engine is incapable of combining sglist entries into a continuous
374 * stream of 4 byte chunks, it treats every entry separately: A TX entry is
375 * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX
376 * entry is rounded up by throwing away received bytes.
378 * Overcome this limitation by transferring the first few bytes without DMA:
379 * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42,
380 * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO.
381 * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with
382 * the rest of the first RX sglist entry it makes up a multiple of 4 bytes.
384 * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1,
385 * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO.
386 * Caution, the additional 4 bytes spill over to the second TX sglist entry
387 * if the length of the first is *exactly* 1.
389 * At most 6 bytes are written and at most 3 bytes read. Do we know the
390 * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH.
392 * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width
393 * by the DMA engine. Toggling the DMA Enable flag in the CS register switches
394 * the width but also garbles the FIFO's contents. The prologue must therefore
395 * be transmitted in 32-bit width to ensure that the following DMA transfer can
396 * pick up the residue in the RX FIFO in ungarbled form.
398 static void bcm2835_spi_transfer_prologue(struct spi_master *master,
399 struct spi_transfer *tfr,
400 struct bcm2835_spi *bs,
408 bs->tx_spillover = false;
410 if (!sg_is_last(&tfr->tx_sg.sgl[0]))
411 bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3;
413 if (!sg_is_last(&tfr->rx_sg.sgl[0])) {
414 bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3;
416 if (bs->rx_prologue > bs->tx_prologue) {
417 if (sg_is_last(&tfr->tx_sg.sgl[0])) {
418 bs->tx_prologue = bs->rx_prologue;
420 bs->tx_prologue += 4;
422 !(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3);
427 /* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */
428 if (!bs->tx_prologue)
431 /* Write and read RX prologue. Adjust first entry in RX sglist. */
432 if (bs->rx_prologue) {
433 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue);
434 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
435 | BCM2835_SPI_CS_DMAEN);
436 bcm2835_wr_fifo_count(bs, bs->rx_prologue);
437 bcm2835_wait_tx_fifo_empty(bs);
438 bcm2835_rd_fifo_count(bs, bs->rx_prologue);
439 bcm2835_spi_reset_hw(master);
441 dma_sync_single_for_device(master->dma_rx->device->dev,
442 sg_dma_address(&tfr->rx_sg.sgl[0]),
443 bs->rx_prologue, DMA_FROM_DEVICE);
445 sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
446 sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
450 * Write remaining TX prologue. Adjust first entry in TX sglist.
451 * Also adjust second entry if prologue spills over to it.
453 tx_remaining = bs->tx_prologue - bs->rx_prologue;
455 bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining);
456 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
457 | BCM2835_SPI_CS_DMAEN);
458 bcm2835_wr_fifo_count(bs, tx_remaining);
459 bcm2835_wait_tx_fifo_empty(bs);
460 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX);
463 if (likely(!bs->tx_spillover)) {
464 sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
465 sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
467 sg_dma_len(&tfr->tx_sg.sgl[0]) = 0;
468 sg_dma_address(&tfr->tx_sg.sgl[1]) += 4;
469 sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4;
474 * bcm2835_spi_undo_prologue() - reconstruct original sglist state
475 * @bs: BCM2835 SPI controller
477 * Undo changes which were made to an SPI transfer's sglist when transmitting
478 * the prologue. This is necessary to ensure the same memory ranges are
479 * unmapped that were originally mapped.
481 static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs)
483 struct spi_transfer *tfr = bs->tfr;
485 if (!bs->tx_prologue)
488 if (bs->rx_prologue) {
489 sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
490 sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
493 if (likely(!bs->tx_spillover)) {
494 sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
495 sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
497 sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4;
498 sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4;
499 sg_dma_len(&tfr->tx_sg.sgl[1]) += 4;
503 static void bcm2835_spi_dma_done(void *data)
505 struct spi_master *master = data;
506 struct bcm2835_spi *bs = spi_master_get_devdata(master);
508 /* reset fifo and HW */
509 bcm2835_spi_reset_hw(master);
511 /* and terminate tx-dma as we do not have an irq for it
512 * because when the rx dma will terminate and this callback
513 * is called the tx-dma must have finished - can't get to this
514 * situation otherwise...
516 if (cmpxchg(&bs->dma_pending, true, false)) {
517 dmaengine_terminate_async(master->dma_tx);
518 bcm2835_spi_undo_prologue(bs);
521 /* and mark as completed */;
522 complete(&master->xfer_completion);
525 static int bcm2835_spi_prepare_sg(struct spi_master *master,
526 struct spi_transfer *tfr,
529 struct dma_chan *chan;
530 struct scatterlist *sgl;
532 enum dma_transfer_direction dir;
535 struct dma_async_tx_descriptor *desc;
539 dir = DMA_MEM_TO_DEV;
540 chan = master->dma_tx;
541 nents = tfr->tx_sg.nents;
542 sgl = tfr->tx_sg.sgl;
543 flags = 0 /* no tx interrupt */;
546 dir = DMA_DEV_TO_MEM;
547 chan = master->dma_rx;
548 nents = tfr->rx_sg.nents;
549 sgl = tfr->rx_sg.sgl;
550 flags = DMA_PREP_INTERRUPT;
552 /* prepare the channel */
553 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
557 /* set callback for rx */
559 desc->callback = bcm2835_spi_dma_done;
560 desc->callback_param = master;
563 /* submit it to DMA-engine */
564 cookie = dmaengine_submit(desc);
566 return dma_submit_error(cookie);
569 static int bcm2835_spi_transfer_one_dma(struct spi_master *master,
570 struct spi_device *spi,
571 struct spi_transfer *tfr,
574 struct bcm2835_spi *bs = spi_master_get_devdata(master);
578 * Transfer first few bytes without DMA if length of first TX or RX
579 * sglist entry is not a multiple of 4 bytes (hardware limitation).
581 bcm2835_spi_transfer_prologue(master, tfr, bs, cs);
584 ret = bcm2835_spi_prepare_sg(master, tfr, true);
589 dma_async_issue_pending(master->dma_tx);
591 /* mark as dma pending */
594 /* set the DMA length */
595 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len);
598 bcm2835_wr(bs, BCM2835_SPI_CS,
599 cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN);
601 /* setup rx-DMA late - to run transfers while
602 * mapping of the rx buffers still takes place
603 * this saves 10us or more.
605 ret = bcm2835_spi_prepare_sg(master, tfr, false);
607 /* need to reset on errors */
608 dmaengine_terminate_sync(master->dma_tx);
609 bs->dma_pending = false;
613 /* start rx dma late */
614 dma_async_issue_pending(master->dma_rx);
616 /* wait for wakeup in framework */
620 bcm2835_spi_reset_hw(master);
621 bcm2835_spi_undo_prologue(bs);
625 static bool bcm2835_spi_can_dma(struct spi_master *master,
626 struct spi_device *spi,
627 struct spi_transfer *tfr)
629 /* we start DMA efforts only on bigger transfers */
630 if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH)
633 /* BCM2835_SPI_DLEN has defined a max transfer size as
634 * 16 bit, so max is 65535
635 * we can revisit this by using an alternative transfer
636 * method - ideally this would get done without any more
639 if (tfr->len > 65535) {
640 dev_warn_once(&spi->dev,
641 "transfer size of %d too big for dma-transfer\n",
650 static void bcm2835_dma_release(struct spi_master *master)
652 if (master->dma_tx) {
653 dmaengine_terminate_sync(master->dma_tx);
654 dma_release_channel(master->dma_tx);
655 master->dma_tx = NULL;
657 if (master->dma_rx) {
658 dmaengine_terminate_sync(master->dma_rx);
659 dma_release_channel(master->dma_rx);
660 master->dma_rx = NULL;
664 static void bcm2835_dma_init(struct spi_master *master, struct device *dev)
666 struct dma_slave_config slave_config;
668 dma_addr_t dma_reg_base;
671 /* base address in dma-space */
672 addr = of_get_address(master->dev.of_node, 0, NULL, NULL);
674 dev_err(dev, "could not get DMA-register address - not using dma mode\n");
677 dma_reg_base = be32_to_cpup(addr);
680 master->dma_tx = dma_request_slave_channel(dev, "tx");
681 if (!master->dma_tx) {
682 dev_err(dev, "no tx-dma configuration found - not using dma mode\n");
685 master->dma_rx = dma_request_slave_channel(dev, "rx");
686 if (!master->dma_rx) {
687 dev_err(dev, "no rx-dma configuration found - not using dma mode\n");
692 slave_config.direction = DMA_MEM_TO_DEV;
693 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
694 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
696 ret = dmaengine_slave_config(master->dma_tx, &slave_config);
700 slave_config.direction = DMA_DEV_TO_MEM;
701 slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
702 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
704 ret = dmaengine_slave_config(master->dma_rx, &slave_config);
708 /* all went well, so set can_dma */
709 master->can_dma = bcm2835_spi_can_dma;
710 master->max_dma_len = 65535; /* limitation by BCM2835_SPI_DLEN */
711 /* need to do TX AND RX DMA, so we need dummy buffers */
712 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
717 dev_err(dev, "issue configuring dma: %d - not using DMA mode\n",
720 bcm2835_dma_release(master);
725 static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
726 struct spi_device *spi,
727 struct spi_transfer *tfr,
729 unsigned long long xfer_time_us)
731 struct bcm2835_spi *bs = spi_master_get_devdata(master);
732 unsigned long timeout;
734 /* enable HW block without interrupts */
735 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
737 /* fill in the fifo before timeout calculations
738 * if we are interrupted here, then the data is
739 * getting transferred by the HW while we are interrupted
741 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
743 /* set the timeout */
744 timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES;
746 /* loop until finished the transfer */
748 /* fill in tx fifo with remaining data */
751 /* read from fifo as much as possible */
754 /* if there is still data pending to read
755 * then check the timeout
757 if (bs->rx_len && time_after(jiffies, timeout)) {
758 dev_dbg_ratelimited(&spi->dev,
759 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
761 bs->tx_len, bs->rx_len);
762 /* fall back to interrupt mode */
763 return bcm2835_spi_transfer_one_irq(master, spi,
768 /* Transfer complete - reset SPI HW */
769 bcm2835_spi_reset_hw(master);
770 /* and return without waiting for completion */
774 static int bcm2835_spi_transfer_one(struct spi_master *master,
775 struct spi_device *spi,
776 struct spi_transfer *tfr)
778 struct bcm2835_spi *bs = spi_master_get_devdata(master);
779 unsigned long spi_hz, clk_hz, cdiv;
780 unsigned long spi_used_hz;
781 unsigned long long xfer_time_us;
782 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
785 spi_hz = tfr->speed_hz;
786 clk_hz = clk_get_rate(bs->clk);
788 if (spi_hz >= clk_hz / 2) {
789 cdiv = 2; /* clk_hz/2 is the fastest we can go */
791 /* CDIV must be a multiple of two */
792 cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
796 cdiv = 0; /* 0 is the slowest we can go */
798 cdiv = 0; /* 0 is the slowest we can go */
800 spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
801 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
803 /* handle all the 3-wire mode */
804 if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
805 cs |= BCM2835_SPI_CS_REN;
807 cs &= ~BCM2835_SPI_CS_REN;
810 * The driver always uses software-controlled GPIO Chip Select.
811 * Set the hardware-controlled native Chip Select to an invalid
812 * value to prevent it from interfering.
814 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
816 /* set transmit buffers and length */
817 bs->tx_buf = tfr->tx_buf;
818 bs->rx_buf = tfr->rx_buf;
819 bs->tx_len = tfr->len;
820 bs->rx_len = tfr->len;
822 /* calculate the estimated time in us the transfer runs */
823 xfer_time_us = (unsigned long long)tfr->len
824 * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
826 do_div(xfer_time_us, spi_used_hz);
828 /* for short requests run polling*/
829 if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
830 return bcm2835_spi_transfer_one_poll(master, spi, tfr,
833 /* run in dma mode if conditions are right */
834 if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr))
835 return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs);
837 /* run in interrupt-mode */
838 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs, true);
841 static int bcm2835_spi_prepare_message(struct spi_master *master,
842 struct spi_message *msg)
844 struct spi_device *spi = msg->spi;
845 struct bcm2835_spi *bs = spi_master_get_devdata(master);
846 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
848 cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA);
850 if (spi->mode & SPI_CPOL)
851 cs |= BCM2835_SPI_CS_CPOL;
852 if (spi->mode & SPI_CPHA)
853 cs |= BCM2835_SPI_CS_CPHA;
855 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
860 static void bcm2835_spi_handle_err(struct spi_master *master,
861 struct spi_message *msg)
863 struct bcm2835_spi *bs = spi_master_get_devdata(master);
865 /* if an error occurred and we have an active dma, then terminate */
866 if (cmpxchg(&bs->dma_pending, true, false)) {
867 dmaengine_terminate_sync(master->dma_tx);
868 dmaengine_terminate_sync(master->dma_rx);
869 bcm2835_spi_undo_prologue(bs);
872 bcm2835_spi_reset_hw(master);
875 static int chip_match_name(struct gpio_chip *chip, void *data)
877 return !strcmp(chip->label, data);
880 static int bcm2835_spi_setup(struct spi_device *spi)
883 struct gpio_chip *chip;
885 * sanity checking the native-chipselects
887 if (spi->mode & SPI_NO_CS)
889 if (gpio_is_valid(spi->cs_gpio))
891 if (spi->chip_select > 1) {
892 /* error in the case of native CS requested with CS > 1
893 * officially there is a CS2, but it is not documented
894 * which GPIO is connected with that...
897 "setup: only two native chip-selects are supported\n");
900 /* now translate native cs to GPIO */
902 /* get the gpio chip for the base */
903 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
907 /* and calculate the real CS */
908 spi->cs_gpio = chip->base + 8 - spi->chip_select;
910 /* and set up the "mode" and level */
911 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
912 spi->chip_select, spi->cs_gpio);
914 /* set up GPIO as output and pull to the correct level */
915 err = gpio_direction_output(spi->cs_gpio,
916 (spi->mode & SPI_CS_HIGH) ? 0 : 1);
919 "could not set CS%i gpio %i as output: %i",
920 spi->chip_select, spi->cs_gpio, err);
927 static int bcm2835_spi_probe(struct platform_device *pdev)
929 struct spi_master *master;
930 struct bcm2835_spi *bs;
931 struct resource *res;
934 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
936 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
940 platform_set_drvdata(pdev, master);
942 master->mode_bits = BCM2835_SPI_MODE_BITS;
943 master->bits_per_word_mask = SPI_BPW_MASK(8);
944 master->num_chipselect = 3;
945 master->setup = bcm2835_spi_setup;
946 master->transfer_one = bcm2835_spi_transfer_one;
947 master->handle_err = bcm2835_spi_handle_err;
948 master->prepare_message = bcm2835_spi_prepare_message;
949 master->dev.of_node = pdev->dev.of_node;
951 bs = spi_master_get_devdata(master);
953 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
954 bs->regs = devm_ioremap_resource(&pdev->dev, res);
955 if (IS_ERR(bs->regs)) {
956 err = PTR_ERR(bs->regs);
960 bs->clk = devm_clk_get(&pdev->dev, NULL);
961 if (IS_ERR(bs->clk)) {
962 err = PTR_ERR(bs->clk);
963 dev_err(&pdev->dev, "could not get clk: %d\n", err);
967 bs->irq = platform_get_irq(pdev, 0);
969 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
970 err = bs->irq ? bs->irq : -ENODEV;
974 clk_prepare_enable(bs->clk);
976 bcm2835_dma_init(master, &pdev->dev);
978 /* initialise the hardware with the default polarities */
979 bcm2835_wr(bs, BCM2835_SPI_CS,
980 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
982 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
983 dev_name(&pdev->dev), master);
985 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
986 goto out_clk_disable;
989 err = devm_spi_register_master(&pdev->dev, master);
991 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
992 goto out_clk_disable;
998 clk_disable_unprepare(bs->clk);
1000 spi_master_put(master);
1004 static int bcm2835_spi_remove(struct platform_device *pdev)
1006 struct spi_master *master = platform_get_drvdata(pdev);
1007 struct bcm2835_spi *bs = spi_master_get_devdata(master);
1009 /* Clear FIFOs, and disable the HW block */
1010 bcm2835_wr(bs, BCM2835_SPI_CS,
1011 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
1013 clk_disable_unprepare(bs->clk);
1015 bcm2835_dma_release(master);
1020 static const struct of_device_id bcm2835_spi_match[] = {
1021 { .compatible = "brcm,bcm2835-spi", },
1024 MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
1026 static struct platform_driver bcm2835_spi_driver = {
1029 .of_match_table = bcm2835_spi_match,
1031 .probe = bcm2835_spi_probe,
1032 .remove = bcm2835_spi_remove,
1034 module_platform_driver(bcm2835_spi_driver);
1036 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
1037 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
1038 MODULE_LICENSE("GPL");