1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 // AMD SPI controller driver
5 // Copyright (c) 2020, Advanced Micro Devices, Inc.
7 // Author: Sanjay R Mehta <sanju.mehta@amd.com>
9 #include <linux/acpi.h>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/delay.h>
14 #include <linux/spi/spi.h>
15 #include <linux/iopoll.h>
17 #define AMD_SPI_CTRL0_REG 0x00
18 #define AMD_SPI_EXEC_CMD BIT(16)
19 #define AMD_SPI_FIFO_CLEAR BIT(20)
20 #define AMD_SPI_BUSY BIT(31)
22 #define AMD_SPI_OPCODE_REG 0x45
23 #define AMD_SPI_CMD_TRIGGER_REG 0x47
24 #define AMD_SPI_TRIGGER_CMD BIT(7)
26 #define AMD_SPI_OPCODE_MASK 0xFF
28 #define AMD_SPI_ALT_CS_REG 0x1D
29 #define AMD_SPI_ALT_CS_MASK 0x3
31 #define AMD_SPI_FIFO_BASE 0x80
32 #define AMD_SPI_TX_COUNT_REG 0x48
33 #define AMD_SPI_RX_COUNT_REG 0x4B
34 #define AMD_SPI_STATUS_REG 0x4C
36 #define AMD_SPI_FIFO_SIZE 70
37 #define AMD_SPI_MEM_SIZE 200
39 /* M_CMD OP codes for SPI */
40 #define AMD_SPI_XFER_TX 1
41 #define AMD_SPI_XFER_RX 2
43 enum amd_spi_versions {
44 AMD_SPI_V1 = 1, /* AMDI0061 */
45 AMD_SPI_V2, /* AMDI0062 */
49 void __iomem *io_remap_addr;
50 unsigned long io_base_addr;
51 enum amd_spi_versions version;
54 static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
56 return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
59 static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
61 iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
64 static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
66 u8 tmp = amd_spi_readreg8(amd_spi, idx);
68 tmp = (tmp & ~clear) | set;
69 amd_spi_writereg8(amd_spi, idx, tmp);
72 static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
74 return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
77 static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
79 iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
82 static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
84 u32 tmp = amd_spi_readreg32(amd_spi, idx);
86 tmp = (tmp & ~clear) | set;
87 amd_spi_writereg32(amd_spi, idx, tmp);
90 static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs)
92 amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK);
95 static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select)
97 amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK);
100 static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi)
102 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR);
105 static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode)
107 switch (amd_spi->version) {
109 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode,
110 AMD_SPI_OPCODE_MASK);
113 amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode);
120 static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
122 amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
125 static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
127 amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
130 static int amd_spi_busy_wait(struct amd_spi *amd_spi)
135 switch (amd_spi->version) {
137 reg = AMD_SPI_CTRL0_REG;
140 reg = AMD_SPI_STATUS_REG;
146 return readl_poll_timeout(amd_spi->io_remap_addr + reg, val,
147 !(val & AMD_SPI_BUSY), 20, 2000000);
150 static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
154 ret = amd_spi_busy_wait(amd_spi);
158 switch (amd_spi->version) {
160 /* Set ExecuteOpCode bit in the CTRL0 register */
161 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
165 /* Trigger the command execution */
166 amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG,
167 AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD);
174 static int amd_spi_master_setup(struct spi_device *spi)
176 struct amd_spi *amd_spi = spi_master_get_devdata(spi->master);
178 amd_spi_clear_fifo_ptr(amd_spi);
183 static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
184 struct spi_master *master,
185 struct spi_message *message)
187 struct spi_transfer *xfer = NULL;
192 u32 tx_len = 0, rx_len = 0;
194 list_for_each_entry(xfer, &message->transfers,
197 m_cmd = AMD_SPI_XFER_RX;
199 m_cmd = AMD_SPI_XFER_TX;
201 if (m_cmd & AMD_SPI_XFER_TX) {
202 buf = (u8 *)xfer->tx_buf;
203 tx_len = xfer->len - 1;
204 cmd_opcode = *(u8 *)xfer->tx_buf;
206 amd_spi_set_opcode(amd_spi, cmd_opcode);
208 /* Write data into the FIFO. */
209 for (i = 0; i < tx_len; i++) {
210 iowrite8(buf[i], ((u8 __iomem *)amd_spi->io_remap_addr +
211 AMD_SPI_FIFO_BASE + i));
214 amd_spi_set_tx_count(amd_spi, tx_len);
215 amd_spi_clear_fifo_ptr(amd_spi);
216 /* Execute command */
217 amd_spi_execute_opcode(amd_spi);
219 if (m_cmd & AMD_SPI_XFER_RX) {
221 * Store no. of bytes to be received from
225 buf = (u8 *)xfer->rx_buf;
226 amd_spi_set_rx_count(amd_spi, rx_len);
227 amd_spi_clear_fifo_ptr(amd_spi);
228 /* Execute command */
229 amd_spi_execute_opcode(amd_spi);
230 amd_spi_busy_wait(amd_spi);
231 /* Read data from FIFO to receive buffer */
232 for (i = 0; i < rx_len; i++)
233 buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i);
237 /* Update statistics */
238 message->actual_length = tx_len + rx_len + 1;
239 /* complete the transaction */
242 switch (amd_spi->version) {
246 amd_spi_clear_chip(amd_spi, message->spi->chip_select);
252 spi_finalize_current_message(master);
257 static int amd_spi_master_transfer(struct spi_master *master,
258 struct spi_message *msg)
260 struct amd_spi *amd_spi = spi_master_get_devdata(master);
261 struct spi_device *spi = msg->spi;
263 amd_spi_select_chip(amd_spi, spi->chip_select);
266 * Extract spi_transfers from the spi message and
267 * program the controller.
269 amd_spi_fifo_xfer(amd_spi, master, msg);
274 static size_t amd_spi_max_transfer_size(struct spi_device *spi)
276 return AMD_SPI_FIFO_SIZE;
279 static int amd_spi_probe(struct platform_device *pdev)
281 struct device *dev = &pdev->dev;
282 struct spi_master *master;
283 struct amd_spi *amd_spi;
286 /* Allocate storage for spi_master and driver private data */
287 master = spi_alloc_master(dev, sizeof(struct amd_spi));
289 dev_err(dev, "Error allocating SPI master\n");
293 amd_spi = spi_master_get_devdata(master);
294 amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
295 if (IS_ERR(amd_spi->io_remap_addr)) {
296 err = PTR_ERR(amd_spi->io_remap_addr);
297 dev_err(dev, "error %d ioremap of SPI registers failed\n", err);
298 goto err_free_master;
300 dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);
302 amd_spi->version = (enum amd_spi_versions) device_get_match_data(dev);
304 /* Initialize the spi_master fields */
306 master->num_chipselect = 4;
307 master->mode_bits = 0;
308 master->flags = SPI_MASTER_HALF_DUPLEX;
309 master->setup = amd_spi_master_setup;
310 master->transfer_one_message = amd_spi_master_transfer;
311 master->max_transfer_size = amd_spi_max_transfer_size;
312 master->max_message_size = amd_spi_max_transfer_size;
314 /* Register the controller with SPI framework */
315 err = devm_spi_register_master(dev, master);
317 dev_err(dev, "error %d registering SPI controller\n", err);
318 goto err_free_master;
324 spi_master_put(master);
330 static const struct acpi_device_id spi_acpi_match[] = {
331 { "AMDI0061", AMD_SPI_V1 },
332 { "AMDI0062", AMD_SPI_V2 },
335 MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
338 static struct platform_driver amd_spi_driver = {
341 .acpi_match_table = ACPI_PTR(spi_acpi_match),
343 .probe = amd_spi_probe,
346 module_platform_driver(amd_spi_driver);
348 MODULE_LICENSE("Dual BSD/GPL");
349 MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
350 MODULE_DESCRIPTION("AMD SPI Master Controller Driver");