drivers/spi/dw_spi.c

   1 /*
   2  * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/highmem.h>
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25
  26 #include <linux/spi/dw_spi.h>
  27 #include <linux/spi/spi.h>
  28
  29 #ifdef CONFIG_DEBUG_FS
  30 #include <linux/debugfs.h>
  31 #endif
  32
  33 #define START_STATE     ((void *)0)
  34 #define RUNNING_STATE   ((void *)1)
  35 #define DONE_STATE      ((void *)2)
  36 #define ERROR_STATE     ((void *)-1)
  37
  38 #define QUEUE_RUNNING   0
  39 #define QUEUE_STOPPED   1
  40
  41 #define MRST_SPI_DEASSERT       0
  42 #define MRST_SPI_ASSERT         1
  43
  44 /* Slave spi_dev related */
  45 struct chip_data {
  46         u16 cr0;
  47         u8 cs;                  /* chip select pin */
  48         u8 n_bytes;             /* current is a 1/2/4 byte op */
  49         u8 tmode;               /* TR/TO/RO/EEPROM */
  50         u8 type;                /* SPI/SSP/MicroWire */
  51
  52         u8 poll_mode;           /* 1 means use poll mode */
  53
  54         u32 dma_width;
  55         u32 rx_threshold;
  56         u32 tx_threshold;
  57         u8 enable_dma;
  58         u8 bits_per_word;
  59         u16 clk_div;            /* baud rate divider */
  60         u32 speed_hz;           /* baud rate */
  61         int (*write)(struct dw_spi *dws);
  62         int (*read)(struct dw_spi *dws);
  63         void (*cs_control)(u32 command);
  64 };
  65
  66 #ifdef CONFIG_DEBUG_FS
  67 static int spi_show_regs_open(struct inode *inode, struct file *file)
  68 {
  69         file->private_data = inode->i_private;
  70         return 0;
  71 }
  72
  73 #define SPI_REGS_BUFSIZE        1024
  74 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  75                                 size_t count, loff_t *ppos)
  76 {
  77         struct dw_spi *dws;
  78         char *buf;
  79         u32 len = 0;
  80         ssize_t ret;
  81
  82         dws = file->private_data;
  83
  84         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  85         if (!buf)
  86                 return 0;
  87
  88         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  89                         "MRST SPI0 registers:\n");
  90         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  91                         "=================================\n");
  92         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  93                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
  94         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  95                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
  96         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  97                         "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
  98         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  99                         "SER: \t\t0x%08x\n", dw_readl(dws, ser));
 100         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 101                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
 102         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 103                         "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
 104         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 105                         "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
 106         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 107                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
 108         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 109                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
 110         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 111                         "SR: \t\t0x%08x\n", dw_readl(dws, sr));
 112         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 113                         "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
 114         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 115                         "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
 116         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 117                         "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
 118         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 119                         "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
 120         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 121                         "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
 122         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 123                         "=================================\n");
 124
 125         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 126         kfree(buf);
 127         return ret;
 128 }
 129
 130 static const struct file_operations mrst_spi_regs_ops = {
 131         .owner          = THIS_MODULE,
 132         .open           = spi_show_regs_open,
 133         .read           = spi_show_regs,
 134         .llseek         = default_llseek,
 135 };
 136
 137 static int mrst_spi_debugfs_init(struct dw_spi *dws)
 138 {
 139         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 140         if (!dws->debugfs)
 141                 return -ENOMEM;
 142
 143         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 144                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 145         return 0;
 146 }
 147
 148 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
 149 {
 150         if (dws->debugfs)
 151                 debugfs_remove_recursive(dws->debugfs);
 152 }
 153
 154 #else
 155 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
 156 {
 157         return 0;
 158 }
 159
 160 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
 161 {
 162 }
 163 #endif /* CONFIG_DEBUG_FS */
 164
 165 static void wait_till_not_busy(struct dw_spi *dws)
 166 {
 167         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
 168
 169         while (time_before(jiffies, end)) {
 170                 if (!(dw_readw(dws, sr) & SR_BUSY))
 171                         return;
 172         }
 173         dev_err(&dws->master->dev,
 174                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
 175 }
 176
 177 static void flush(struct dw_spi *dws)
 178 {
 179         while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 180                 dw_readw(dws, dr);
 181
 182         wait_till_not_busy(dws);
 183 }
 184
 185 static void null_cs_control(u32 command)
 186 {
 187 }
 188
 189 static int null_writer(struct dw_spi *dws)
 190 {
 191         u8 n_bytes = dws->n_bytes;
 192
 193         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 194                 || (dws->tx == dws->tx_end))
 195                 return 0;
 196         dw_writew(dws, dr, 0);
 197         dws->tx += n_bytes;
 198
 199         wait_till_not_busy(dws);
 200         return 1;
 201 }
 202
 203 static int null_reader(struct dw_spi *dws)
 204 {
 205         u8 n_bytes = dws->n_bytes;
 206
 207         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 208                 && (dws->rx < dws->rx_end)) {
 209                 dw_readw(dws, dr);
 210                 dws->rx += n_bytes;
 211         }
 212         wait_till_not_busy(dws);
 213         return dws->rx == dws->rx_end;
 214 }
 215
 216 static int u8_writer(struct dw_spi *dws)
 217 {
 218         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 219                 || (dws->tx == dws->tx_end))
 220                 return 0;
 221
 222         dw_writew(dws, dr, *(u8 *)(dws->tx));
 223         ++dws->tx;
 224
 225         wait_till_not_busy(dws);
 226         return 1;
 227 }
 228
 229 static int u8_reader(struct dw_spi *dws)
 230 {
 231         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 232                 && (dws->rx < dws->rx_end)) {
 233                 *(u8 *)(dws->rx) = dw_readw(dws, dr);
 234                 ++dws->rx;
 235         }
 236
 237         wait_till_not_busy(dws);
 238         return dws->rx == dws->rx_end;
 239 }
 240
 241 static int u16_writer(struct dw_spi *dws)
 242 {
 243         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 244                 || (dws->tx == dws->tx_end))
 245                 return 0;
 246
 247         dw_writew(dws, dr, *(u16 *)(dws->tx));
 248         dws->tx += 2;
 249
 250         wait_till_not_busy(dws);
 251         return 1;
 252 }
 253
 254 static int u16_reader(struct dw_spi *dws)
 255 {
 256         u16 temp;
 257
 258         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 259                 && (dws->rx < dws->rx_end)) {
 260                 temp = dw_readw(dws, dr);
 261                 *(u16 *)(dws->rx) = temp;
 262                 dws->rx += 2;
 263         }
 264
 265         wait_till_not_busy(dws);
 266         return dws->rx == dws->rx_end;
 267 }
 268
 269 static void *next_transfer(struct dw_spi *dws)
 270 {
 271         struct spi_message *msg = dws->cur_msg;
 272         struct spi_transfer *trans = dws->cur_transfer;
 273
 274         /* Move to next transfer */
 275         if (trans->transfer_list.next != &msg->transfers) {
 276                 dws->cur_transfer =
 277                         list_entry(trans->transfer_list.next,
 278                                         struct spi_transfer,
 279                                         transfer_list);
 280                 return RUNNING_STATE;
 281         } else
 282                 return DONE_STATE;
 283 }
 284
 285 /*
 286  * Note: first step is the protocol driver prepares
 287  * a dma-capable memory, and this func just need translate
 288  * the virt addr to physical
 289  */
 290 static int map_dma_buffers(struct dw_spi *dws)
 291 {
 292         if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
 293                 || !dws->cur_chip->enable_dma)
 294                 return 0;
 295
 296         if (dws->cur_transfer->tx_dma)
 297                 dws->tx_dma = dws->cur_transfer->tx_dma;
 298
 299         if (dws->cur_transfer->rx_dma)
 300                 dws->rx_dma = dws->cur_transfer->rx_dma;
 301
 302         return 1;
 303 }
 304
 305 /* Caller already set message->status; dma and pio irqs are blocked */
 306 static void giveback(struct dw_spi *dws)
 307 {
 308         struct spi_transfer *last_transfer;
 309         unsigned long flags;
 310         struct spi_message *msg;
 311
 312         spin_lock_irqsave(&dws->lock, flags);
 313         msg = dws->cur_msg;
 314         dws->cur_msg = NULL;
 315         dws->cur_transfer = NULL;
 316         dws->prev_chip = dws->cur_chip;
 317         dws->cur_chip = NULL;
 318         dws->dma_mapped = 0;
 319         queue_work(dws->workqueue, &dws->pump_messages);
 320         spin_unlock_irqrestore(&dws->lock, flags);
 321
 322         last_transfer = list_entry(msg->transfers.prev,
 323                                         struct spi_transfer,
 324                                         transfer_list);
 325
 326         if (!last_transfer->cs_change)
 327                 dws->cs_control(MRST_SPI_DEASSERT);
 328
 329         msg->state = NULL;
 330         if (msg->complete)
 331                 msg->complete(msg->context);
 332 }
 333
 334 static void int_error_stop(struct dw_spi *dws, const char *msg)
 335 {
 336         /* Stop and reset hw */
 337         flush(dws);
 338         spi_enable_chip(dws, 0);
 339
 340         dev_err(&dws->master->dev, "%s\n", msg);
 341         dws->cur_msg->state = ERROR_STATE;
 342         tasklet_schedule(&dws->pump_transfers);
 343 }
 344
 345 static void transfer_complete(struct dw_spi *dws)
 346 {
 347         /* Update total byte transfered return count actual bytes read */
 348         dws->cur_msg->actual_length += dws->len;
 349
 350         /* Move to next transfer */
 351         dws->cur_msg->state = next_transfer(dws);
 352
 353         /* Handle end of message */
 354         if (dws->cur_msg->state == DONE_STATE) {
 355                 dws->cur_msg->status = 0;
 356                 giveback(dws);
 357         } else
 358                 tasklet_schedule(&dws->pump_transfers);
 359 }
 360
 361 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 362 {
 363         u16 irq_status, irq_mask = 0x3f;
 364         u32 int_level = dws->fifo_len / 2;
 365         u32 left;
 366
 367         irq_status = dw_readw(dws, isr) & irq_mask;
 368         /* Error handling */
 369         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 370                 dw_readw(dws, txoicr);
 371                 dw_readw(dws, rxoicr);
 372                 dw_readw(dws, rxuicr);
 373                 int_error_stop(dws, "interrupt_transfer: fifo overrun");
 374                 return IRQ_HANDLED;
 375         }
 376
 377         if (irq_status & SPI_INT_TXEI) {
 378                 spi_mask_intr(dws, SPI_INT_TXEI);
 379
 380                 left = (dws->tx_end - dws->tx) / dws->n_bytes;
 381                 left = (left > int_level) ? int_level : left;
 382
 383                 while (left--)
 384                         dws->write(dws);
 385                 dws->read(dws);
 386
 387                 /* Re-enable the IRQ if there is still data left to tx */
 388                 if (dws->tx_end > dws->tx)
 389                         spi_umask_intr(dws, SPI_INT_TXEI);
 390                 else
 391                         transfer_complete(dws);
 392         }
 393
 394         return IRQ_HANDLED;
 395 }
 396
 397 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 398 {
 399         struct dw_spi *dws = dev_id;
 400
 401         if (!dws->cur_msg) {
 402                 spi_mask_intr(dws, SPI_INT_TXEI);
 403                 /* Never fail */
 404                 return IRQ_HANDLED;
 405         }
 406
 407         return dws->transfer_handler(dws);
 408 }
 409
 410 /* Must be called inside pump_transfers() */
 411 static void poll_transfer(struct dw_spi *dws)
 412 {
 413         while (dws->write(dws))
 414                 dws->read(dws);
 415
 416         transfer_complete(dws);
 417 }
 418
 419 static void dma_transfer(struct dw_spi *dws, int cs_change)
 420 {
 421 }
 422
 423 static void pump_transfers(unsigned long data)
 424 {
 425         struct dw_spi *dws = (struct dw_spi *)data;
 426         struct spi_message *message = NULL;
 427         struct spi_transfer *transfer = NULL;
 428         struct spi_transfer *previous = NULL;
 429         struct spi_device *spi = NULL;
 430         struct chip_data *chip = NULL;
 431         u8 bits = 0;
 432         u8 imask = 0;
 433         u8 cs_change = 0;
 434         u16 txint_level = 0;
 435         u16 clk_div = 0;
 436         u32 speed = 0;
 437         u32 cr0 = 0;
 438
 439         /* Get current state information */
 440         message = dws->cur_msg;
 441         transfer = dws->cur_transfer;
 442         chip = dws->cur_chip;
 443         spi = message->spi;
 444
 445         if (unlikely(!chip->clk_div))
 446                 chip->clk_div = dws->max_freq / chip->speed_hz;
 447
 448         if (message->state == ERROR_STATE) {
 449                 message->status = -EIO;
 450                 goto early_exit;
 451         }
 452
 453         /* Handle end of message */
 454         if (message->state == DONE_STATE) {
 455                 message->status = 0;
 456                 goto early_exit;
 457         }
 458
 459         /* Delay if requested at end of transfer*/
 460         if (message->state == RUNNING_STATE) {
 461                 previous = list_entry(transfer->transfer_list.prev,
 462                                         struct spi_transfer,
 463                                         transfer_list);
 464                 if (previous->delay_usecs)
 465                         udelay(previous->delay_usecs);
 466         }
 467
 468         dws->n_bytes = chip->n_bytes;
 469         dws->dma_width = chip->dma_width;
 470         dws->cs_control = chip->cs_control;
 471
 472         dws->rx_dma = transfer->rx_dma;
 473         dws->tx_dma = transfer->tx_dma;
 474         dws->tx = (void *)transfer->tx_buf;
 475         dws->tx_end = dws->tx + transfer->len;
 476         dws->rx = transfer->rx_buf;
 477         dws->rx_end = dws->rx + transfer->len;
 478         dws->write = dws->tx ? chip->write : null_writer;
 479         dws->read = dws->rx ? chip->read : null_reader;
 480         dws->cs_change = transfer->cs_change;
 481         dws->len = dws->cur_transfer->len;
 482         if (chip != dws->prev_chip)
 483                 cs_change = 1;
 484
 485         cr0 = chip->cr0;
 486
 487         /* Handle per transfer options for bpw and speed */
 488         if (transfer->speed_hz) {
 489                 speed = chip->speed_hz;
 490
 491                 if (transfer->speed_hz != speed) {
 492                         speed = transfer->speed_hz;
 493                         if (speed > dws->max_freq) {
 494                                 printk(KERN_ERR "MRST SPI0: unsupported"
 495                                         "freq: %dHz\n", speed);
 496                                 message->status = -EIO;
 497                                 goto early_exit;
 498                         }
 499
 500                         /* clk_div doesn't support odd number */
 501                         clk_div = dws->max_freq / speed;
 502                         clk_div = (clk_div + 1) & 0xfffe;
 503
 504                         chip->speed_hz = speed;
 505                         chip->clk_div = clk_div;
 506                 }
 507         }
 508         if (transfer->bits_per_word) {
 509                 bits = transfer->bits_per_word;
 510
 511                 switch (bits) {
 512                 case 8:
 513                         dws->n_bytes = 1;
 514                         dws->dma_width = 1;
 515                         dws->read = (dws->read != null_reader) ?
 516                                         u8_reader : null_reader;
 517                         dws->write = (dws->write != null_writer) ?
 518                                         u8_writer : null_writer;
 519                         break;
 520                 case 16:
 521                         dws->n_bytes = 2;
 522                         dws->dma_width = 2;
 523                         dws->read = (dws->read != null_reader) ?
 524                                         u16_reader : null_reader;
 525                         dws->write = (dws->write != null_writer) ?
 526                                         u16_writer : null_writer;
 527                         break;
 528                 default:
 529                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 530                                 "%db\n", bits);
 531                         message->status = -EIO;
 532                         goto early_exit;
 533                 }
 534
 535                 cr0 = (bits - 1)
 536                         | (chip->type << SPI_FRF_OFFSET)
 537                         | (spi->mode << SPI_MODE_OFFSET)
 538                         | (chip->tmode << SPI_TMOD_OFFSET);
 539         }
 540         message->state = RUNNING_STATE;
 541
 542         /*
 543          * Adjust transfer mode if necessary. Requires platform dependent
 544          * chipselect mechanism.
 545          */
 546         if (dws->cs_control) {
 547                 if (dws->rx && dws->tx)
 548                         chip->tmode = 0x00;
 549                 else if (dws->rx)
 550                         chip->tmode = 0x02;
 551                 else
 552                         chip->tmode = 0x01;
 553
 554                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
 555                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 556         }
 557
 558         /* Check if current transfer is a DMA transaction */
 559         dws->dma_mapped = map_dma_buffers(dws);
 560
 561         /*
 562          * Interrupt mode
 563          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 564          */
 565         if (!dws->dma_mapped && !chip->poll_mode) {
 566                 int templen = dws->len / dws->n_bytes;
 567                 txint_level = dws->fifo_len / 2;
 568                 txint_level = (templen > txint_level) ? txint_level : templen;
 569
 570                 imask |= SPI_INT_TXEI;
 571                 dws->transfer_handler = interrupt_transfer;
 572         }
 573
 574         /*
 575          * Reprogram registers only if
 576          *      1. chip select changes
 577          *      2. clk_div is changed
 578          *      3. control value changes
 579          */
 580         if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
 581                 spi_enable_chip(dws, 0);
 582
 583                 if (dw_readw(dws, ctrl0) != cr0)
 584                         dw_writew(dws, ctrl0, cr0);
 585
 586                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 587                 spi_chip_sel(dws, spi->chip_select);
 588
 589                 /* Set the interrupt mask, for poll mode just diable all int */
 590                 spi_mask_intr(dws, 0xff);
 591                 if (imask)
 592                         spi_umask_intr(dws, imask);
 593                 if (txint_level)
 594                         dw_writew(dws, txfltr, txint_level);
 595
 596                 spi_enable_chip(dws, 1);
 597                 if (cs_change)
 598                         dws->prev_chip = chip;
 599         }
 600
 601         if (dws->dma_mapped)
 602                 dma_transfer(dws, cs_change);
 603
 604         if (chip->poll_mode)
 605                 poll_transfer(dws);
 606
 607         return;
 608
 609 early_exit:
 610         giveback(dws);
 611         return;
 612 }
 613
 614 static void pump_messages(struct work_struct *work)
 615 {
 616         struct dw_spi *dws =
 617                 container_of(work, struct dw_spi, pump_messages);
 618         unsigned long flags;
 619
 620         /* Lock queue and check for queue work */
 621         spin_lock_irqsave(&dws->lock, flags);
 622         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 623                 dws->busy = 0;
 624                 spin_unlock_irqrestore(&dws->lock, flags);
 625                 return;
 626         }
 627
 628         /* Make sure we are not already running a message */
 629         if (dws->cur_msg) {
 630                 spin_unlock_irqrestore(&dws->lock, flags);
 631                 return;
 632         }
 633
 634         /* Extract head of queue */
 635         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 636         list_del_init(&dws->cur_msg->queue);
 637
 638         /* Initial message state*/
 639         dws->cur_msg->state = START_STATE;
 640         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 641                                                 struct spi_transfer,
 642                                                 transfer_list);
 643         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 644
 645         /* Mark as busy and launch transfers */
 646         tasklet_schedule(&dws->pump_transfers);
 647
 648         dws->busy = 1;
 649         spin_unlock_irqrestore(&dws->lock, flags);
 650 }
 651
 652 /* spi_device use this to queue in their spi_msg */
 653 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 654 {
 655         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 656         unsigned long flags;
 657
 658         spin_lock_irqsave(&dws->lock, flags);
 659
 660         if (dws->run == QUEUE_STOPPED) {
 661                 spin_unlock_irqrestore(&dws->lock, flags);
 662                 return -ESHUTDOWN;
 663         }
 664
 665         msg->actual_length = 0;
 666         msg->status = -EINPROGRESS;
 667         msg->state = START_STATE;
 668
 669         list_add_tail(&msg->queue, &dws->queue);
 670
 671         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 672
 673                 if (dws->cur_transfer || dws->cur_msg)
 674                         queue_work(dws->workqueue,
 675                                         &dws->pump_messages);
 676                 else {
 677                         /* If no other data transaction in air, just go */
 678                         spin_unlock_irqrestore(&dws->lock, flags);
 679                         pump_messages(&dws->pump_messages);
 680                         return 0;
 681                 }
 682         }
 683
 684         spin_unlock_irqrestore(&dws->lock, flags);
 685         return 0;
 686 }
 687
 688 /* This may be called twice for each spi dev */
 689 static int dw_spi_setup(struct spi_device *spi)
 690 {
 691         struct dw_spi_chip *chip_info = NULL;
 692         struct chip_data *chip;
 693
 694         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 695                 return -EINVAL;
 696
 697         /* Only alloc on first setup */
 698         chip = spi_get_ctldata(spi);
 699         if (!chip) {
 700                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 701                 if (!chip)
 702                         return -ENOMEM;
 703
 704                 chip->cs_control = null_cs_control;
 705                 chip->enable_dma = 0;
 706         }
 707
 708         /*
 709          * Protocol drivers may change the chip settings, so...
 710          * if chip_info exists, use it
 711          */
 712         chip_info = spi->controller_data;
 713
 714         /* chip_info doesn't always exist */
 715         if (chip_info) {
 716                 if (chip_info->cs_control)
 717                         chip->cs_control = chip_info->cs_control;
 718
 719                 chip->poll_mode = chip_info->poll_mode;
 720                 chip->type = chip_info->type;
 721
 722                 chip->rx_threshold = 0;
 723                 chip->tx_threshold = 0;
 724
 725                 chip->enable_dma = chip_info->enable_dma;
 726         }
 727
 728         if (spi->bits_per_word <= 8) {
 729                 chip->n_bytes = 1;
 730                 chip->dma_width = 1;
 731                 chip->read = u8_reader;
 732                 chip->write = u8_writer;
 733         } else if (spi->bits_per_word <= 16) {
 734                 chip->n_bytes = 2;
 735                 chip->dma_width = 2;
 736                 chip->read = u16_reader;
 737                 chip->write = u16_writer;
 738         } else {
 739                 /* Never take >16b case for MRST SPIC */
 740                 dev_err(&spi->dev, "invalid wordsize\n");
 741                 return -EINVAL;
 742         }
 743         chip->bits_per_word = spi->bits_per_word;
 744
 745         if (!spi->max_speed_hz) {
 746                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 747                 return -EINVAL;
 748         }
 749         chip->speed_hz = spi->max_speed_hz;
 750
 751         chip->tmode = 0; /* Tx & Rx */
 752         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 753         chip->cr0 = (chip->bits_per_word - 1)
 754                         | (chip->type << SPI_FRF_OFFSET)
 755                         | (spi->mode  << SPI_MODE_OFFSET)
 756                         | (chip->tmode << SPI_TMOD_OFFSET);
 757
 758         spi_set_ctldata(spi, chip);
 759         return 0;
 760 }
 761
 762 static void dw_spi_cleanup(struct spi_device *spi)
 763 {
 764         struct chip_data *chip = spi_get_ctldata(spi);
 765         kfree(chip);
 766 }
 767
 768 static int __devinit init_queue(struct dw_spi *dws)
 769 {
 770         INIT_LIST_HEAD(&dws->queue);
 771         spin_lock_init(&dws->lock);
 772
 773         dws->run = QUEUE_STOPPED;
 774         dws->busy = 0;
 775
 776         tasklet_init(&dws->pump_transfers,
 777                         pump_transfers, (unsigned long)dws);
 778
 779         INIT_WORK(&dws->pump_messages, pump_messages);
 780         dws->workqueue = create_singlethread_workqueue(
 781                                         dev_name(dws->master->dev.parent));
 782         if (dws->workqueue == NULL)
 783                 return -EBUSY;
 784
 785         return 0;
 786 }
 787
 788 static int start_queue(struct dw_spi *dws)
 789 {
 790         unsigned long flags;
 791
 792         spin_lock_irqsave(&dws->lock, flags);
 793
 794         if (dws->run == QUEUE_RUNNING || dws->busy) {
 795                 spin_unlock_irqrestore(&dws->lock, flags);
 796                 return -EBUSY;
 797         }
 798
 799         dws->run = QUEUE_RUNNING;
 800         dws->cur_msg = NULL;
 801         dws->cur_transfer = NULL;
 802         dws->cur_chip = NULL;
 803         dws->prev_chip = NULL;
 804         spin_unlock_irqrestore(&dws->lock, flags);
 805
 806         queue_work(dws->workqueue, &dws->pump_messages);
 807
 808         return 0;
 809 }
 810
 811 static int stop_queue(struct dw_spi *dws)
 812 {
 813         unsigned long flags;
 814         unsigned limit = 50;
 815         int status = 0;
 816
 817         spin_lock_irqsave(&dws->lock, flags);
 818         dws->run = QUEUE_STOPPED;
 819         while (!list_empty(&dws->queue) && dws->busy && limit--) {
 820                 spin_unlock_irqrestore(&dws->lock, flags);
 821                 msleep(10);
 822                 spin_lock_irqsave(&dws->lock, flags);
 823         }
 824
 825         if (!list_empty(&dws->queue) || dws->busy)
 826                 status = -EBUSY;
 827         spin_unlock_irqrestore(&dws->lock, flags);
 828
 829         return status;
 830 }
 831
 832 static int destroy_queue(struct dw_spi *dws)
 833 {
 834         int status;
 835
 836         status = stop_queue(dws);
 837         if (status != 0)
 838                 return status;
 839         destroy_workqueue(dws->workqueue);
 840         return 0;
 841 }
 842
 843 /* Restart the controller, disable all interrupts, clean rx fifo */
 844 static void spi_hw_init(struct dw_spi *dws)
 845 {
 846         spi_enable_chip(dws, 0);
 847         spi_mask_intr(dws, 0xff);
 848         spi_enable_chip(dws, 1);
 849         flush(dws);
 850
 851         /*
 852          * Try to detect the FIFO depth if not set by interface driver,
 853          * the depth could be from 2 to 256 from HW spec
 854          */
 855         if (!dws->fifo_len) {
 856                 u32 fifo;
 857                 for (fifo = 2; fifo <= 257; fifo++) {
 858                         dw_writew(dws, txfltr, fifo);
 859                         if (fifo != dw_readw(dws, txfltr))
 860                                 break;
 861                 }
 862
 863                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
 864                 dw_writew(dws, txfltr, 0);
 865         }
 866 }
 867
 868 int __devinit dw_spi_add_host(struct dw_spi *dws)
 869 {
 870         struct spi_master *master;
 871         int ret;
 872
 873         BUG_ON(dws == NULL);
 874
 875         master = spi_alloc_master(dws->parent_dev, 0);
 876         if (!master) {
 877                 ret = -ENOMEM;
 878                 goto exit;
 879         }
 880
 881         dws->master = master;
 882         dws->type = SSI_MOTO_SPI;
 883         dws->prev_chip = NULL;
 884         dws->dma_inited = 0;
 885         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 886
 887         ret = request_irq(dws->irq, dw_spi_irq, 0,
 888                         "dw_spi", dws);
 889         if (ret < 0) {
 890                 dev_err(&master->dev, "can not get IRQ\n");
 891                 goto err_free_master;
 892         }
 893
 894         master->mode_bits = SPI_CPOL | SPI_CPHA;
 895         master->bus_num = dws->bus_num;
 896         master->num_chipselect = dws->num_cs;
 897         master->cleanup = dw_spi_cleanup;
 898         master->setup = dw_spi_setup;
 899         master->transfer = dw_spi_transfer;
 900
 901         dws->dma_inited = 0;
 902
 903         /* Basic HW init */
 904         spi_hw_init(dws);
 905
 906         /* Initial and start queue */
 907         ret = init_queue(dws);
 908         if (ret) {
 909                 dev_err(&master->dev, "problem initializing queue\n");
 910                 goto err_diable_hw;
 911         }
 912         ret = start_queue(dws);
 913         if (ret) {
 914                 dev_err(&master->dev, "problem starting queue\n");
 915                 goto err_diable_hw;
 916         }
 917
 918         spi_master_set_devdata(master, dws);
 919         ret = spi_register_master(master);
 920         if (ret) {
 921                 dev_err(&master->dev, "problem registering spi master\n");
 922                 goto err_queue_alloc;
 923         }
 924
 925         mrst_spi_debugfs_init(dws);
 926         return 0;
 927
 928 err_queue_alloc:
 929         destroy_queue(dws);
 930 err_diable_hw:
 931         spi_enable_chip(dws, 0);
 932         free_irq(dws->irq, dws);
 933 err_free_master:
 934         spi_master_put(master);
 935 exit:
 936         return ret;
 937 }
 938 EXPORT_SYMBOL(dw_spi_add_host);
 939
 940 void __devexit dw_spi_remove_host(struct dw_spi *dws)
 941 {
 942         int status = 0;
 943
 944         if (!dws)
 945                 return;
 946         mrst_spi_debugfs_remove(dws);
 947
 948         /* Remove the queue */
 949         status = destroy_queue(dws);
 950         if (status != 0)
 951                 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
 952                         "complete, message memory not freed\n");
 953
 954         spi_enable_chip(dws, 0);
 955         /* Disable clk */
 956         spi_set_clk(dws, 0);
 957         free_irq(dws->irq, dws);
 958
 959         /* Disconnect from the SPI framework */
 960         spi_unregister_master(dws->master);
 961 }
 962 EXPORT_SYMBOL(dw_spi_remove_host);
 963
 964 int dw_spi_suspend_host(struct dw_spi *dws)
 965 {
 966         int ret = 0;
 967
 968         ret = stop_queue(dws);
 969         if (ret)
 970                 return ret;
 971         spi_enable_chip(dws, 0);
 972         spi_set_clk(dws, 0);
 973         return ret;
 974 }
 975 EXPORT_SYMBOL(dw_spi_suspend_host);
 976
 977 int dw_spi_resume_host(struct dw_spi *dws)
 978 {
 979         int ret;
 980
 981         spi_hw_init(dws);
 982         ret = start_queue(dws);
 983         if (ret)
 984                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 985         return ret;
 986 }
 987 EXPORT_SYMBOL(dw_spi_resume_host);
 988
 989 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 990 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 991 MODULE_LICENSE("GPL v2");