drivers/spi/atmel-quadspi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Atmel QSPI Controller
   4  *
   5  * Copyright (C) 2015 Atmel Corporation
   6  * Copyright (C) 2018 Cryptera A/S
   7  *
   8  * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
   9  * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
  10  *
  11  * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/spi/spi-mem.h>
  25
  26 /* QSPI register offsets */
  27 #define QSPI_CR      0x0000  /* Control Register */
  28 #define QSPI_MR      0x0004  /* Mode Register */
  29 #define QSPI_RD      0x0008  /* Receive Data Register */
  30 #define QSPI_TD      0x000c  /* Transmit Data Register */
  31 #define QSPI_SR      0x0010  /* Status Register */
  32 #define QSPI_IER     0x0014  /* Interrupt Enable Register */
  33 #define QSPI_IDR     0x0018  /* Interrupt Disable Register */
  34 #define QSPI_IMR     0x001c  /* Interrupt Mask Register */
  35 #define QSPI_SCR     0x0020  /* Serial Clock Register */
  36
  37 #define QSPI_IAR     0x0030  /* Instruction Address Register */
  38 #define QSPI_ICR     0x0034  /* Instruction Code Register */
  39 #define QSPI_WICR    0x0034  /* Write Instruction Code Register */
  40 #define QSPI_IFR     0x0038  /* Instruction Frame Register */
  41 #define QSPI_RICR    0x003C  /* Read Instruction Code Register */
  42
  43 #define QSPI_SMR     0x0040  /* Scrambling Mode Register */
  44 #define QSPI_SKR     0x0044  /* Scrambling Key Register */
  45
  46 #define QSPI_WPMR    0x00E4  /* Write Protection Mode Register */
  47 #define QSPI_WPSR    0x00E8  /* Write Protection Status Register */
  48
  49 #define QSPI_VERSION 0x00FC  /* Version Register */
  50
  51
  52 /* Bitfields in QSPI_CR (Control Register) */
  53 #define QSPI_CR_QSPIEN                  BIT(0)
  54 #define QSPI_CR_QSPIDIS                 BIT(1)
  55 #define QSPI_CR_SWRST                   BIT(7)
  56 #define QSPI_CR_LASTXFER                BIT(24)
  57
  58 /* Bitfields in QSPI_MR (Mode Register) */
  59 #define QSPI_MR_SMM                     BIT(0)
  60 #define QSPI_MR_LLB                     BIT(1)
  61 #define QSPI_MR_WDRBT                   BIT(2)
  62 #define QSPI_MR_SMRM                    BIT(3)
  63 #define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
  64 #define QSPI_MR_CSMODE_NOT_RELOADED     (0 << 4)
  65 #define QSPI_MR_CSMODE_LASTXFER         (1 << 4)
  66 #define QSPI_MR_CSMODE_SYSTEMATICALLY   (2 << 4)
  67 #define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
  68 #define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
  69 #define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
  70 #define QSPI_MR_DLYBCT(n)               (((n) << 16) & QSPI_MR_DLYBCT_MASK)
  71 #define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
  72 #define QSPI_MR_DLYCS(n)                (((n) << 24) & QSPI_MR_DLYCS_MASK)
  73
  74 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR  */
  75 #define QSPI_SR_RDRF                    BIT(0)
  76 #define QSPI_SR_TDRE                    BIT(1)
  77 #define QSPI_SR_TXEMPTY                 BIT(2)
  78 #define QSPI_SR_OVRES                   BIT(3)
  79 #define QSPI_SR_CSR                     BIT(8)
  80 #define QSPI_SR_CSS                     BIT(9)
  81 #define QSPI_SR_INSTRE                  BIT(10)
  82 #define QSPI_SR_QSPIENS                 BIT(24)
  83
  84 #define QSPI_SR_CMD_COMPLETED   (QSPI_SR_INSTRE | QSPI_SR_CSR)
  85
  86 /* Bitfields in QSPI_SCR (Serial Clock Register) */
  87 #define QSPI_SCR_CPOL                   BIT(0)
  88 #define QSPI_SCR_CPHA                   BIT(1)
  89 #define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
  90 #define QSPI_SCR_SCBR(n)                (((n) << 8) & QSPI_SCR_SCBR_MASK)
  91 #define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
  92 #define QSPI_SCR_DLYBS(n)               (((n) << 16) & QSPI_SCR_DLYBS_MASK)
  93
  94 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
  95 #define QSPI_ICR_INST_MASK              GENMASK(7, 0)
  96 #define QSPI_ICR_INST(inst)             (((inst) << 0) & QSPI_ICR_INST_MASK)
  97 #define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
  98 #define QSPI_ICR_OPT(opt)               (((opt) << 16) & QSPI_ICR_OPT_MASK)
  99
 100 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
 101 #define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
 102 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI   (0 << 0)
 103 #define QSPI_IFR_WIDTH_DUAL_OUTPUT      (1 << 0)
 104 #define QSPI_IFR_WIDTH_QUAD_OUTPUT      (2 << 0)
 105 #define QSPI_IFR_WIDTH_DUAL_IO          (3 << 0)
 106 #define QSPI_IFR_WIDTH_QUAD_IO          (4 << 0)
 107 #define QSPI_IFR_WIDTH_DUAL_CMD         (5 << 0)
 108 #define QSPI_IFR_WIDTH_QUAD_CMD         (6 << 0)
 109 #define QSPI_IFR_INSTEN                 BIT(4)
 110 #define QSPI_IFR_ADDREN                 BIT(5)
 111 #define QSPI_IFR_OPTEN                  BIT(6)
 112 #define QSPI_IFR_DATAEN                 BIT(7)
 113 #define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
 114 #define QSPI_IFR_OPTL_1BIT              (0 << 8)
 115 #define QSPI_IFR_OPTL_2BIT              (1 << 8)
 116 #define QSPI_IFR_OPTL_4BIT              (2 << 8)
 117 #define QSPI_IFR_OPTL_8BIT              (3 << 8)
 118 #define QSPI_IFR_ADDRL                  BIT(10)
 119 #define QSPI_IFR_TFRTYP_MEM             BIT(12)
 120 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR    BIT(13)
 121 #define QSPI_IFR_CRM                    BIT(14)
 122 #define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
 123 #define QSPI_IFR_NBDUM(n)               (((n) << 16) & QSPI_IFR_NBDUM_MASK)
 124 #define QSPI_IFR_APBTFRTYP_READ         BIT(24) /* Defined in SAM9X60 */
 125
 126 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
 127 #define QSPI_SMR_SCREN                  BIT(0)
 128 #define QSPI_SMR_RVDIS                  BIT(1)
 129
 130 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
 131 #define QSPI_WPMR_WPEN                  BIT(0)
 132 #define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
 133 #define QSPI_WPMR_WPKEY(wpkey)          (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
 134
 135 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
 136 #define QSPI_WPSR_WPVS                  BIT(0)
 137 #define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
 138 #define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)
 139
 140 struct atmel_qspi_caps {
 141         bool has_qspick;
 142         bool has_ricr;
 143 };
 144
 145 struct atmel_qspi {
 146         void __iomem            *regs;
 147         void __iomem            *mem;
 148         struct clk              *pclk;
 149         struct clk              *qspick;
 150         struct platform_device  *pdev;
 151         const struct atmel_qspi_caps *caps;
 152         u32                     pending;
 153         u32                     mr;
 154         struct completion       cmd_completion;
 155 };
 156
 157 struct atmel_qspi_mode {
 158         u8 cmd_buswidth;
 159         u8 addr_buswidth;
 160         u8 data_buswidth;
 161         u32 config;
 162 };
 163
 164 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
 165         { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
 166         { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
 167         { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
 168         { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
 169         { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
 170         { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
 171         { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
 172 };
 173
 174 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
 175                                             const struct atmel_qspi_mode *mode)
 176 {
 177         if (op->cmd.buswidth != mode->cmd_buswidth)
 178                 return false;
 179
 180         if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
 181                 return false;
 182
 183         if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
 184                 return false;
 185
 186         return true;
 187 }
 188
 189 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
 190 {
 191         u32 i;
 192
 193         for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
 194                 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
 195                         return i;
 196
 197         return -ENOTSUPP;
 198 }
 199
 200 static bool atmel_qspi_supports_op(struct spi_mem *mem,
 201                                    const struct spi_mem_op *op)
 202 {
 203         if (atmel_qspi_find_mode(op) < 0)
 204                 return false;
 205
 206         /* special case not supported by hardware */
 207         if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
 208                 op->dummy.nbytes == 0)
 209                 return false;
 210
 211         return true;
 212 }
 213
 214 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
 215                               const struct spi_mem_op *op, u32 *offset)
 216 {
 217         u32 iar, icr, ifr;
 218         u32 dummy_cycles = 0;
 219         int mode;
 220
 221         iar = 0;
 222         icr = QSPI_ICR_INST(op->cmd.opcode);
 223         ifr = QSPI_IFR_INSTEN;
 224
 225         mode = atmel_qspi_find_mode(op);
 226         if (mode < 0)
 227                 return mode;
 228         ifr |= atmel_qspi_modes[mode].config;
 229
 230         if (op->dummy.buswidth && op->dummy.nbytes)
 231                 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
 232
 233         /*
 234          * The controller allows 24 and 32-bit addressing while NAND-flash
 235          * requires 16-bit long. Handling 8-bit long addresses is done using
 236          * the option field. For the 16-bit addresses, the workaround depends
 237          * of the number of requested dummy bits. If there are 8 or more dummy
 238          * cycles, the address is shifted and sent with the first dummy byte.
 239          * Otherwise opcode is disabled and the first byte of the address
 240          * contains the command opcode (works only if the opcode and address
 241          * use the same buswidth). The limitation is when the 16-bit address is
 242          * used without enough dummy cycles and the opcode is using a different
 243          * buswidth than the address.
 244          */
 245         if (op->addr.buswidth) {
 246                 switch (op->addr.nbytes) {
 247                 case 0:
 248                         break;
 249                 case 1:
 250                         ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
 251                         icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
 252                         break;
 253                 case 2:
 254                         if (dummy_cycles < 8 / op->addr.buswidth) {
 255                                 ifr &= ~QSPI_IFR_INSTEN;
 256                                 ifr |= QSPI_IFR_ADDREN;
 257                                 iar = (op->cmd.opcode << 16) |
 258                                         (op->addr.val & 0xffff);
 259                         } else {
 260                                 ifr |= QSPI_IFR_ADDREN;
 261                                 iar = (op->addr.val << 8) & 0xffffff;
 262                                 dummy_cycles -= 8 / op->addr.buswidth;
 263                         }
 264                         break;
 265                 case 3:
 266                         ifr |= QSPI_IFR_ADDREN;
 267                         iar = op->addr.val & 0xffffff;
 268                         break;
 269                 case 4:
 270                         ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
 271                         iar = op->addr.val & 0x7ffffff;
 272                         break;
 273                 default:
 274                         return -ENOTSUPP;
 275                 }
 276         }
 277
 278         /* offset of the data access in the QSPI memory space */
 279         *offset = iar;
 280
 281         /* Set number of dummy cycles */
 282         if (dummy_cycles)
 283                 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
 284
 285         /* Set data enable */
 286         if (op->data.nbytes)
 287                 ifr |= QSPI_IFR_DATAEN;
 288
 289         /*
 290          * If the QSPI controller is set in regular SPI mode, set it in
 291          * Serial Memory Mode (SMM).
 292          */
 293         if (aq->mr != QSPI_MR_SMM) {
 294                 writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
 295                 aq->mr = QSPI_MR_SMM;
 296         }
 297
 298         /* Clear pending interrupts */
 299         (void)readl_relaxed(aq->regs + QSPI_SR);
 300
 301         if (aq->caps->has_ricr) {
 302                 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
 303                         ifr |= QSPI_IFR_APBTFRTYP_READ;
 304
 305                 /* Set QSPI Instruction Frame registers */
 306                 writel_relaxed(iar, aq->regs + QSPI_IAR);
 307                 if (op->data.dir == SPI_MEM_DATA_IN)
 308                         writel_relaxed(icr, aq->regs + QSPI_RICR);
 309                 else
 310                         writel_relaxed(icr, aq->regs + QSPI_WICR);
 311                 writel_relaxed(ifr, aq->regs + QSPI_IFR);
 312         } else {
 313                 if (op->data.dir == SPI_MEM_DATA_OUT)
 314                         ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
 315
 316                 /* Set QSPI Instruction Frame registers */
 317                 writel_relaxed(iar, aq->regs + QSPI_IAR);
 318                 writel_relaxed(icr, aq->regs + QSPI_ICR);
 319                 writel_relaxed(ifr, aq->regs + QSPI_IFR);
 320         }
 321
 322         return 0;
 323 }
 324
 325 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 326 {
 327         struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
 328         u32 sr, offset;
 329         int err;
 330
 331         err = atmel_qspi_set_cfg(aq, op, &offset);
 332         if (err)
 333                 return err;
 334
 335         /* Skip to the final steps if there is no data */
 336         if (op->data.nbytes) {
 337                 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
 338                 (void)readl_relaxed(aq->regs + QSPI_IFR);
 339
 340                 /* Send/Receive data */
 341                 if (op->data.dir == SPI_MEM_DATA_IN)
 342                         _memcpy_fromio(op->data.buf.in, aq->mem + offset,
 343                                        op->data.nbytes);
 344                 else
 345                         _memcpy_toio(aq->mem + offset, op->data.buf.out,
 346                                      op->data.nbytes);
 347
 348                 /* Release the chip-select */
 349                 writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
 350         }
 351
 352         /* Poll INSTRuction End status */
 353         sr = readl_relaxed(aq->regs + QSPI_SR);
 354         if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
 355                 return err;
 356
 357         /* Wait for INSTRuction End interrupt */
 358         reinit_completion(&aq->cmd_completion);
 359         aq->pending = sr & QSPI_SR_CMD_COMPLETED;
 360         writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
 361         if (!wait_for_completion_timeout(&aq->cmd_completion,
 362                                          msecs_to_jiffies(1000)))
 363                 err = -ETIMEDOUT;
 364         writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);
 365
 366         return err;
 367 }
 368
 369 static const char *atmel_qspi_get_name(struct spi_mem *spimem)
 370 {
 371         return dev_name(spimem->spi->dev.parent);
 372 }
 373
 374 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
 375         .supports_op = atmel_qspi_supports_op,
 376         .exec_op = atmel_qspi_exec_op,
 377         .get_name = atmel_qspi_get_name
 378 };
 379
 380 static int atmel_qspi_setup(struct spi_device *spi)
 381 {
 382         struct spi_controller *ctrl = spi->master;
 383         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 384         unsigned long src_rate;
 385         u32 scr, scbr;
 386
 387         if (ctrl->busy)
 388                 return -EBUSY;
 389
 390         if (!spi->max_speed_hz)
 391                 return -EINVAL;
 392
 393         src_rate = clk_get_rate(aq->pclk);
 394         if (!src_rate)
 395                 return -EINVAL;
 396
 397         /* Compute the QSPI baudrate */
 398         scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
 399         if (scbr > 0)
 400                 scbr--;
 401
 402         scr = QSPI_SCR_SCBR(scbr);
 403         writel_relaxed(scr, aq->regs + QSPI_SCR);
 404
 405         return 0;
 406 }
 407
 408 static int atmel_qspi_init(struct atmel_qspi *aq)
 409 {
 410         /* Reset the QSPI controller */
 411         writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);
 412
 413         /* Set the QSPI controller by default in Serial Memory Mode */
 414         writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
 415         aq->mr = QSPI_MR_SMM;
 416
 417         /* Enable the QSPI controller */
 418         writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
 419
 420         return 0;
 421 }
 422
 423 static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
 424 {
 425         struct atmel_qspi *aq = dev_id;
 426         u32 status, mask, pending;
 427
 428         status = readl_relaxed(aq->regs + QSPI_SR);
 429         mask = readl_relaxed(aq->regs + QSPI_IMR);
 430         pending = status & mask;
 431
 432         if (!pending)
 433                 return IRQ_NONE;
 434
 435         aq->pending |= pending;
 436         if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
 437                 complete(&aq->cmd_completion);
 438
 439         return IRQ_HANDLED;
 440 }
 441
 442 static int atmel_qspi_probe(struct platform_device *pdev)
 443 {
 444         struct spi_controller *ctrl;
 445         struct atmel_qspi *aq;
 446         struct resource *res;
 447         int irq, err = 0;
 448
 449         ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
 450         if (!ctrl)
 451                 return -ENOMEM;
 452
 453         ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
 454         ctrl->setup = atmel_qspi_setup;
 455         ctrl->bus_num = -1;
 456         ctrl->mem_ops = &atmel_qspi_mem_ops;
 457         ctrl->num_chipselect = 1;
 458         ctrl->dev.of_node = pdev->dev.of_node;
 459         platform_set_drvdata(pdev, ctrl);
 460
 461         aq = spi_controller_get_devdata(ctrl);
 462
 463         init_completion(&aq->cmd_completion);
 464         aq->pdev = pdev;
 465
 466         /* Map the registers */
 467         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 468         aq->regs = devm_ioremap_resource(&pdev->dev, res);
 469         if (IS_ERR(aq->regs)) {
 470                 dev_err(&pdev->dev, "missing registers\n");
 471                 err = PTR_ERR(aq->regs);
 472                 goto exit;
 473         }
 474
 475         /* Map the AHB memory */
 476         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
 477         aq->mem = devm_ioremap_resource(&pdev->dev, res);
 478         if (IS_ERR(aq->mem)) {
 479                 dev_err(&pdev->dev, "missing AHB memory\n");
 480                 err = PTR_ERR(aq->mem);
 481                 goto exit;
 482         }
 483
 484         /* Get the peripheral clock */
 485         aq->pclk = devm_clk_get(&pdev->dev, "pclk");
 486         if (IS_ERR(aq->pclk))
 487                 aq->pclk = devm_clk_get(&pdev->dev, NULL);
 488
 489         if (IS_ERR(aq->pclk)) {
 490                 dev_err(&pdev->dev, "missing peripheral clock\n");
 491                 err = PTR_ERR(aq->pclk);
 492                 goto exit;
 493         }
 494
 495         /* Enable the peripheral clock */
 496         err = clk_prepare_enable(aq->pclk);
 497         if (err) {
 498                 dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
 499                 goto exit;
 500         }
 501
 502         aq->caps = of_device_get_match_data(&pdev->dev);
 503         if (!aq->caps) {
 504                 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
 505                 err = -EINVAL;
 506                 goto exit;
 507         }
 508
 509         if (aq->caps->has_qspick) {
 510                 /* Get the QSPI system clock */
 511                 aq->qspick = devm_clk_get(&pdev->dev, "qspick");
 512                 if (IS_ERR(aq->qspick)) {
 513                         dev_err(&pdev->dev, "missing system clock\n");
 514                         err = PTR_ERR(aq->qspick);
 515                         goto disable_pclk;
 516                 }
 517
 518                 /* Enable the QSPI system clock */
 519                 err = clk_prepare_enable(aq->qspick);
 520                 if (err) {
 521                         dev_err(&pdev->dev,
 522                                 "failed to enable the QSPI system clock\n");
 523                         goto disable_pclk;
 524                 }
 525         }
 526
 527         /* Request the IRQ */
 528         irq = platform_get_irq(pdev, 0);
 529         if (irq < 0) {
 530                 dev_err(&pdev->dev, "missing IRQ\n");
 531                 err = irq;
 532                 goto disable_qspick;
 533         }
 534         err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
 535                                0, dev_name(&pdev->dev), aq);
 536         if (err)
 537                 goto disable_qspick;
 538
 539         err = atmel_qspi_init(aq);
 540         if (err)
 541                 goto disable_qspick;
 542
 543         err = spi_register_controller(ctrl);
 544         if (err)
 545                 goto disable_qspick;
 546
 547         return 0;
 548
 549 disable_qspick:
 550         clk_disable_unprepare(aq->qspick);
 551 disable_pclk:
 552         clk_disable_unprepare(aq->pclk);
 553 exit:
 554         spi_controller_put(ctrl);
 555
 556         return err;
 557 }
 558
 559 static int atmel_qspi_remove(struct platform_device *pdev)
 560 {
 561         struct spi_controller *ctrl = platform_get_drvdata(pdev);
 562         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 563
 564         spi_unregister_controller(ctrl);
 565         writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
 566         clk_disable_unprepare(aq->qspick);
 567         clk_disable_unprepare(aq->pclk);
 568         return 0;
 569 }
 570
 571 static int __maybe_unused atmel_qspi_suspend(struct device *dev)
 572 {
 573         struct spi_controller *ctrl = dev_get_drvdata(dev);
 574         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 575
 576         clk_disable_unprepare(aq->qspick);
 577         clk_disable_unprepare(aq->pclk);
 578
 579         return 0;
 580 }
 581
 582 static int __maybe_unused atmel_qspi_resume(struct device *dev)
 583 {
 584         struct spi_controller *ctrl = dev_get_drvdata(dev);
 585         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 586
 587         clk_prepare_enable(aq->pclk);
 588         clk_prepare_enable(aq->qspick);
 589
 590         return atmel_qspi_init(aq);
 591 }
 592
 593 static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
 594                          atmel_qspi_resume);
 595
 596 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
 597
 598 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
 599         .has_qspick = true,
 600         .has_ricr = true,
 601 };
 602
 603 static const struct of_device_id atmel_qspi_dt_ids[] = {
 604         {
 605                 .compatible = "atmel,sama5d2-qspi",
 606                 .data = &atmel_sama5d2_qspi_caps,
 607         },
 608         {
 609                 .compatible = "microchip,sam9x60-qspi",
 610                 .data = &atmel_sam9x60_qspi_caps,
 611         },
 612         { /* sentinel */ }
 613 };
 614
 615 MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
 616
 617 static struct platform_driver atmel_qspi_driver = {
 618         .driver = {
 619                 .name   = "atmel_qspi",
 620                 .of_match_table = atmel_qspi_dt_ids,
 621                 .pm     = &atmel_qspi_pm_ops,
 622         },
 623         .probe          = atmel_qspi_probe,
 624         .remove         = atmel_qspi_remove,
 625 };
 626 module_platform_driver(atmel_qspi_driver);
 627
 628 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
 629 MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
 630 MODULE_DESCRIPTION("Atmel QSPI Controller driver");
 631 MODULE_LICENSE("GPL v2");