1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
5 #include <linux/completion.h>
6 #include <linux/interrupt.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/debugfs.h>
12 #include <linux/of_irq.h>
13 #include <linux/of_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17 #include <linux/slab.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/slimbus.h>
20 #include <linux/soundwire/sdw.h>
21 #include <linux/soundwire/sdw_registers.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
26 #define SWRM_COMP_SW_RESET 0x008
27 #define SWRM_COMP_STATUS 0x014
28 #define SWRM_LINK_MANAGER_EE 0x018
30 #define SWRM_FRM_GEN_ENABLED BIT(0)
31 #define SWRM_COMP_HW_VERSION 0x00
32 #define SWRM_COMP_CFG_ADDR 0x04
33 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
34 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
35 #define SWRM_COMP_PARAMS 0x100
36 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10)
37 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
38 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
39 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
40 #define SWRM_COMP_MASTER_ID 0x104
41 #define SWRM_INTERRUPT_STATUS 0x200
42 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
43 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
44 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
45 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
46 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3)
47 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4)
48 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5)
49 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6)
50 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
51 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8)
52 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9)
53 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
54 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13)
55 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14)
56 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16)
57 #define SWRM_INTERRUPT_MAX 17
58 #define SWRM_INTERRUPT_MASK_ADDR 0x204
59 #define SWRM_INTERRUPT_CLEAR 0x208
60 #define SWRM_INTERRUPT_CPU_EN 0x210
61 #define SWRM_CMD_FIFO_WR_CMD 0x300
62 #define SWRM_CMD_FIFO_RD_CMD 0x304
63 #define SWRM_CMD_FIFO_CMD 0x308
64 #define SWRM_CMD_FIFO_FLUSH 0x1
65 #define SWRM_CMD_FIFO_STATUS 0x30C
66 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16)
67 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8)
68 #define SWRM_CMD_FIFO_CFG_ADDR 0x314
69 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
70 #define SWRM_RD_WR_CMD_RETRIES 0x7
71 #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
72 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
73 #define SWRM_ENUMERATOR_CFG_ADDR 0x500
74 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
75 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
76 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
77 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
78 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
79 #define SWRM_MCP_BUS_CTRL 0x1044
80 #define SWRM_MCP_BUS_CLK_START BIT(1)
81 #define SWRM_MCP_CFG_ADDR 0x1048
82 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
83 #define SWRM_DEF_CMD_NO_PINGS 0x1f
84 #define SWRM_MCP_STATUS 0x104C
85 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
86 #define SWRM_MCP_SLV_STATUS 0x1090
87 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
88 #define SWRM_MCP_SLV_STATUS_SZ 2
89 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
90 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
91 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
92 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
93 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
94 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
95 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
96 #define SWR_MSTR_MAX_REG_ADDR (0x1740)
98 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
99 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
100 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
101 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
102 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
103 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
104 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
106 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \
107 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
109 #define MAX_FREQ_NUM 1
110 #define TIMEOUT_MS 100
111 #define QCOM_SWRM_MAX_RD_LEN 0x1
112 #define QCOM_SDW_MAX_PORTS 14
113 #define DEFAULT_CLK_FREQ 9600000
114 #define SWRM_MAX_DAIS 0xF
115 #define SWR_INVALID_PARAM 0xFF
116 #define SWR_HSTOP_MAX_VAL 0xF
117 #define SWR_HSTART_MIN_VAL 0x0
118 #define SWR_BROADCAST_CMD_ID 0x0F
119 #define SWR_MAX_CMD_ID 14
120 #define MAX_FIFO_RD_RETRY 3
121 #define SWR_OVERFLOW_RETRY_COUNT 30
122 #define SWRM_LINK_STATUS_RETRY_CNT 100
130 struct qcom_swrm_port_config {
142 struct qcom_swrm_ctrl {
145 struct regmap *regmap;
147 struct reset_control *audio_cgcr;
148 #ifdef CONFIG_DEBUG_FS
149 struct dentry *debugfs;
151 struct completion broadcast;
152 struct completion enumeration;
153 struct work_struct slave_work;
154 /* Port alloc/free lock */
155 struct mutex port_lock;
160 unsigned int version;
166 unsigned long dout_port_mask;
167 unsigned long din_port_mask;
171 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
172 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
173 enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
174 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
175 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
179 bool clock_stop_not_supported;
182 struct qcom_swrm_data {
185 bool sw_clk_gate_required;
188 static const struct qcom_swrm_data swrm_v1_3_data = {
193 static const struct qcom_swrm_data swrm_v1_5_data = {
198 static const struct qcom_swrm_data swrm_v1_6_data = {
201 .sw_clk_gate_required = true,
204 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
206 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
209 struct regmap *wcd_regmap = ctrl->regmap;
212 /* pg register + offset */
213 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
218 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
226 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
229 struct regmap *wcd_regmap = ctrl->regmap;
231 /* pg register + offset */
232 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
237 /* write address register */
238 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
246 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
249 *val = readl(ctrl->mmio + reg);
253 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
256 writel(val, ctrl->mmio + reg);
260 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
261 u8 dev_addr, u16 reg_addr)
266 if (id != SWR_BROADCAST_CMD_ID) {
267 if (id < SWR_MAX_CMD_ID)
273 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
278 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
280 u32 fifo_outstanding_data, value;
281 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
284 /* Check for fifo underflow during read */
285 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
286 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
288 /* Check if read data is available in read fifo */
289 if (fifo_outstanding_data > 0)
292 usleep_range(500, 510);
293 } while (fifo_retry_count--);
295 if (fifo_outstanding_data == 0) {
296 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
303 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
305 u32 fifo_outstanding_cmds, value;
306 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
309 /* Check for fifo overflow during write */
310 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
311 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
313 /* Check for space in write fifo before writing */
314 if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
317 usleep_range(500, 510);
318 } while (fifo_retry_count--);
320 if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
321 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
328 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
329 u8 dev_addr, u16 reg_addr)
336 if (dev_addr == SDW_BROADCAST_DEV_NUM) {
337 cmd_id = SWR_BROADCAST_CMD_ID;
338 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
341 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
345 if (swrm_wait_for_wr_fifo_avail(swrm))
346 return SDW_CMD_FAIL_OTHER;
348 if (cmd_id == SWR_BROADCAST_CMD_ID)
349 reinit_completion(&swrm->broadcast);
351 /* Its assumed that write is okay as we do not get any status back */
352 swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
354 /* version 1.3 or less */
355 if (swrm->version <= 0x01030000)
356 usleep_range(150, 155);
358 if (cmd_id == SWR_BROADCAST_CMD_ID) {
360 * sleep for 10ms for MSM soundwire variant to allow broadcast
361 * command to complete.
363 ret = wait_for_completion_timeout(&swrm->broadcast,
364 msecs_to_jiffies(TIMEOUT_MS));
366 ret = SDW_CMD_IGNORED;
376 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
377 u8 dev_addr, u16 reg_addr,
380 u32 cmd_data, cmd_id, val, retry_attempt = 0;
382 val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
385 * Check for outstanding cmd wrt. write fifo depth to avoid
386 * overflow as read will also increase write fifo cnt.
388 swrm_wait_for_wr_fifo_avail(swrm);
390 /* wait for FIFO RD to complete to avoid overflow */
391 usleep_range(100, 105);
392 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
393 /* wait for FIFO RD CMD complete to avoid overflow */
394 usleep_range(250, 255);
396 if (swrm_wait_for_rd_fifo_avail(swrm))
397 return SDW_CMD_FAIL_OTHER;
400 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
401 rval[0] = cmd_data & 0xFF;
402 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
404 if (cmd_id != swrm->rcmd_id) {
405 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
406 /* wait 500 us before retry on fifo read failure */
407 usleep_range(500, 505);
408 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
409 SWRM_CMD_FIFO_FLUSH);
410 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
417 } while (retry_attempt < MAX_FIFO_RD_RETRY);
419 dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
420 dev_num: 0x%x, cmd_data: 0x%x\n",
421 reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
423 return SDW_CMD_IGNORED;
426 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
431 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
433 for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
434 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
436 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
437 ctrl->status[dev_num] = status;
445 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
450 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
451 ctrl->slave_status = val;
453 for (i = 1; i <= SDW_MAX_DEVICES; i++) {
456 s = (val >> (i * 2));
457 s &= SWRM_MCP_SLV_STATUS_MASK;
462 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
463 struct sdw_slave *slave, int devnum)
465 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
468 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
469 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
470 status &= SWRM_MCP_SLV_STATUS_MASK;
472 if (status == SDW_SLAVE_ATTACHED) {
474 slave->dev_num = devnum;
475 mutex_lock(&bus->bus_lock);
476 set_bit(devnum, bus->assigned);
477 mutex_unlock(&bus->bus_lock);
481 static int qcom_swrm_enumerate(struct sdw_bus *bus)
483 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
484 struct sdw_slave *slave, *_s;
485 struct sdw_slave_id id;
490 char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
492 for (i = 1; i <= SDW_MAX_DEVICES; i++) {
493 /* do not continue if the status is Not Present */
494 if (!ctrl->status[i])
497 /*SCP_Devid5 - Devid 4*/
498 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
500 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
501 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
506 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
507 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
508 ((u64)buf1[0] << 40);
510 sdw_extract_slave_id(bus, addr, &id);
512 /* Now compare with entries */
513 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
514 if (sdw_compare_devid(slave, id) == 0) {
515 qcom_swrm_set_slave_dev_num(bus, slave, i);
522 qcom_swrm_set_slave_dev_num(bus, NULL, i);
523 sdw_slave_add(bus, &id, NULL);
527 complete(&ctrl->enumeration);
531 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
533 struct qcom_swrm_ctrl *swrm = dev_id;
536 ret = pm_runtime_resume_and_get(swrm->dev);
537 if (ret < 0 && ret != -EACCES) {
538 dev_err_ratelimited(swrm->dev,
539 "pm_runtime_resume_and_get failed in %s, ret %d\n",
544 if (swrm->wake_irq > 0) {
545 if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq)))
546 disable_irq_nosync(swrm->wake_irq);
549 pm_runtime_mark_last_busy(swrm->dev);
550 pm_runtime_put_autosuspend(swrm->dev);
555 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
557 struct qcom_swrm_ctrl *swrm = dev_id;
558 u32 value, intr_sts, intr_sts_masked, slave_status;
561 int ret = IRQ_HANDLED;
562 clk_prepare_enable(swrm->hclk);
564 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
565 intr_sts_masked = intr_sts & swrm->intr_mask;
568 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
569 value = intr_sts_masked & BIT(i);
574 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
575 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
577 dev_err_ratelimited(swrm->dev,
578 "no slave alert found.spurious interrupt\n");
580 sdw_handle_slave_status(&swrm->bus, swrm->status);
584 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
585 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
586 dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n");
587 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
588 if (swrm->slave_status == slave_status) {
589 dev_dbg(swrm->dev, "Slave status not changed %x\n",
592 qcom_swrm_get_device_status(swrm);
593 qcom_swrm_enumerate(&swrm->bus);
594 sdw_handle_slave_status(&swrm->bus, swrm->status);
597 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
598 dev_err_ratelimited(swrm->dev,
599 "%s: SWR bus clsh detected\n",
601 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
602 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
604 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
605 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
606 dev_err_ratelimited(swrm->dev,
607 "%s: SWR read FIFO overflow fifo status 0x%x\n",
610 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
611 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
612 dev_err_ratelimited(swrm->dev,
613 "%s: SWR read FIFO underflow fifo status 0x%x\n",
616 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
617 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
619 "%s: SWR write FIFO overflow fifo status %x\n",
621 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
623 case SWRM_INTERRUPT_STATUS_CMD_ERROR:
624 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
625 dev_err_ratelimited(swrm->dev,
626 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
628 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
630 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
631 dev_err_ratelimited(swrm->dev,
632 "%s: SWR Port collision detected\n",
634 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
635 swrm->reg_write(swrm,
636 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
638 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
639 dev_err_ratelimited(swrm->dev,
640 "%s: SWR read enable valid mismatch\n",
643 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
644 swrm->reg_write(swrm,
645 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
647 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
648 complete(&swrm->broadcast);
650 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
652 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
654 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
657 dev_err_ratelimited(swrm->dev,
658 "%s: SWR unknown interrupt value: %d\n",
664 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
665 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
666 intr_sts_masked = intr_sts & swrm->intr_mask;
667 } while (intr_sts_masked);
669 clk_disable_unprepare(swrm->hclk);
673 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
677 /* Clear Rows and Cols */
678 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
679 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
681 reset_control_reset(ctrl->audio_cgcr);
683 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
685 /* Enable Auto enumeration */
686 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
688 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
689 /* Mask soundwire interrupts */
690 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
691 SWRM_INTERRUPT_STATUS_RMSK);
693 /* Configure No pings */
694 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
695 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
696 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
698 if (ctrl->version >= 0x01070000) {
699 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
700 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
701 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
703 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
706 /* Configure number of retries of a read/write cmd */
707 if (ctrl->version > 0x01050001) {
708 /* Only for versions >= 1.5.1 */
709 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
710 SWRM_RD_WR_CMD_RETRIES |
711 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
713 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
714 SWRM_RD_WR_CMD_RETRIES);
717 /* Set IRQ to PULSE */
718 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
719 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
720 SWRM_COMP_CFG_ENABLE_MSK);
722 /* enable CPU IRQs */
724 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
725 SWRM_INTERRUPT_STATUS_RMSK);
727 ctrl->slave_status = 0;
728 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
729 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
730 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
735 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
738 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
741 if (msg->flags == SDW_MSG_FLAG_READ) {
742 for (i = 0; i < msg->len;) {
743 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
746 len = QCOM_SWRM_MAX_RD_LEN;
748 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
756 } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
757 for (i = 0; i < msg->len; i++) {
758 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
762 return SDW_CMD_IGNORED;
769 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
771 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
772 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
775 ctrl->reg_read(ctrl, reg, &val);
777 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
778 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
780 return ctrl->reg_write(ctrl, reg, val);
783 static int qcom_swrm_port_params(struct sdw_bus *bus,
784 struct sdw_port_params *p_params,
787 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
789 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
794 static int qcom_swrm_transport_params(struct sdw_bus *bus,
795 struct sdw_transport_params *params,
796 enum sdw_reg_bank bank)
798 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
799 struct qcom_swrm_port_config *pcfg;
801 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
804 pcfg = &ctrl->pconfig[params->port_num];
806 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
807 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
810 ret = ctrl->reg_write(ctrl, reg, value);
814 if (pcfg->lane_control != SWR_INVALID_PARAM) {
815 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
816 value = pcfg->lane_control;
817 ret = ctrl->reg_write(ctrl, reg, value);
822 if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
823 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
824 value = pcfg->blk_group_count;
825 ret = ctrl->reg_write(ctrl, reg, value);
830 if (pcfg->hstart != SWR_INVALID_PARAM
831 && pcfg->hstop != SWR_INVALID_PARAM) {
832 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
833 value = (pcfg->hstop << 4) | pcfg->hstart;
834 ret = ctrl->reg_write(ctrl, reg, value);
836 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
837 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
838 ret = ctrl->reg_write(ctrl, reg, value);
844 if (pcfg->bp_mode != SWR_INVALID_PARAM) {
845 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
846 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
853 static int qcom_swrm_port_enable(struct sdw_bus *bus,
854 struct sdw_enable_ch *enable_ch,
857 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
858 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
861 ctrl->reg_read(ctrl, reg, &val);
863 if (enable_ch->enable)
864 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
866 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
868 return ctrl->reg_write(ctrl, reg, val);
871 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
872 .dpn_set_port_params = qcom_swrm_port_params,
873 .dpn_set_port_transport_params = qcom_swrm_transport_params,
874 .dpn_port_enable_ch = qcom_swrm_port_enable,
877 static const struct sdw_master_ops qcom_swrm_ops = {
878 .xfer_msg = qcom_swrm_xfer_msg,
879 .pre_bank_switch = qcom_swrm_pre_bank_switch,
882 static int qcom_swrm_compute_params(struct sdw_bus *bus)
884 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
885 struct sdw_master_runtime *m_rt;
886 struct sdw_slave_runtime *s_rt;
887 struct sdw_port_runtime *p_rt;
888 struct qcom_swrm_port_config *pcfg;
889 struct sdw_slave *slave;
893 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
894 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
895 pcfg = &ctrl->pconfig[p_rt->num];
896 p_rt->transport_params.port_num = p_rt->num;
897 if (pcfg->word_length != SWR_INVALID_PARAM) {
898 sdw_fill_port_params(&p_rt->port_params,
899 p_rt->num, pcfg->word_length + 1,
900 SDW_PORT_FLOW_MODE_ISOCH,
901 SDW_PORT_DATA_MODE_NORMAL);
906 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
908 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
909 m_port = slave->m_port_map[p_rt->num];
910 /* port config starts at offset 0 so -1 from actual port number */
912 pcfg = &ctrl->pconfig[m_port];
914 pcfg = &ctrl->pconfig[i];
915 p_rt->transport_params.port_num = p_rt->num;
916 p_rt->transport_params.sample_interval =
918 p_rt->transport_params.offset1 = pcfg->off1;
919 p_rt->transport_params.offset2 = pcfg->off2;
920 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
921 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
923 p_rt->transport_params.hstart = pcfg->hstart;
924 p_rt->transport_params.hstop = pcfg->hstop;
925 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
926 if (pcfg->word_length != SWR_INVALID_PARAM) {
927 sdw_fill_port_params(&p_rt->port_params,
929 pcfg->word_length + 1,
930 SDW_PORT_FLOW_MODE_ISOCH,
931 SDW_PORT_DATA_MODE_NORMAL);
941 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
945 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
946 struct sdw_stream_runtime *stream)
948 struct sdw_master_runtime *m_rt;
949 struct sdw_port_runtime *p_rt;
950 unsigned long *port_mask;
952 mutex_lock(&ctrl->port_lock);
954 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
955 if (m_rt->direction == SDW_DATA_DIR_RX)
956 port_mask = &ctrl->dout_port_mask;
958 port_mask = &ctrl->din_port_mask;
960 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
961 clear_bit(p_rt->num, port_mask);
964 mutex_unlock(&ctrl->port_lock);
967 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
968 struct sdw_stream_runtime *stream,
969 struct snd_pcm_hw_params *params,
972 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
973 struct sdw_stream_config sconfig;
974 struct sdw_master_runtime *m_rt;
975 struct sdw_slave_runtime *s_rt;
976 struct sdw_port_runtime *p_rt;
977 struct sdw_slave *slave;
978 unsigned long *port_mask;
979 int i, maxport, pn, nports = 0, ret = 0;
982 mutex_lock(&ctrl->port_lock);
983 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
984 if (m_rt->direction == SDW_DATA_DIR_RX) {
985 maxport = ctrl->num_dout_ports;
986 port_mask = &ctrl->dout_port_mask;
988 maxport = ctrl->num_din_ports;
989 port_mask = &ctrl->din_port_mask;
992 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
994 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
995 m_port = slave->m_port_map[p_rt->num];
996 /* Port numbers start from 1 - 14*/
1000 pn = find_first_zero_bit(port_mask, maxport);
1003 dev_err(ctrl->dev, "All ports busy\n");
1007 set_bit(pn, port_mask);
1008 pconfig[nports].num = pn;
1009 pconfig[nports].ch_mask = p_rt->ch_mask;
1015 if (direction == SNDRV_PCM_STREAM_CAPTURE)
1016 sconfig.direction = SDW_DATA_DIR_TX;
1018 sconfig.direction = SDW_DATA_DIR_RX;
1020 /* hw parameters wil be ignored as we only support PDM */
1021 sconfig.ch_count = 1;
1022 sconfig.frame_rate = params_rate(params);
1023 sconfig.type = stream->type;
1025 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1029 for (i = 0; i < nports; i++)
1030 clear_bit(pconfig[i].num, port_mask);
1033 mutex_unlock(&ctrl->port_lock);
1038 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1039 struct snd_pcm_hw_params *params,
1040 struct snd_soc_dai *dai)
1042 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1043 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1046 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1049 qcom_swrm_stream_free_ports(ctrl, sruntime);
1054 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1055 struct snd_soc_dai *dai)
1057 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1058 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1060 qcom_swrm_stream_free_ports(ctrl, sruntime);
1061 sdw_stream_remove_master(&ctrl->bus, sruntime);
1066 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1067 void *stream, int direction)
1069 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1071 ctrl->sruntime[dai->id] = stream;
1076 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1078 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1080 return ctrl->sruntime[dai->id];
1083 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1084 struct snd_soc_dai *dai)
1086 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1087 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1088 struct sdw_stream_runtime *sruntime;
1089 struct snd_soc_dai *codec_dai;
1092 ret = pm_runtime_resume_and_get(ctrl->dev);
1093 if (ret < 0 && ret != -EACCES) {
1094 dev_err_ratelimited(ctrl->dev,
1095 "pm_runtime_resume_and_get failed in %s, ret %d\n",
1100 sruntime = sdw_alloc_stream(dai->name);
1104 ctrl->sruntime[dai->id] = sruntime;
1106 for_each_rtd_codec_dais(rtd, i, codec_dai) {
1107 ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1109 if (ret < 0 && ret != -ENOTSUPP) {
1110 dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1112 sdw_release_stream(sruntime);
1120 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1121 struct snd_soc_dai *dai)
1123 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1125 sdw_release_stream(ctrl->sruntime[dai->id]);
1126 ctrl->sruntime[dai->id] = NULL;
1127 pm_runtime_mark_last_busy(ctrl->dev);
1128 pm_runtime_put_autosuspend(ctrl->dev);
1132 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1133 .hw_params = qcom_swrm_hw_params,
1134 .hw_free = qcom_swrm_hw_free,
1135 .startup = qcom_swrm_startup,
1136 .shutdown = qcom_swrm_shutdown,
1137 .set_stream = qcom_swrm_set_sdw_stream,
1138 .get_stream = qcom_swrm_get_sdw_stream,
1141 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1142 .name = "soundwire",
1145 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1147 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1148 struct snd_soc_dai_driver *dais;
1149 struct snd_soc_pcm_stream *stream;
1150 struct device *dev = ctrl->dev;
1153 /* PDM dais are only tested for now */
1154 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1158 for (i = 0; i < num_dais; i++) {
1159 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1163 if (i < ctrl->num_dout_ports)
1164 stream = &dais[i].playback;
1166 stream = &dais[i].capture;
1168 stream->channels_min = 1;
1169 stream->channels_max = 1;
1170 stream->rates = SNDRV_PCM_RATE_48000;
1171 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1173 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1177 return devm_snd_soc_register_component(ctrl->dev,
1178 &qcom_swrm_dai_component,
1182 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1184 struct device_node *np = ctrl->dev->of_node;
1185 u8 off1[QCOM_SDW_MAX_PORTS];
1186 u8 off2[QCOM_SDW_MAX_PORTS];
1187 u8 si[QCOM_SDW_MAX_PORTS];
1188 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1189 u8 hstart[QCOM_SDW_MAX_PORTS];
1190 u8 hstop[QCOM_SDW_MAX_PORTS];
1191 u8 word_length[QCOM_SDW_MAX_PORTS];
1192 u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1193 u8 lane_control[QCOM_SDW_MAX_PORTS];
1194 int i, ret, nports, val;
1196 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1198 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1199 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1201 ret = of_property_read_u32(np, "qcom,din-ports", &val);
1205 if (val > ctrl->num_din_ports)
1208 ctrl->num_din_ports = val;
1210 ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1214 if (val > ctrl->num_dout_ports)
1217 ctrl->num_dout_ports = val;
1219 nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1220 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1221 set_bit(0, &ctrl->dout_port_mask);
1222 set_bit(0, &ctrl->din_port_mask);
1224 ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1229 ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1234 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1239 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1242 if (ctrl->version <= 0x01030000)
1243 memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1248 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1249 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1251 memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1252 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1254 memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1255 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1257 memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1258 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1260 memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1261 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1263 for (i = 0; i < nports; i++) {
1264 /* Valid port number range is from 1-14 */
1265 ctrl->pconfig[i + 1].si = si[i];
1266 ctrl->pconfig[i + 1].off1 = off1[i];
1267 ctrl->pconfig[i + 1].off2 = off2[i];
1268 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1269 ctrl->pconfig[i + 1].hstart = hstart[i];
1270 ctrl->pconfig[i + 1].hstop = hstop[i];
1271 ctrl->pconfig[i + 1].word_length = word_length[i];
1272 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1273 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1279 #ifdef CONFIG_DEBUG_FS
1280 static int swrm_reg_show(struct seq_file *s_file, void *data)
1282 struct qcom_swrm_ctrl *swrm = s_file->private;
1283 int reg, reg_val, ret;
1285 ret = pm_runtime_resume_and_get(swrm->dev);
1286 if (ret < 0 && ret != -EACCES) {
1287 dev_err_ratelimited(swrm->dev,
1288 "pm_runtime_resume_and_get failed in %s, ret %d\n",
1293 for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
1294 swrm->reg_read(swrm, reg, ®_val);
1295 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1297 pm_runtime_mark_last_busy(swrm->dev);
1298 pm_runtime_put_autosuspend(swrm->dev);
1303 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1306 static int qcom_swrm_probe(struct platform_device *pdev)
1308 struct device *dev = &pdev->dev;
1309 struct sdw_master_prop *prop;
1310 struct sdw_bus_params *params;
1311 struct qcom_swrm_ctrl *ctrl;
1312 const struct qcom_swrm_data *data;
1316 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1320 data = of_device_get_match_data(dev);
1321 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1322 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1323 #if IS_REACHABLE(CONFIG_SLIMBUS)
1324 if (dev->parent->bus == &slimbus_bus) {
1328 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1329 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1330 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1334 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1335 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1336 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1337 if (IS_ERR(ctrl->mmio))
1338 return PTR_ERR(ctrl->mmio);
1341 if (data->sw_clk_gate_required) {
1342 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1343 if (IS_ERR(ctrl->audio_cgcr)) {
1344 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1345 ret = PTR_ERR(ctrl->audio_cgcr);
1350 ctrl->irq = of_irq_get(dev->of_node, 0);
1351 if (ctrl->irq < 0) {
1356 ctrl->hclk = devm_clk_get(dev, "iface");
1357 if (IS_ERR(ctrl->hclk)) {
1358 ret = PTR_ERR(ctrl->hclk);
1362 clk_prepare_enable(ctrl->hclk);
1365 dev_set_drvdata(&pdev->dev, ctrl);
1366 mutex_init(&ctrl->port_lock);
1367 init_completion(&ctrl->broadcast);
1368 init_completion(&ctrl->enumeration);
1370 ctrl->bus.ops = &qcom_swrm_ops;
1371 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1372 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1373 ctrl->bus.clk_stop_timeout = 300;
1375 ret = qcom_swrm_get_port_config(ctrl);
1379 params = &ctrl->bus.params;
1380 params->max_dr_freq = DEFAULT_CLK_FREQ;
1381 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1382 params->col = data->default_cols;
1383 params->row = data->default_rows;
1384 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1385 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1386 params->next_bank = !params->curr_bank;
1388 prop = &ctrl->bus.prop;
1389 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1390 prop->num_clk_gears = 0;
1391 prop->num_clk_freq = MAX_FREQ_NUM;
1392 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1393 prop->default_col = data->default_cols;
1394 prop->default_row = data->default_rows;
1396 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1398 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1399 qcom_swrm_irq_handler,
1400 IRQF_TRIGGER_RISING |
1404 dev_err(dev, "Failed to request soundwire irq\n");
1408 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1409 if (ctrl->wake_irq > 0) {
1410 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1411 qcom_swrm_wake_irq_handler,
1412 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1413 "swr_wake_irq", ctrl);
1415 dev_err(dev, "Failed to request soundwire wake irq\n");
1420 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1422 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1427 qcom_swrm_init(ctrl);
1428 wait_for_completion_timeout(&ctrl->enumeration,
1429 msecs_to_jiffies(TIMEOUT_MS));
1430 ret = qcom_swrm_register_dais(ctrl);
1432 goto err_master_add;
1434 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1435 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1436 ctrl->version & 0xffff);
1438 pm_runtime_set_autosuspend_delay(dev, 3000);
1439 pm_runtime_use_autosuspend(dev);
1440 pm_runtime_mark_last_busy(dev);
1441 pm_runtime_set_active(dev);
1442 pm_runtime_enable(dev);
1444 /* Clk stop is not supported on WSA Soundwire masters */
1445 if (ctrl->version <= 0x01030000) {
1446 ctrl->clock_stop_not_supported = true;
1448 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1449 if (val == MASTER_ID_WSA)
1450 ctrl->clock_stop_not_supported = true;
1453 #ifdef CONFIG_DEBUG_FS
1454 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1455 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1462 sdw_bus_master_delete(&ctrl->bus);
1464 clk_disable_unprepare(ctrl->hclk);
1469 static int qcom_swrm_remove(struct platform_device *pdev)
1471 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1473 sdw_bus_master_delete(&ctrl->bus);
1474 clk_disable_unprepare(ctrl->hclk);
1479 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm)
1481 int retry = SWRM_LINK_STATUS_RETRY_CNT;
1485 swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
1487 if (comp_sts & SWRM_FRM_GEN_ENABLED)
1490 usleep_range(500, 510);
1493 dev_err(swrm->dev, "%s: link status not %s\n", __func__,
1494 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
1499 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1501 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1504 if (ctrl->wake_irq > 0) {
1505 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1506 disable_irq_nosync(ctrl->wake_irq);
1509 clk_prepare_enable(ctrl->hclk);
1511 if (ctrl->clock_stop_not_supported) {
1512 reinit_completion(&ctrl->enumeration);
1513 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1514 usleep_range(100, 105);
1516 qcom_swrm_init(ctrl);
1518 usleep_range(100, 105);
1519 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1520 dev_err(ctrl->dev, "link failed to connect\n");
1522 /* wait for hw enumeration to complete */
1523 wait_for_completion_timeout(&ctrl->enumeration,
1524 msecs_to_jiffies(TIMEOUT_MS));
1525 qcom_swrm_get_device_status(ctrl);
1526 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1528 reset_control_reset(ctrl->audio_cgcr);
1530 if (ctrl->version >= 0x01070000) {
1531 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1532 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1533 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
1535 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1537 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
1538 SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1540 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1541 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1542 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1544 usleep_range(100, 105);
1545 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1546 dev_err(ctrl->dev, "link failed to connect\n");
1548 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1550 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1556 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1558 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1561 if (!ctrl->clock_stop_not_supported) {
1562 /* Mask bus clash interrupt */
1563 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1564 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1565 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1566 /* Prepare slaves for clock stop */
1567 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1568 if (ret < 0 && ret != -ENODATA) {
1569 dev_err(dev, "prepare clock stop failed %d", ret);
1573 ret = sdw_bus_clk_stop(&ctrl->bus);
1574 if (ret < 0 && ret != -ENODATA) {
1575 dev_err(dev, "bus clock stop failed %d", ret);
1580 clk_disable_unprepare(ctrl->hclk);
1582 usleep_range(300, 305);
1584 if (ctrl->wake_irq > 0) {
1585 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1586 enable_irq(ctrl->wake_irq);
1592 static const struct dev_pm_ops swrm_dev_pm_ops = {
1593 SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1596 static const struct of_device_id qcom_swrm_of_match[] = {
1597 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1598 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1599 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1600 { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1604 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1606 static struct platform_driver qcom_swrm_driver = {
1607 .probe = &qcom_swrm_probe,
1608 .remove = &qcom_swrm_remove,
1610 .name = "qcom-soundwire",
1611 .of_match_table = qcom_swrm_of_match,
1612 .pm = &swrm_dev_pm_ops,
1615 module_platform_driver(qcom_swrm_driver);
1617 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1618 MODULE_LICENSE("GPL v2");