1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2023 Intel Corporation. All rights reserved.
5 * Soundwire Intel ops for LunarLake
8 #include <linux/acpi.h>
9 #include <linux/device.h>
10 #include <linux/soundwire/sdw_registers.h>
11 #include <linux/soundwire/sdw.h>
12 #include <linux/soundwire/sdw_intel.h>
13 #include <sound/hda-mlink.h>
14 #include "cadence_master.h"
19 * shim vendor-specific (vs) ops
22 static void intel_shim_vs_init(struct sdw_intel *sdw)
24 void __iomem *shim_vs = sdw->link_res->shim_vs;
27 u16p_replace_bits(&act, 0x1, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS);
28 act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE;
29 act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DODS;
30 intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL, act);
34 static int intel_shim_check_wake(struct sdw_intel *sdw)
36 void __iomem *shim_vs;
39 shim_vs = sdw->link_res->shim_vs;
40 wake_sts = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS);
42 return wake_sts & SDW_SHIM2_INTEL_VS_WAKEEN_PWS;
45 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
47 void __iomem *shim_vs = sdw->link_res->shim_vs;
51 wake_en = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN);
54 /* Enable the wakeup */
55 wake_en |= SDW_SHIM2_INTEL_VS_WAKEEN_PWE;
56 intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN, wake_en);
58 /* Disable the wake up interrupt */
59 wake_en &= ~SDW_SHIM2_INTEL_VS_WAKEEN_PWE;
60 intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN, wake_en);
62 /* Clear wake status (W1C) */
63 wake_sts = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS);
64 wake_sts |= SDW_SHIM2_INTEL_VS_WAKEEN_PWS;
65 intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS, wake_sts);
69 static int intel_link_power_up(struct sdw_intel *sdw)
71 struct sdw_bus *bus = &sdw->cdns.bus;
72 struct sdw_master_prop *prop = &bus->prop;
73 u32 *shim_mask = sdw->link_res->shim_mask;
74 unsigned int link_id = sdw->instance;
78 mutex_lock(sdw->link_res->shim_lock);
81 /* we first need to program the SyncPRD/CPU registers */
82 dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n");
84 if (prop->mclk_freq % 6000000)
85 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
87 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
89 ret = hdac_bus_eml_sdw_set_syncprd_unlocked(sdw->link_res->hbus, syncprd);
91 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_set_syncprd failed: %d\n",
97 ret = hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, link_id);
99 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_up failed: %d\n",
105 /* SYNCPU will change once link is active */
106 ret = hdac_bus_eml_sdw_wait_syncpu_unlocked(sdw->link_res->hbus);
108 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_wait_syncpu failed: %d\n",
114 *shim_mask |= BIT(link_id);
116 sdw->cdns.link_up = true;
118 intel_shim_vs_init(sdw);
121 mutex_unlock(sdw->link_res->shim_lock);
126 static int intel_link_power_down(struct sdw_intel *sdw)
128 u32 *shim_mask = sdw->link_res->shim_mask;
129 unsigned int link_id = sdw->instance;
132 mutex_lock(sdw->link_res->shim_lock);
134 sdw->cdns.link_up = false;
136 *shim_mask &= ~BIT(link_id);
138 ret = hdac_bus_eml_sdw_power_down_unlocked(sdw->link_res->hbus, link_id);
140 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_down failed: %d\n",
144 * we leave the sdw->cdns.link_up flag as false since we've disabled
145 * the link at this point and cannot handle interrupts any longer.
149 mutex_unlock(sdw->link_res->shim_lock);
154 static void intel_sync_arm(struct sdw_intel *sdw)
156 unsigned int link_id = sdw->instance;
158 mutex_lock(sdw->link_res->shim_lock);
160 hdac_bus_eml_sdw_sync_arm_unlocked(sdw->link_res->hbus, link_id);
162 mutex_unlock(sdw->link_res->shim_lock);
165 static int intel_sync_go_unlocked(struct sdw_intel *sdw)
169 ret = hdac_bus_eml_sdw_sync_go_unlocked(sdw->link_res->hbus);
171 dev_err(sdw->cdns.dev, "%s: SyncGO clear failed: %d\n", __func__, ret);
176 static int intel_sync_go(struct sdw_intel *sdw)
180 mutex_lock(sdw->link_res->shim_lock);
182 ret = intel_sync_go_unlocked(sdw);
184 mutex_unlock(sdw->link_res->shim_lock);
189 static bool intel_check_cmdsync_unlocked(struct sdw_intel *sdw)
191 return hdac_bus_eml_sdw_check_cmdsync_unlocked(sdw->link_res->hbus);
197 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
200 static const struct snd_soc_component_driver dai_component = {
207 static void intel_pdi_init(struct sdw_intel *sdw,
208 struct sdw_cdns_stream_config *config)
210 void __iomem *shim = sdw->link_res->shim;
213 /* PCM Stream Capability */
214 pcm_cap = intel_readw(shim, SDW_SHIM2_PCMSCAP);
216 config->pcm_bd = FIELD_GET(SDW_SHIM2_PCMSCAP_BSS, pcm_cap);
217 config->pcm_in = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap);
218 config->pcm_out = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap);
220 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
221 config->pcm_bd, config->pcm_in, config->pcm_out);
225 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num)
227 void __iomem *shim = sdw->link_res->shim;
229 /* zero based values for channel count in register */
230 return intel_readw(shim, SDW_SHIM2_PCMSYCHC(pdi_num)) + 1;
233 static void intel_pdi_get_ch_update(struct sdw_intel *sdw,
234 struct sdw_cdns_pdi *pdi,
235 unsigned int num_pdi,
236 unsigned int *num_ch)
241 for (i = 0; i < num_pdi; i++) {
242 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num);
243 ch_count += pdi->ch_count;
250 static void intel_pdi_stream_ch_update(struct sdw_intel *sdw,
251 struct sdw_cdns_streams *stream)
253 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
256 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
259 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
260 &stream->num_ch_out);
263 static int intel_create_dai(struct sdw_cdns *cdns,
264 struct snd_soc_dai_driver *dais,
265 enum intel_pdi_type type,
266 u32 num, u32 off, u32 max_ch)
273 for (i = off; i < (off + num); i++) {
274 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
280 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
281 dais[i].playback.channels_min = 1;
282 dais[i].playback.channels_max = max_ch;
285 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
286 dais[i].capture.channels_min = 1;
287 dais[i].capture.channels_max = max_ch;
290 dais[i].ops = &intel_pcm_dai_ops;
296 static int intel_register_dai(struct sdw_intel *sdw)
298 struct sdw_cdns_dai_runtime **dai_runtime_array;
299 struct sdw_cdns_stream_config config;
300 struct sdw_cdns *cdns = &sdw->cdns;
301 struct sdw_cdns_streams *stream;
302 struct snd_soc_dai_driver *dais;
307 /* Read the PDI config and initialize cadence PDI */
308 intel_pdi_init(sdw, &config);
309 ret = sdw_cdns_pdi_init(cdns, config);
313 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm);
315 /* DAIs are created based on total number of PDIs supported */
316 num_dai = cdns->pcm.num_pdi;
318 dai_runtime_array = devm_kcalloc(cdns->dev, num_dai,
319 sizeof(struct sdw_cdns_dai_runtime *),
321 if (!dai_runtime_array)
323 cdns->dai_runtime_array = dai_runtime_array;
325 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
329 /* Create PCM DAIs */
332 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
333 off, stream->num_ch_in);
337 off += cdns->pcm.num_in;
338 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
339 off, stream->num_ch_out);
343 off += cdns->pcm.num_out;
344 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
345 off, stream->num_ch_bd);
349 return devm_snd_soc_register_component(cdns->dev, &dai_component,
353 static void intel_program_sdi(struct sdw_intel *sdw, int dev_num)
357 ret = hdac_bus_eml_sdw_set_lsdiid(sdw->link_res->hbus, sdw->instance, dev_num);
359 dev_err(sdw->cdns.dev, "%s: could not set lsdiid for link %d %d\n",
360 __func__, sdw->instance, dev_num);
363 const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops = {
364 .debugfs_init = intel_ace2x_debugfs_init,
365 .debugfs_exit = intel_ace2x_debugfs_exit,
367 .register_dai = intel_register_dai,
369 .check_clock_stop = intel_check_clock_stop,
370 .start_bus = intel_start_bus,
371 .start_bus_after_reset = intel_start_bus_after_reset,
372 .start_bus_after_clock_stop = intel_start_bus_after_clock_stop,
373 .stop_bus = intel_stop_bus,
375 .link_power_up = intel_link_power_up,
376 .link_power_down = intel_link_power_down,
378 .shim_check_wake = intel_shim_check_wake,
379 .shim_wake = intel_shim_wake,
381 .pre_bank_switch = intel_pre_bank_switch,
382 .post_bank_switch = intel_post_bank_switch,
384 .sync_arm = intel_sync_arm,
385 .sync_go_unlocked = intel_sync_go_unlocked,
386 .sync_go = intel_sync_go,
387 .sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked,
389 .program_sdi = intel_program_sdi,
391 EXPORT_SYMBOL_NS(sdw_intel_lnl_hw_ops, SOUNDWIRE_INTEL);
393 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK);