1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
5 * Soundwire Intel Master Driver
8 #include <linux/acpi.h>
9 #include <linux/delay.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <sound/pcm_params.h>
14 #include <sound/soc.h>
15 #include <linux/soundwire/sdw_registers.h>
16 #include <linux/soundwire/sdw.h>
17 #include <linux/soundwire/sdw_intel.h>
18 #include "cadence_master.h"
21 /* Intel SHIM Registers Definition */
22 #define SDW_SHIM_LCAP 0x0
23 #define SDW_SHIM_LCTL 0x4
24 #define SDW_SHIM_IPPTR 0x8
25 #define SDW_SHIM_SYNC 0xC
27 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
28 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
29 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
30 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
31 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
32 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
34 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
35 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
36 #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
37 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
38 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
40 #define SDW_SHIM_WAKEEN 0x190
41 #define SDW_SHIM_WAKESTS 0x192
43 #define SDW_SHIM_LCTL_SPA BIT(0)
44 #define SDW_SHIM_LCTL_CPA BIT(8)
46 #define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F
47 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
48 #define SDW_SHIM_SYNC_SYNCCPU BIT(15)
49 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
50 #define SDW_SHIM_SYNC_CMDSYNC BIT(16)
51 #define SDW_SHIM_SYNC_SYNCGO BIT(24)
53 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
54 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
55 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
57 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
58 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
59 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
60 #define SDW_SHIM_PCMSYCM_DIR BIT(15)
62 #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
63 #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
64 #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
65 #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
67 #define SDW_SHIM_IOCTL_MIF BIT(0)
68 #define SDW_SHIM_IOCTL_CO BIT(1)
69 #define SDW_SHIM_IOCTL_COE BIT(2)
70 #define SDW_SHIM_IOCTL_DO BIT(3)
71 #define SDW_SHIM_IOCTL_DOE BIT(4)
72 #define SDW_SHIM_IOCTL_BKE BIT(5)
73 #define SDW_SHIM_IOCTL_WPDD BIT(6)
74 #define SDW_SHIM_IOCTL_CIBD BIT(8)
75 #define SDW_SHIM_IOCTL_DIBD BIT(9)
77 #define SDW_SHIM_CTMCTL_DACTQE BIT(0)
78 #define SDW_SHIM_CTMCTL_DODS BIT(1)
79 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
81 #define SDW_SHIM_WAKEEN_ENABLE BIT(0)
82 #define SDW_SHIM_WAKESTS_STATUS BIT(0)
84 /* Intel ALH Register definitions */
85 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
87 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
88 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
89 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
100 struct sdw_intel_link_res *res;
103 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
106 * Read, write helpers for HW registers
108 static inline int intel_readl(void __iomem *base, int offset)
110 return readl(base + offset);
113 static inline void intel_writel(void __iomem *base, int offset, int value)
115 writel(value, base + offset);
118 static inline u16 intel_readw(void __iomem *base, int offset)
120 return readw(base + offset);
123 static inline void intel_writew(void __iomem *base, int offset, u16 value)
125 writew(value, base + offset);
128 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
133 writel(value, base + offset);
135 reg_read = readl(base + offset);
136 if (!(reg_read & mask))
141 } while (timeout != 0);
146 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
151 writel(value, base + offset);
153 reg_read = readl(base + offset);
159 } while (timeout != 0);
168 static int intel_link_power_up(struct sdw_intel *sdw)
170 unsigned int link_id = sdw->instance;
171 void __iomem *shim = sdw->res->shim;
172 int spa_mask, cpa_mask;
173 int link_control, ret;
175 /* Link power up sequence */
176 link_control = intel_readl(shim, SDW_SHIM_LCTL);
177 spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
178 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
179 link_control |= spa_mask;
181 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
185 sdw->cdns.link_up = true;
189 static int intel_shim_init(struct sdw_intel *sdw)
191 void __iomem *shim = sdw->res->shim;
192 unsigned int link_id = sdw->instance;
194 u16 ioctl = 0, act = 0;
196 /* Initialize Shim */
197 ioctl |= SDW_SHIM_IOCTL_BKE;
198 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
200 ioctl |= SDW_SHIM_IOCTL_WPDD;
201 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
203 ioctl |= SDW_SHIM_IOCTL_DO;
204 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
206 ioctl |= SDW_SHIM_IOCTL_DOE;
207 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
209 /* Switch to MIP from Glue logic */
210 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
212 ioctl &= ~(SDW_SHIM_IOCTL_DOE);
213 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
215 ioctl &= ~(SDW_SHIM_IOCTL_DO);
216 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
218 ioctl |= (SDW_SHIM_IOCTL_MIF);
219 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
221 ioctl &= ~(SDW_SHIM_IOCTL_BKE);
222 ioctl &= ~(SDW_SHIM_IOCTL_COE);
224 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
226 act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
227 act |= SDW_SHIM_CTMCTL_DACTQE;
228 act |= SDW_SHIM_CTMCTL_DODS;
229 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
231 /* Now set SyncPRD period */
232 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
233 sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL <<
234 SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
236 /* Set SyncCPU bit */
237 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
238 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
239 SDW_SHIM_SYNC_SYNCCPU);
241 dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret);
249 static void intel_pdi_init(struct sdw_intel *sdw,
250 struct sdw_cdns_stream_config *config)
252 void __iomem *shim = sdw->res->shim;
253 unsigned int link_id = sdw->instance;
254 int pcm_cap, pdm_cap;
256 /* PCM Stream Capability */
257 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
259 config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
260 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
261 config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
262 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
263 config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
264 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
266 /* PDM Stream Capability */
267 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
269 config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
270 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
271 config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
272 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
273 config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
274 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
278 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
280 void __iomem *shim = sdw->res->shim;
281 unsigned int link_id = sdw->instance;
285 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
287 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
288 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
289 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
292 /* zero based values for channel count in register */
298 static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
299 struct sdw_cdns_pdi *pdi,
300 unsigned int num_pdi,
301 unsigned int *num_ch, bool pcm)
305 for (i = 0; i < num_pdi; i++) {
306 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
307 ch_count += pdi->ch_count;
315 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
316 struct sdw_cdns_streams *stream, bool pcm)
318 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
319 &stream->num_ch_bd, pcm);
321 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
322 &stream->num_ch_in, pcm);
324 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
325 &stream->num_ch_out, pcm);
330 static int intel_pdi_ch_update(struct sdw_intel *sdw)
332 /* First update PCM streams followed by PDM streams */
333 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
334 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
340 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
342 void __iomem *shim = sdw->res->shim;
343 unsigned int link_id = sdw->instance;
346 pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
349 * Program stream parameters to stream SHIM register
350 * This is applicable for PCM stream only.
352 if (pdi->type != SDW_STREAM_PCM)
355 if (pdi->dir == SDW_DATA_DIR_RX)
356 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
358 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
360 pdi_conf |= (pdi->intel_alh_id <<
361 SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
362 pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
363 pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
365 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
369 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
371 void __iomem *alh = sdw->res->alh;
372 unsigned int link_id = sdw->instance;
375 pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
377 /* Program Stream config ALH register */
378 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
380 conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
381 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
383 conf |= ((pdi->ch_count - 1) <<
384 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
386 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
389 static int intel_config_stream(struct sdw_intel *sdw,
390 struct snd_pcm_substream *substream,
391 struct snd_soc_dai *dai,
392 struct snd_pcm_hw_params *hw_params, int link_id)
394 if (sdw->res->ops && sdw->res->ops->config_stream)
395 return sdw->res->ops->config_stream(sdw->res->arg,
396 substream, dai, hw_params, link_id);
402 * bank switch routines
405 static int intel_pre_bank_switch(struct sdw_bus *bus)
407 struct sdw_cdns *cdns = bus_to_cdns(bus);
408 struct sdw_intel *sdw = cdns_to_intel(cdns);
409 void __iomem *shim = sdw->res->shim;
412 /* Write to register only for multi-link */
413 if (!bus->multi_link)
416 /* Read SYNC register */
417 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
418 sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance;
419 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
424 static int intel_post_bank_switch(struct sdw_bus *bus)
426 struct sdw_cdns *cdns = bus_to_cdns(bus);
427 struct sdw_intel *sdw = cdns_to_intel(cdns);
428 void __iomem *shim = sdw->res->shim;
431 /* Write to register only for multi-link */
432 if (!bus->multi_link)
435 /* Read SYNC register */
436 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
439 * post_bank_switch() ops is called from the bus in loop for
440 * all the Masters in the steam with the expectation that
441 * we trigger the bankswitch for the only first Master in the list
442 * and do nothing for the other Masters
444 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
446 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK))
450 * Set SyncGO bit to synchronously trigger a bank switch for
451 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
454 sync_reg |= SDW_SHIM_SYNC_SYNCGO;
456 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
457 SDW_SHIM_SYNC_SYNCGO);
459 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
468 static struct sdw_cdns_port *intel_alloc_port(struct sdw_intel *sdw,
469 u32 ch, u32 dir, bool pcm)
471 struct sdw_cdns *cdns = &sdw->cdns;
472 struct sdw_cdns_port *port = NULL;
475 for (i = 0; i < cdns->num_ports; i++) {
476 if (cdns->ports[i].assigned)
479 port = &cdns->ports[i];
480 port->assigned = true;
481 port->direction = dir;
487 dev_err(cdns->dev, "Unable to find a free port\n");
492 ret = sdw_cdns_alloc_stream(cdns, &cdns->pcm, port, ch, dir);
496 intel_pdi_shim_configure(sdw, port->pdi);
497 sdw_cdns_config_stream(cdns, port, ch, dir, port->pdi);
499 intel_pdi_alh_configure(sdw, port->pdi);
502 ret = sdw_cdns_alloc_stream(cdns, &cdns->pdm, port, ch, dir);
507 port->assigned = false;
514 static void intel_port_cleanup(struct sdw_cdns_dma_data *dma)
518 for (i = 0; i < dma->nr_ports; i++) {
520 dma->port[i]->pdi->assigned = false;
521 dma->port[i]->pdi = NULL;
522 dma->port[i]->assigned = false;
528 static int intel_hw_params(struct snd_pcm_substream *substream,
529 struct snd_pcm_hw_params *params,
530 struct snd_soc_dai *dai)
532 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
533 struct sdw_intel *sdw = cdns_to_intel(cdns);
534 struct sdw_cdns_dma_data *dma;
535 struct sdw_stream_config sconfig;
536 struct sdw_port_config *pconfig;
540 dma = snd_soc_dai_get_dma_data(dai, substream);
544 ch = params_channels(params);
545 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
546 dir = SDW_DATA_DIR_RX;
548 dir = SDW_DATA_DIR_TX;
550 if (dma->stream_type == SDW_STREAM_PDM) {
551 /* TODO: Check whether PDM decimator is already in use */
552 dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pdm, ch, dir);
555 dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pcm, ch, dir);
558 if (!dma->nr_ports) {
559 dev_err(dai->dev, "ports/resources not available\n");
563 dma->port = kcalloc(dma->nr_ports, sizeof(*dma->port), GFP_KERNEL);
567 for (i = 0; i < dma->nr_ports; i++) {
568 dma->port[i] = intel_alloc_port(sdw, ch, dir, pcm);
575 /* Inform DSP about PDI stream number */
576 for (i = 0; i < dma->nr_ports; i++) {
577 ret = intel_config_stream(sdw, substream, dai, params,
578 dma->port[i]->pdi->intel_alh_id);
583 sconfig.direction = dir;
584 sconfig.ch_count = ch;
585 sconfig.frame_rate = params_rate(params);
586 sconfig.type = dma->stream_type;
588 if (dma->stream_type == SDW_STREAM_PDM) {
589 sconfig.frame_rate *= 50;
592 sconfig.bps = snd_pcm_format_width(params_format(params));
595 /* Port configuration */
596 pconfig = kcalloc(dma->nr_ports, sizeof(*pconfig), GFP_KERNEL);
602 for (i = 0; i < dma->nr_ports; i++) {
603 pconfig[i].num = dma->port[i]->num;
604 pconfig[i].ch_mask = (1 << ch) - 1;
607 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
608 pconfig, dma->nr_ports, dma->stream);
610 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
620 intel_port_cleanup(dma);
626 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
628 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
629 struct sdw_cdns_dma_data *dma;
632 dma = snd_soc_dai_get_dma_data(dai, substream);
636 ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
638 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
639 dma->stream->name, ret);
641 intel_port_cleanup(dma);
646 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
647 void *stream, int direction)
649 return cdns_set_sdw_stream(dai, stream, true, direction);
652 static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
653 void *stream, int direction)
655 return cdns_set_sdw_stream(dai, stream, false, direction);
658 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
659 .hw_params = intel_hw_params,
660 .hw_free = intel_hw_free,
661 .shutdown = sdw_cdns_shutdown,
662 .set_sdw_stream = intel_pcm_set_sdw_stream,
665 static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
666 .hw_params = intel_hw_params,
667 .hw_free = intel_hw_free,
668 .shutdown = sdw_cdns_shutdown,
669 .set_sdw_stream = intel_pdm_set_sdw_stream,
672 static const struct snd_soc_component_driver dai_component = {
676 static int intel_create_dai(struct sdw_cdns *cdns,
677 struct snd_soc_dai_driver *dais,
678 enum intel_pdi_type type,
679 u32 num, u32 off, u32 max_ch, bool pcm)
686 /* TODO: Read supported rates/formats from hardware */
687 for (i = off; i < (off + num); i++) {
688 dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d",
693 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
694 dais[i].playback.stream_name =
695 kasprintf(GFP_KERNEL, "SDW%d Tx%d",
697 if (!dais[i].playback.stream_name) {
702 dais[i].playback.channels_min = 1;
703 dais[i].playback.channels_max = max_ch;
704 dais[i].playback.rates = SNDRV_PCM_RATE_48000;
705 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
708 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
709 dais[i].capture.stream_name =
710 kasprintf(GFP_KERNEL, "SDW%d Rx%d",
712 if (!dais[i].capture.stream_name) {
714 kfree(dais[i].playback.stream_name);
718 dais[i].capture.channels_min = 1;
719 dais[i].capture.channels_max = max_ch;
720 dais[i].capture.rates = SNDRV_PCM_RATE_48000;
721 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
724 dais[i].id = SDW_DAI_ID_RANGE_START + i;
727 dais[i].ops = &intel_pcm_dai_ops;
729 dais[i].ops = &intel_pdm_dai_ops;
735 static int intel_register_dai(struct sdw_intel *sdw)
737 struct sdw_cdns *cdns = &sdw->cdns;
738 struct sdw_cdns_streams *stream;
739 struct snd_soc_dai_driver *dais;
740 int num_dai, ret, off = 0;
742 /* DAIs are created based on total number of PDIs supported */
743 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
745 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
749 /* Create PCM DAIs */
752 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, stream->num_in,
753 off, stream->num_ch_in, true);
757 off += cdns->pcm.num_in;
758 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
759 off, stream->num_ch_out, true);
763 off += cdns->pcm.num_out;
764 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
765 off, stream->num_ch_bd, true);
769 /* Create PDM DAIs */
771 off += cdns->pcm.num_bd;
772 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
773 off, stream->num_ch_in, false);
777 off += cdns->pdm.num_in;
778 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
779 off, stream->num_ch_out, false);
783 off += cdns->pdm.num_bd;
784 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
785 off, stream->num_ch_bd, false);
789 return snd_soc_register_component(cdns->dev, &dai_component,
793 static int intel_prop_read(struct sdw_bus *bus)
795 /* Initialize with default handler to read all DisCo properties */
796 sdw_master_read_prop(bus);
798 /* BIOS is not giving some values correctly. So, lets override them */
799 bus->prop.num_freq = 1;
800 bus->prop.freq = devm_kcalloc(bus->dev, bus->prop.num_freq,
801 sizeof(*bus->prop.freq), GFP_KERNEL);
805 bus->prop.freq[0] = bus->prop.max_freq;
806 bus->prop.err_threshold = 5;
811 static struct sdw_master_ops sdw_intel_ops = {
812 .read_prop = sdw_master_read_prop,
813 .xfer_msg = cdns_xfer_msg,
814 .xfer_msg_defer = cdns_xfer_msg_defer,
815 .reset_page_addr = cdns_reset_page_addr,
816 .set_bus_conf = cdns_bus_conf,
817 .pre_bank_switch = intel_pre_bank_switch,
818 .post_bank_switch = intel_post_bank_switch,
824 static int intel_probe(struct platform_device *pdev)
826 struct sdw_cdns_stream_config config;
827 struct sdw_intel *sdw;
830 sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL);
834 sdw->instance = pdev->id;
835 sdw->res = dev_get_platdata(&pdev->dev);
836 sdw->cdns.dev = &pdev->dev;
837 sdw->cdns.registers = sdw->res->registers;
838 sdw->cdns.instance = sdw->instance;
839 sdw->cdns.msg_count = 0;
840 sdw->cdns.bus.dev = &pdev->dev;
841 sdw->cdns.bus.link_id = pdev->id;
843 sdw_cdns_probe(&sdw->cdns);
845 /* Set property read ops */
846 sdw_intel_ops.read_prop = intel_prop_read;
847 sdw->cdns.bus.ops = &sdw_intel_ops;
849 platform_set_drvdata(pdev, sdw);
851 ret = sdw_add_bus_master(&sdw->cdns.bus);
853 dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret);
857 /* Initialize shim and controller */
858 intel_link_power_up(sdw);
859 intel_shim_init(sdw);
861 ret = sdw_cdns_init(&sdw->cdns);
865 ret = sdw_cdns_enable_interrupt(&sdw->cdns);
867 /* Read the PDI config and initialize cadence PDI */
868 intel_pdi_init(sdw, &config);
869 ret = sdw_cdns_pdi_init(&sdw->cdns, config);
873 intel_pdi_ch_update(sdw);
876 ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, sdw_cdns_thread,
877 IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns);
879 dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n",
885 ret = intel_register_dai(sdw);
887 dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret);
888 snd_soc_unregister_component(sdw->cdns.dev);
895 free_irq(sdw->res->irq, sdw);
897 sdw_delete_bus_master(&sdw->cdns.bus);
902 static int intel_remove(struct platform_device *pdev)
904 struct sdw_intel *sdw;
906 sdw = platform_get_drvdata(pdev);
908 free_irq(sdw->res->irq, sdw);
909 snd_soc_unregister_component(sdw->cdns.dev);
910 sdw_delete_bus_master(&sdw->cdns.bus);
915 static struct platform_driver sdw_intel_drv = {
916 .probe = intel_probe,
917 .remove = intel_remove,
924 module_platform_driver(sdw_intel_drv);
926 MODULE_LICENSE("Dual BSD/GPL");
927 MODULE_ALIAS("platform:int-sdw");
928 MODULE_DESCRIPTION("Intel Soundwire Master Driver");