1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
5 * Soundwire Intel Master Driver
8 #include <linux/acpi.h>
9 #include <linux/debugfs.h>
10 #include <linux/delay.h>
12 #include <sound/pcm_params.h>
13 #include <linux/pm_runtime.h>
14 #include <sound/soc.h>
15 #include <linux/soundwire/sdw_registers.h>
16 #include <linux/soundwire/sdw.h>
17 #include <linux/soundwire/sdw_intel.h>
18 #include "cadence_master.h"
22 static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
28 reg_read = readl(base + offset);
29 if ((reg_read & mask) == target)
33 usleep_range(50, 100);
34 } while (timeout != 0);
39 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
41 writel(value, base + offset);
42 return intel_wait_bit(base, offset, mask, 0);
45 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
47 writel(value, base + offset);
48 return intel_wait_bit(base, offset, mask, mask);
54 #ifdef CONFIG_DEBUG_FS
56 #define RD_BUF (2 * PAGE_SIZE)
58 static ssize_t intel_sprintf(void __iomem *mem, bool l,
59 char *buf, size_t pos, unsigned int reg)
64 value = intel_readl(mem, reg);
66 value = intel_readw(mem, reg);
68 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
71 static int intel_reg_show(struct seq_file *s_file, void *data)
73 struct sdw_intel *sdw = s_file->private;
74 void __iomem *s = sdw->link_res->shim;
75 void __iomem *a = sdw->link_res->alh;
79 unsigned int links, reg;
81 buf = kzalloc(RD_BUF, GFP_KERNEL);
85 links = intel_readl(s, SDW_SHIM_LCAP) & SDW_SHIM_LCAP_LCOUNT_MASK;
87 ret = scnprintf(buf, RD_BUF, "Register Value\n");
88 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
90 for (i = 0; i < links; i++) {
91 reg = SDW_SHIM_LCAP + i * 4;
92 ret += intel_sprintf(s, true, buf, ret, reg);
95 for (i = 0; i < links; i++) {
96 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
97 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
98 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
99 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
100 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
101 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
102 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
104 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
107 * the value 10 is the number of PDIs. We will need a
108 * cleanup to remove hard-coded Intel configurations
109 * from cadence_master.c
111 for (j = 0; j < 10; j++) {
112 ret += intel_sprintf(s, false, buf, ret,
113 SDW_SHIM_PCMSYCHM(i, j));
114 ret += intel_sprintf(s, false, buf, ret,
115 SDW_SHIM_PCMSYCHC(i, j));
117 ret += scnprintf(buf + ret, RD_BUF - ret, "\n IOCTL, CTMCTL\n");
119 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
120 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
123 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
124 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
125 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
127 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
128 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
129 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
131 seq_printf(s_file, "%s", buf);
136 DEFINE_SHOW_ATTRIBUTE(intel_reg);
138 static int intel_set_m_datamode(void *data, u64 value)
140 struct sdw_intel *sdw = data;
141 struct sdw_bus *bus = &sdw->cdns.bus;
143 if (value > SDW_PORT_DATA_MODE_STATIC_1)
146 /* Userspace changed the hardware state behind the kernel's back */
147 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
149 bus->params.m_data_mode = value;
153 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL,
154 intel_set_m_datamode, "%llu\n");
156 static int intel_set_s_datamode(void *data, u64 value)
158 struct sdw_intel *sdw = data;
159 struct sdw_bus *bus = &sdw->cdns.bus;
161 if (value > SDW_PORT_DATA_MODE_STATIC_1)
164 /* Userspace changed the hardware state behind the kernel's back */
165 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
167 bus->params.s_data_mode = value;
171 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL,
172 intel_set_s_datamode, "%llu\n");
174 static void intel_debugfs_init(struct sdw_intel *sdw)
176 struct dentry *root = sdw->cdns.bus.debugfs;
181 sdw->debugfs = debugfs_create_dir("intel-sdw", root);
183 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
186 debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw,
187 &intel_set_m_datamode_fops);
189 debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw,
190 &intel_set_s_datamode_fops);
192 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
195 static void intel_debugfs_exit(struct sdw_intel *sdw)
197 debugfs_remove_recursive(sdw->debugfs);
200 static void intel_debugfs_init(struct sdw_intel *sdw) {}
201 static void intel_debugfs_exit(struct sdw_intel *sdw) {}
202 #endif /* CONFIG_DEBUG_FS */
207 /* this needs to be called with shim_lock */
208 static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
210 void __iomem *shim = sdw->link_res->shim;
211 unsigned int link_id = sdw->instance;
214 /* Switch to MIP from Glue logic */
215 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
217 ioctl &= ~(SDW_SHIM_IOCTL_DOE);
218 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
219 usleep_range(10, 15);
221 ioctl &= ~(SDW_SHIM_IOCTL_DO);
222 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
223 usleep_range(10, 15);
225 ioctl |= (SDW_SHIM_IOCTL_MIF);
226 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
227 usleep_range(10, 15);
229 ioctl &= ~(SDW_SHIM_IOCTL_BKE);
230 ioctl &= ~(SDW_SHIM_IOCTL_COE);
231 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
232 usleep_range(10, 15);
234 /* at this point Master IP has full control of the I/Os */
237 /* this needs to be called with shim_lock */
238 static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
240 unsigned int link_id = sdw->instance;
241 void __iomem *shim = sdw->link_res->shim;
245 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
246 ioctl |= SDW_SHIM_IOCTL_BKE;
247 ioctl |= SDW_SHIM_IOCTL_COE;
248 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
249 usleep_range(10, 15);
251 ioctl &= ~(SDW_SHIM_IOCTL_MIF);
252 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
253 usleep_range(10, 15);
255 /* at this point Integration Glue has full control of the I/Os */
258 /* this needs to be called with shim_lock */
259 static void intel_shim_init(struct sdw_intel *sdw)
261 void __iomem *shim = sdw->link_res->shim;
262 unsigned int link_id = sdw->instance;
263 u16 ioctl = 0, act = 0;
265 /* Initialize Shim */
266 ioctl |= SDW_SHIM_IOCTL_BKE;
267 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
268 usleep_range(10, 15);
270 ioctl |= SDW_SHIM_IOCTL_WPDD;
271 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
272 usleep_range(10, 15);
274 ioctl |= SDW_SHIM_IOCTL_DO;
275 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
276 usleep_range(10, 15);
278 ioctl |= SDW_SHIM_IOCTL_DOE;
279 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
280 usleep_range(10, 15);
282 intel_shim_glue_to_master_ip(sdw);
284 u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);
285 act |= SDW_SHIM_CTMCTL_DACTQE;
286 act |= SDW_SHIM_CTMCTL_DODS;
287 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
288 usleep_range(10, 15);
291 static int intel_shim_check_wake(struct sdw_intel *sdw)
296 shim = sdw->link_res->shim;
297 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
299 return wake_sts & BIT(sdw->instance);
302 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
304 void __iomem *shim = sdw->link_res->shim;
305 unsigned int link_id = sdw->instance;
306 u16 wake_en, wake_sts;
308 mutex_lock(sdw->link_res->shim_lock);
309 wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
312 /* Enable the wakeup */
313 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
314 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
316 /* Disable the wake up interrupt */
317 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
318 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
320 /* Clear wake status */
321 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
322 wake_sts |= (SDW_SHIM_WAKESTS_STATUS << link_id);
323 intel_writew(shim, SDW_SHIM_WAKESTS, wake_sts);
325 mutex_unlock(sdw->link_res->shim_lock);
328 static bool intel_check_cmdsync_unlocked(struct sdw_intel *sdw)
330 void __iomem *shim = sdw->link_res->shim;
333 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
334 return !!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK);
337 static int intel_link_power_up(struct sdw_intel *sdw)
339 unsigned int link_id = sdw->instance;
340 void __iomem *shim = sdw->link_res->shim;
341 u32 *shim_mask = sdw->link_res->shim_mask;
342 struct sdw_bus *bus = &sdw->cdns.bus;
343 struct sdw_master_prop *prop = &bus->prop;
344 u32 spa_mask, cpa_mask;
350 mutex_lock(sdw->link_res->shim_lock);
353 * The hardware relies on an internal counter, typically 4kHz,
354 * to generate the SoundWire SSP - which defines a 'safe'
355 * synchronization point between commands and audio transport
356 * and allows for multi link synchronization. The SYNCPRD value
357 * is only dependent on the oscillator clock provided to
358 * the IP, so adjust based on _DSD properties reported in DSDT
359 * tables. The values reported are based on either 24MHz
360 * (CNL/CML) or 38.4 MHz (ICL/TGL+).
362 if (prop->mclk_freq % 6000000)
363 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
365 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
368 dev_dbg(sdw->cdns.dev, "powering up all links\n");
370 /* we first need to program the SyncPRD/CPU registers */
371 dev_dbg(sdw->cdns.dev,
372 "first link up, programming SYNCPRD\n");
374 /* set SyncPRD period */
375 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
376 u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);
378 /* Set SyncCPU bit */
379 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
380 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
382 /* Link power up sequence */
383 link_control = intel_readl(shim, SDW_SHIM_LCTL);
385 /* only power-up enabled links */
386 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);
387 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
389 link_control |= spa_mask;
391 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
393 dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);
397 /* SyncCPU will change once link is active */
398 ret = intel_wait_bit(shim, SDW_SHIM_SYNC,
399 SDW_SHIM_SYNC_SYNCCPU, 0);
401 dev_err(sdw->cdns.dev,
402 "Failed to set SHIM_SYNC: %d\n", ret);
407 *shim_mask |= BIT(link_id);
409 sdw->cdns.link_up = true;
411 intel_shim_init(sdw);
414 mutex_unlock(sdw->link_res->shim_lock);
419 static int intel_link_power_down(struct sdw_intel *sdw)
421 u32 link_control, spa_mask, cpa_mask;
422 unsigned int link_id = sdw->instance;
423 void __iomem *shim = sdw->link_res->shim;
424 u32 *shim_mask = sdw->link_res->shim_mask;
427 mutex_lock(sdw->link_res->shim_lock);
429 if (!(*shim_mask & BIT(link_id)))
430 dev_err(sdw->cdns.dev,
431 "%s: Unbalanced power-up/down calls\n", __func__);
433 sdw->cdns.link_up = false;
435 intel_shim_master_ip_to_glue(sdw);
437 *shim_mask &= ~BIT(link_id);
441 dev_dbg(sdw->cdns.dev, "powering down all links\n");
443 /* Link power down sequence */
444 link_control = intel_readl(shim, SDW_SHIM_LCTL);
446 /* only power-down enabled links */
447 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask);
448 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
450 link_control &= spa_mask;
452 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
454 dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__);
457 * we leave the sdw->cdns.link_up flag as false since we've disabled
458 * the link at this point and cannot handle interrupts any longer.
463 mutex_unlock(sdw->link_res->shim_lock);
468 static void intel_shim_sync_arm(struct sdw_intel *sdw)
470 void __iomem *shim = sdw->link_res->shim;
473 mutex_lock(sdw->link_res->shim_lock);
475 /* update SYNC register */
476 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
477 sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);
478 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
480 mutex_unlock(sdw->link_res->shim_lock);
483 static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw)
485 void __iomem *shim = sdw->link_res->shim;
488 /* Read SYNC register */
489 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
492 * Set SyncGO bit to synchronously trigger a bank switch for
493 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
496 sync_reg |= SDW_SHIM_SYNC_SYNCGO;
498 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
503 static int intel_shim_sync_go(struct sdw_intel *sdw)
507 mutex_lock(sdw->link_res->shim_lock);
509 ret = intel_shim_sync_go_unlocked(sdw);
511 mutex_unlock(sdw->link_res->shim_lock);
519 static void intel_pdi_init(struct sdw_intel *sdw,
520 struct sdw_cdns_stream_config *config)
522 void __iomem *shim = sdw->link_res->shim;
523 unsigned int link_id = sdw->instance;
526 /* PCM Stream Capability */
527 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
529 config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap);
530 config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap);
531 config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap);
533 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
534 config->pcm_bd, config->pcm_in, config->pcm_out);
538 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num)
540 void __iomem *shim = sdw->link_res->shim;
541 unsigned int link_id = sdw->instance;
544 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
547 * WORKAROUND: on all existing Intel controllers, pdi
548 * number 2 reports channel count as 1 even though it
549 * supports 8 channels. Performing hardcoding for pdi
555 /* zero based values for channel count in register */
561 static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
562 struct sdw_cdns_pdi *pdi,
563 unsigned int num_pdi,
564 unsigned int *num_ch)
568 for (i = 0; i < num_pdi; i++) {
569 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num);
570 ch_count += pdi->ch_count;
578 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
579 struct sdw_cdns_streams *stream)
581 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
584 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
587 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
588 &stream->num_ch_out);
594 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
596 void __iomem *shim = sdw->link_res->shim;
597 unsigned int link_id = sdw->instance;
600 /* the Bulk and PCM streams are not contiguous */
601 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
603 pdi->intel_alh_id += 2;
606 * Program stream parameters to stream SHIM register
607 * This is applicable for PCM stream only.
609 if (pdi->type != SDW_STREAM_PCM)
612 if (pdi->dir == SDW_DATA_DIR_RX)
613 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
615 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
617 u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM);
618 u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN);
619 u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN);
621 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
625 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
627 void __iomem *alh = sdw->link_res->alh;
628 unsigned int link_id = sdw->instance;
631 /* the Bulk and PCM streams are not contiguous */
632 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
634 pdi->intel_alh_id += 2;
636 /* Program Stream config ALH register */
637 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
639 u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT);
640 u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN);
642 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
645 static int intel_params_stream(struct sdw_intel *sdw,
647 struct snd_soc_dai *dai,
648 struct snd_pcm_hw_params *hw_params,
649 int link_id, int alh_stream_id)
651 struct sdw_intel_link_res *res = sdw->link_res;
652 struct sdw_intel_stream_params_data params_data;
654 params_data.stream = stream; /* direction */
655 params_data.dai = dai;
656 params_data.hw_params = hw_params;
657 params_data.link_id = link_id;
658 params_data.alh_stream_id = alh_stream_id;
660 if (res->ops && res->ops->params_stream && res->dev)
661 return res->ops->params_stream(res->dev,
666 static int intel_free_stream(struct sdw_intel *sdw,
668 struct snd_soc_dai *dai,
671 struct sdw_intel_link_res *res = sdw->link_res;
672 struct sdw_intel_stream_free_data free_data;
674 free_data.stream = stream; /* direction */
676 free_data.link_id = link_id;
678 if (res->ops && res->ops->free_stream && res->dev)
679 return res->ops->free_stream(res->dev,
689 static int intel_hw_params(struct snd_pcm_substream *substream,
690 struct snd_pcm_hw_params *params,
691 struct snd_soc_dai *dai)
693 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
694 struct sdw_intel *sdw = cdns_to_intel(cdns);
695 struct sdw_cdns_dai_runtime *dai_runtime;
696 struct sdw_cdns_pdi *pdi;
697 struct sdw_stream_config sconfig;
698 struct sdw_port_config *pconfig;
702 dai_runtime = cdns->dai_runtime_array[dai->id];
706 ch = params_channels(params);
707 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
708 dir = SDW_DATA_DIR_RX;
710 dir = SDW_DATA_DIR_TX;
712 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
719 /* do run-time configurations for SHIM, ALH and PDI/PORT */
720 intel_pdi_shim_configure(sdw, pdi);
721 intel_pdi_alh_configure(sdw, pdi);
722 sdw_cdns_config_stream(cdns, ch, dir, pdi);
724 /* store pdi and hw_params, may be needed in prepare step */
725 dai_runtime->paused = false;
726 dai_runtime->suspended = false;
727 dai_runtime->pdi = pdi;
729 /* Inform DSP about PDI stream number */
730 ret = intel_params_stream(sdw, substream->stream, dai, params,
736 sconfig.direction = dir;
737 sconfig.ch_count = ch;
738 sconfig.frame_rate = params_rate(params);
739 sconfig.type = dai_runtime->stream_type;
741 sconfig.bps = snd_pcm_format_width(params_format(params));
743 /* Port configuration */
744 pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
750 pconfig->num = pdi->num;
751 pconfig->ch_mask = (1 << ch) - 1;
753 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
754 pconfig, 1, dai_runtime->stream);
756 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
763 static int intel_prepare(struct snd_pcm_substream *substream,
764 struct snd_soc_dai *dai)
766 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
767 struct sdw_intel *sdw = cdns_to_intel(cdns);
768 struct sdw_cdns_dai_runtime *dai_runtime;
772 dai_runtime = cdns->dai_runtime_array[dai->id];
774 dev_err(dai->dev, "failed to get dai runtime in %s\n",
779 if (dai_runtime->suspended) {
780 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
781 struct snd_pcm_hw_params *hw_params;
783 hw_params = &rtd->dpcm[substream->stream].hw_params;
785 dai_runtime->suspended = false;
788 * .prepare() is called after system resume, where we
789 * need to reinitialize the SHIM/ALH/Cadence IP.
790 * .prepare() is also called to deal with underflows,
791 * but in those cases we cannot touch ALH/SHIM
795 /* configure stream */
796 ch = params_channels(hw_params);
797 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
798 dir = SDW_DATA_DIR_RX;
800 dir = SDW_DATA_DIR_TX;
802 intel_pdi_shim_configure(sdw, dai_runtime->pdi);
803 intel_pdi_alh_configure(sdw, dai_runtime->pdi);
804 sdw_cdns_config_stream(cdns, ch, dir, dai_runtime->pdi);
806 /* Inform DSP about PDI stream number */
807 ret = intel_params_stream(sdw, substream->stream, dai,
810 dai_runtime->pdi->intel_alh_id);
817 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
819 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
820 struct sdw_intel *sdw = cdns_to_intel(cdns);
821 struct sdw_cdns_dai_runtime *dai_runtime;
824 dai_runtime = cdns->dai_runtime_array[dai->id];
829 * The sdw stream state will transition to RELEASED when stream->
830 * master_list is empty. So the stream state will transition to
831 * DEPREPARED for the first cpu-dai and to RELEASED for the last
834 ret = sdw_stream_remove_master(&cdns->bus, dai_runtime->stream);
836 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
837 dai_runtime->stream->name, ret);
841 ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
843 dev_err(dai->dev, "intel_free_stream: failed %d\n", ret);
847 dai_runtime->pdi = NULL;
852 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
853 void *stream, int direction)
855 return cdns_set_sdw_stream(dai, stream, direction);
858 static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
861 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
862 struct sdw_cdns_dai_runtime *dai_runtime;
864 dai_runtime = cdns->dai_runtime_array[dai->id];
866 return ERR_PTR(-EINVAL);
868 return dai_runtime->stream;
871 static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
873 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
874 struct sdw_intel *sdw = cdns_to_intel(cdns);
875 struct sdw_intel_link_res *res = sdw->link_res;
876 struct sdw_cdns_dai_runtime *dai_runtime;
880 * The .trigger callback is used to send required IPC to audio
881 * firmware. The .free_stream callback will still be called
882 * by intel_free_stream() in the TRIGGER_SUSPEND case.
884 if (res->ops && res->ops->trigger)
885 res->ops->trigger(dai, cmd, substream->stream);
887 dai_runtime = cdns->dai_runtime_array[dai->id];
889 dev_err(dai->dev, "failed to get dai runtime in %s\n",
895 case SNDRV_PCM_TRIGGER_SUSPEND:
898 * The .prepare callback is used to deal with xruns and resume operations.
899 * In the case of xruns, the DMAs and SHIM registers cannot be touched,
900 * but for resume operations the DMAs and SHIM registers need to be initialized.
901 * the .trigger callback is used to track the suspend case only.
904 dai_runtime->suspended = true;
906 ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
909 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
910 dai_runtime->paused = true;
912 case SNDRV_PCM_TRIGGER_STOP:
913 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
914 dai_runtime->paused = false;
923 static int intel_component_probe(struct snd_soc_component *component)
928 * make sure the device is pm_runtime_active before initiating
929 * bus transactions during the card registration.
930 * We use pm_runtime_resume() here, without taking a reference
931 * and releasing it immediately.
933 ret = pm_runtime_resume(component->dev);
934 if (ret < 0 && ret != -EACCES)
940 static int intel_component_dais_suspend(struct snd_soc_component *component)
942 struct snd_soc_dai *dai;
945 * In the corner case where a SUSPEND happens during a PAUSE, the ALSA core
946 * does not throw the TRIGGER_SUSPEND. This leaves the DAIs in an unbalanced state.
947 * Since the component suspend is called last, we can trap this corner case
948 * and force the DAIs to release their resources.
950 for_each_component_dais(component, dai) {
951 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
952 struct sdw_intel *sdw = cdns_to_intel(cdns);
953 struct sdw_cdns_dai_runtime *dai_runtime;
956 dai_runtime = cdns->dai_runtime_array[dai->id];
961 if (dai_runtime->suspended)
964 if (dai_runtime->paused) {
965 dai_runtime->suspended = true;
967 ret = intel_free_stream(sdw, dai_runtime->direction, dai, sdw->instance);
976 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
977 .hw_params = intel_hw_params,
978 .prepare = intel_prepare,
979 .hw_free = intel_hw_free,
980 .trigger = intel_trigger,
981 .set_stream = intel_pcm_set_sdw_stream,
982 .get_stream = intel_get_sdw_stream,
985 static const struct snd_soc_component_driver dai_component = {
987 .probe = intel_component_probe,
988 .suspend = intel_component_dais_suspend,
989 .legacy_dai_naming = 1,
992 static int intel_create_dai(struct sdw_cdns *cdns,
993 struct snd_soc_dai_driver *dais,
994 enum intel_pdi_type type,
995 u32 num, u32 off, u32 max_ch)
1002 for (i = off; i < (off + num); i++) {
1003 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
1009 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
1010 dais[i].playback.channels_min = 1;
1011 dais[i].playback.channels_max = max_ch;
1014 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
1015 dais[i].capture.channels_min = 1;
1016 dais[i].capture.channels_max = max_ch;
1019 dais[i].ops = &intel_pcm_dai_ops;
1025 static int intel_register_dai(struct sdw_intel *sdw)
1027 struct sdw_cdns_dai_runtime **dai_runtime_array;
1028 struct sdw_cdns_stream_config config;
1029 struct sdw_cdns *cdns = &sdw->cdns;
1030 struct sdw_cdns_streams *stream;
1031 struct snd_soc_dai_driver *dais;
1032 int num_dai, ret, off = 0;
1034 /* Read the PDI config and initialize cadence PDI */
1035 intel_pdi_init(sdw, &config);
1036 ret = sdw_cdns_pdi_init(cdns, config);
1040 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm);
1042 /* DAIs are created based on total number of PDIs supported */
1043 num_dai = cdns->pcm.num_pdi;
1045 dai_runtime_array = devm_kcalloc(cdns->dev, num_dai,
1046 sizeof(struct sdw_cdns_dai_runtime *),
1048 if (!dai_runtime_array)
1050 cdns->dai_runtime_array = dai_runtime_array;
1052 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
1056 /* Create PCM DAIs */
1057 stream = &cdns->pcm;
1059 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
1060 off, stream->num_ch_in);
1064 off += cdns->pcm.num_in;
1065 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
1066 off, stream->num_ch_out);
1070 off += cdns->pcm.num_out;
1071 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1072 off, stream->num_ch_bd);
1076 return devm_snd_soc_register_component(cdns->dev, &dai_component,
1081 const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops = {
1082 .debugfs_init = intel_debugfs_init,
1083 .debugfs_exit = intel_debugfs_exit,
1085 .register_dai = intel_register_dai,
1087 .check_clock_stop = intel_check_clock_stop,
1088 .start_bus = intel_start_bus,
1089 .start_bus_after_reset = intel_start_bus_after_reset,
1090 .start_bus_after_clock_stop = intel_start_bus_after_clock_stop,
1091 .stop_bus = intel_stop_bus,
1093 .link_power_up = intel_link_power_up,
1094 .link_power_down = intel_link_power_down,
1096 .shim_check_wake = intel_shim_check_wake,
1097 .shim_wake = intel_shim_wake,
1099 .pre_bank_switch = intel_pre_bank_switch,
1100 .post_bank_switch = intel_post_bank_switch,
1102 .sync_arm = intel_shim_sync_arm,
1103 .sync_go_unlocked = intel_shim_sync_go_unlocked,
1104 .sync_go = intel_shim_sync_go,
1105 .sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked,
1107 EXPORT_SYMBOL_NS(sdw_intel_cnl_hw_ops, SOUNDWIRE_INTEL);