2 * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/init.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_domain.h>
22 #include <linux/regmap.h>
23 #include <linux/soc/mediatek/infracfg.h>
24 #include <linux/regulator/consumer.h>
25 #include <dt-bindings/power/mt8173-power.h>
27 #define SPM_VDE_PWR_CON 0x0210
28 #define SPM_MFG_PWR_CON 0x0214
29 #define SPM_VEN_PWR_CON 0x0230
30 #define SPM_ISP_PWR_CON 0x0238
31 #define SPM_DIS_PWR_CON 0x023c
32 #define SPM_VEN2_PWR_CON 0x0298
33 #define SPM_AUDIO_PWR_CON 0x029c
34 #define SPM_MFG_2D_PWR_CON 0x02c0
35 #define SPM_MFG_ASYNC_PWR_CON 0x02c4
36 #define SPM_USB_PWR_CON 0x02cc
37 #define SPM_PWR_STATUS 0x060c
38 #define SPM_PWR_STATUS_2ND 0x0610
40 #define PWR_RST_B_BIT BIT(0)
41 #define PWR_ISO_BIT BIT(1)
42 #define PWR_ON_BIT BIT(2)
43 #define PWR_ON_2ND_BIT BIT(3)
44 #define PWR_CLK_DIS_BIT BIT(4)
46 #define PWR_STATUS_DISP BIT(3)
47 #define PWR_STATUS_MFG BIT(4)
48 #define PWR_STATUS_ISP BIT(5)
49 #define PWR_STATUS_VDEC BIT(7)
50 #define PWR_STATUS_VENC_LT BIT(20)
51 #define PWR_STATUS_VENC BIT(21)
52 #define PWR_STATUS_MFG_2D BIT(22)
53 #define PWR_STATUS_MFG_ASYNC BIT(23)
54 #define PWR_STATUS_AUDIO BIT(24)
55 #define PWR_STATUS_USB BIT(25)
68 struct scp_domain_data {
73 u32 sram_pdn_ack_bits;
75 enum clk_id clk_id[MAX_CLKS];
79 static const struct scp_domain_data scp_domain_data[] __initconst = {
80 [MT8173_POWER_DOMAIN_VDEC] = {
82 .sta_mask = PWR_STATUS_VDEC,
83 .ctl_offs = SPM_VDE_PWR_CON,
84 .sram_pdn_bits = GENMASK(11, 8),
85 .sram_pdn_ack_bits = GENMASK(12, 12),
86 .clk_id = {MT8173_CLK_MM},
88 [MT8173_POWER_DOMAIN_VENC] = {
90 .sta_mask = PWR_STATUS_VENC,
91 .ctl_offs = SPM_VEN_PWR_CON,
92 .sram_pdn_bits = GENMASK(11, 8),
93 .sram_pdn_ack_bits = GENMASK(15, 12),
94 .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
96 [MT8173_POWER_DOMAIN_ISP] = {
98 .sta_mask = PWR_STATUS_ISP,
99 .ctl_offs = SPM_ISP_PWR_CON,
100 .sram_pdn_bits = GENMASK(11, 8),
101 .sram_pdn_ack_bits = GENMASK(13, 12),
102 .clk_id = {MT8173_CLK_MM},
104 [MT8173_POWER_DOMAIN_MM] = {
106 .sta_mask = PWR_STATUS_DISP,
107 .ctl_offs = SPM_DIS_PWR_CON,
108 .sram_pdn_bits = GENMASK(11, 8),
109 .sram_pdn_ack_bits = GENMASK(12, 12),
110 .clk_id = {MT8173_CLK_MM},
111 .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
112 MT8173_TOP_AXI_PROT_EN_MM_M1,
114 [MT8173_POWER_DOMAIN_VENC_LT] = {
116 .sta_mask = PWR_STATUS_VENC_LT,
117 .ctl_offs = SPM_VEN2_PWR_CON,
118 .sram_pdn_bits = GENMASK(11, 8),
119 .sram_pdn_ack_bits = GENMASK(15, 12),
120 .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
122 [MT8173_POWER_DOMAIN_AUDIO] = {
124 .sta_mask = PWR_STATUS_AUDIO,
125 .ctl_offs = SPM_AUDIO_PWR_CON,
126 .sram_pdn_bits = GENMASK(11, 8),
127 .sram_pdn_ack_bits = GENMASK(15, 12),
128 .clk_id = {MT8173_CLK_NONE},
130 [MT8173_POWER_DOMAIN_USB] = {
132 .sta_mask = PWR_STATUS_USB,
133 .ctl_offs = SPM_USB_PWR_CON,
134 .sram_pdn_bits = GENMASK(11, 8),
135 .sram_pdn_ack_bits = GENMASK(15, 12),
136 .clk_id = {MT8173_CLK_NONE},
137 .active_wakeup = true,
139 [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
141 .sta_mask = PWR_STATUS_MFG_ASYNC,
142 .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
143 .sram_pdn_bits = GENMASK(11, 8),
144 .sram_pdn_ack_bits = 0,
145 .clk_id = {MT8173_CLK_MFG},
147 [MT8173_POWER_DOMAIN_MFG_2D] = {
149 .sta_mask = PWR_STATUS_MFG_2D,
150 .ctl_offs = SPM_MFG_2D_PWR_CON,
151 .sram_pdn_bits = GENMASK(11, 8),
152 .sram_pdn_ack_bits = GENMASK(13, 12),
153 .clk_id = {MT8173_CLK_NONE},
155 [MT8173_POWER_DOMAIN_MFG] = {
157 .sta_mask = PWR_STATUS_MFG,
158 .ctl_offs = SPM_MFG_PWR_CON,
159 .sram_pdn_bits = GENMASK(13, 8),
160 .sram_pdn_ack_bits = GENMASK(21, 16),
161 .clk_id = {MT8173_CLK_NONE},
162 .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
163 MT8173_TOP_AXI_PROT_EN_MFG_M0 |
164 MT8173_TOP_AXI_PROT_EN_MFG_M1 |
165 MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
169 #define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
174 struct generic_pm_domain genpd;
176 struct clk *clk[MAX_CLKS];
178 void __iomem *ctl_addr;
180 u32 sram_pdn_ack_bits;
183 struct regulator *supply;
187 struct scp_domain domains[NUM_DOMAINS];
188 struct genpd_onecell_data pd_data;
191 struct regmap *infracfg;
194 static int scpsys_domain_is_on(struct scp_domain *scpd)
196 struct scp *scp = scpd->scp;
198 u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask;
199 u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask;
202 * A domain is on when both status bits are set. If only one is set
203 * return an error. This happens while powering up a domain
206 if (status && status2)
208 if (!status && !status2)
214 static int scpsys_power_on(struct generic_pm_domain *genpd)
216 struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
217 struct scp *scp = scpd->scp;
218 unsigned long timeout;
220 void __iomem *ctl_addr = scpd->ctl_addr;
221 u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
227 ret = regulator_enable(scpd->supply);
232 for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
233 ret = clk_prepare_enable(scpd->clk[i]);
235 for (--i; i >= 0; i--)
236 clk_disable_unprepare(scpd->clk[i]);
242 val = readl(ctl_addr);
244 writel(val, ctl_addr);
245 val |= PWR_ON_2ND_BIT;
246 writel(val, ctl_addr);
248 /* wait until PWR_ACK = 1 */
249 timeout = jiffies + HZ;
252 ret = scpsys_domain_is_on(scpd);
263 if (time_after(jiffies, timeout))
267 val &= ~PWR_CLK_DIS_BIT;
268 writel(val, ctl_addr);
271 writel(val, ctl_addr);
273 val |= PWR_RST_B_BIT;
274 writel(val, ctl_addr);
276 val &= ~scpd->sram_pdn_bits;
277 writel(val, ctl_addr);
279 /* wait until SRAM_PDN_ACK all 0 */
280 timeout = jiffies + HZ;
282 while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
291 if (time_after(jiffies, timeout))
295 if (scpd->bus_prot_mask) {
296 ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
297 scpd->bus_prot_mask);
305 for (i = MAX_CLKS - 1; i >= 0; i--) {
307 clk_disable_unprepare(scpd->clk[i]);
311 regulator_disable(scpd->supply);
313 dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
318 static int scpsys_power_off(struct generic_pm_domain *genpd)
320 struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
321 struct scp *scp = scpd->scp;
322 unsigned long timeout;
324 void __iomem *ctl_addr = scpd->ctl_addr;
325 u32 pdn_ack = scpd->sram_pdn_ack_bits;
330 if (scpd->bus_prot_mask) {
331 ret = mtk_infracfg_set_bus_protection(scp->infracfg,
332 scpd->bus_prot_mask);
337 val = readl(ctl_addr);
338 val |= scpd->sram_pdn_bits;
339 writel(val, ctl_addr);
341 /* wait until SRAM_PDN_ACK all 1 */
342 timeout = jiffies + HZ;
344 while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
352 if (time_after(jiffies, timeout))
357 writel(val, ctl_addr);
359 val &= ~PWR_RST_B_BIT;
360 writel(val, ctl_addr);
362 val |= PWR_CLK_DIS_BIT;
363 writel(val, ctl_addr);
366 writel(val, ctl_addr);
368 val &= ~PWR_ON_2ND_BIT;
369 writel(val, ctl_addr);
371 /* wait until PWR_ACK = 0 */
372 timeout = jiffies + HZ;
375 ret = scpsys_domain_is_on(scpd);
386 if (time_after(jiffies, timeout))
390 for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
391 clk_disable_unprepare(scpd->clk[i]);
394 regulator_disable(scpd->supply);
399 dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
404 static bool scpsys_active_wakeup(struct device *dev)
406 struct generic_pm_domain *genpd;
407 struct scp_domain *scpd;
409 genpd = pd_to_genpd(dev->pm_domain);
410 scpd = container_of(genpd, struct scp_domain, genpd);
412 return scpd->active_wakeup;
415 static int __init scpsys_probe(struct platform_device *pdev)
417 struct genpd_onecell_data *pd_data;
418 struct resource *res;
421 struct clk *clk[MT8173_CLK_MAX];
423 scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
427 scp->dev = &pdev->dev;
429 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
430 scp->base = devm_ioremap_resource(&pdev->dev, res);
431 if (IS_ERR(scp->base))
432 return PTR_ERR(scp->base);
434 pd_data = &scp->pd_data;
436 pd_data->domains = devm_kzalloc(&pdev->dev,
437 sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
438 if (!pd_data->domains)
441 clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
442 if (IS_ERR(clk[MT8173_CLK_MM]))
443 return PTR_ERR(clk[MT8173_CLK_MM]);
445 clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
446 if (IS_ERR(clk[MT8173_CLK_MFG]))
447 return PTR_ERR(clk[MT8173_CLK_MFG]);
449 clk[MT8173_CLK_VENC] = devm_clk_get(&pdev->dev, "venc");
450 if (IS_ERR(clk[MT8173_CLK_VENC]))
451 return PTR_ERR(clk[MT8173_CLK_VENC]);
453 clk[MT8173_CLK_VENC_LT] = devm_clk_get(&pdev->dev, "venc_lt");
454 if (IS_ERR(clk[MT8173_CLK_VENC_LT]))
455 return PTR_ERR(clk[MT8173_CLK_VENC_LT]);
457 scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
459 if (IS_ERR(scp->infracfg)) {
460 dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
461 PTR_ERR(scp->infracfg));
462 return PTR_ERR(scp->infracfg);
465 for (i = 0; i < NUM_DOMAINS; i++) {
466 struct scp_domain *scpd = &scp->domains[i];
467 const struct scp_domain_data *data = &scp_domain_data[i];
469 scpd->supply = devm_regulator_get_optional(&pdev->dev, data->name);
470 if (IS_ERR(scpd->supply)) {
471 if (PTR_ERR(scpd->supply) == -ENODEV)
474 return PTR_ERR(scpd->supply);
478 pd_data->num_domains = NUM_DOMAINS;
480 for (i = 0; i < NUM_DOMAINS; i++) {
481 struct scp_domain *scpd = &scp->domains[i];
482 struct generic_pm_domain *genpd = &scpd->genpd;
483 const struct scp_domain_data *data = &scp_domain_data[i];
485 pd_data->domains[i] = genpd;
488 scpd->sta_mask = data->sta_mask;
489 scpd->ctl_addr = scp->base + data->ctl_offs;
490 scpd->sram_pdn_bits = data->sram_pdn_bits;
491 scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
492 scpd->bus_prot_mask = data->bus_prot_mask;
493 scpd->active_wakeup = data->active_wakeup;
494 for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++)
495 scpd->clk[j] = clk[data->clk_id[j]];
497 genpd->name = data->name;
498 genpd->power_off = scpsys_power_off;
499 genpd->power_on = scpsys_power_on;
500 genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
503 * Initially turn on all domains to make the domains usable
504 * with !CONFIG_PM and to get the hardware in sync with the
505 * software. The unused domains will be switched off during
508 genpd->power_on(genpd);
510 pm_genpd_init(genpd, NULL, false);
514 * We are not allowed to fail here since there is no way to unregister
515 * a power domain. Once registered above we have to keep the domains
519 ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
520 pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
521 if (ret && IS_ENABLED(CONFIG_PM))
522 dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
524 ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
525 pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
526 if (ret && IS_ENABLED(CONFIG_PM))
527 dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
529 ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
531 dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
536 static const struct of_device_id of_scpsys_match_tbl[] = {
538 .compatible = "mediatek,mt8173-scpsys",
544 static struct platform_driver scpsys_drv = {
546 .name = "mtk-scpsys",
547 .owner = THIS_MODULE,
548 .of_match_table = of_match_ptr(of_scpsys_match_tbl),
551 builtin_platform_driver_probe(scpsys_drv, scpsys_probe);