1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
5 * Authors: Shlomi Gridish <gridish@freescale.com>
6 * Li Yang <leoli@freescale.com>
7 * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
10 * General Purpose functions for the global management of the
13 #include <linux/bitmap.h>
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
17 #include <linux/param.h>
18 #include <linux/string.h>
19 #include <linux/spinlock.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/crc32.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/of_platform.h>
30 #include <asm/pgtable.h>
31 #include <soc/fsl/qe/immap_qe.h>
32 #include <soc/fsl/qe/qe.h>
34 #include <asm/rheap.h>
36 static void qe_snums_init(void);
37 static int qe_sdma_init(void);
39 static DEFINE_SPINLOCK(qe_lock);
40 DEFINE_SPINLOCK(cmxgcr_lock);
41 EXPORT_SYMBOL(cmxgcr_lock);
43 /* We allocate this here because it is used almost exclusively for
44 * the communication processor devices.
46 struct qe_immap __iomem *qe_immr;
47 EXPORT_SYMBOL(qe_immr);
49 static u8 snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
50 static DECLARE_BITMAP(snum_state, QE_NUM_OF_SNUM);
51 static unsigned int qe_num_of_snum;
53 static phys_addr_t qebase = -1;
55 static struct device_node *qe_get_device_node(void)
57 struct device_node *qe;
60 * Newer device trees have an "fsl,qe" compatible property for the QE
61 * node, but we still need to support older device trees.
63 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
66 return of_find_node_by_type(NULL, "qe");
69 static phys_addr_t get_qe_base(void)
71 struct device_node *qe;
78 qe = qe_get_device_node();
82 ret = of_address_to_resource(qe, 0, &res);
93 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
97 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
98 QE_CR_PROTOCOL_UNSPECIFIED, 0);
100 /* Reclaim the MURAM memory for our use. */
104 panic("sdma init failed!");
107 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
110 u8 mcn_shift = 0, dev_shift = 0;
113 spin_lock_irqsave(&qe_lock, flags);
114 if (cmd == QE_RESET) {
115 out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
117 if (cmd == QE_ASSIGN_PAGE) {
118 /* Here device is the SNUM, not sub-block */
119 dev_shift = QE_CR_SNUM_SHIFT;
120 } else if (cmd == QE_ASSIGN_RISC) {
121 /* Here device is the SNUM, and mcnProtocol is
122 * e_QeCmdRiscAssignment value */
123 dev_shift = QE_CR_SNUM_SHIFT;
124 mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
126 if (device == QE_CR_SUBBLOCK_USB)
127 mcn_shift = QE_CR_MCN_USB_SHIFT;
129 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
132 out_be32(&qe_immr->cp.cecdr, cmd_input);
133 out_be32(&qe_immr->cp.cecr,
134 (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
135 mcn_protocol << mcn_shift));
138 /* wait for the QE_CR_FLG to clear */
139 ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
141 /* On timeout (e.g. failure), the expression will be false (ret == 0),
142 otherwise it will be true (ret == 1). */
143 spin_unlock_irqrestore(&qe_lock, flags);
147 EXPORT_SYMBOL(qe_issue_cmd);
149 /* Set a baud rate generator. This needs lots of work. There are
150 * 16 BRGs, which can be connected to the QE channels or output
151 * as clocks. The BRGs are in two different block of internal
152 * memory mapped space.
153 * The BRG clock is the QE clock divided by 2.
154 * It was set up long ago during the initial boot phase and is
156 * Baud rate clocks are zero-based in the driver code (as that maps
157 * to port numbers). Documentation uses 1-based numbering.
159 static unsigned int brg_clk = 0;
161 #define CLK_GRAN (1000)
162 #define CLK_GRAN_LIMIT (5)
164 unsigned int qe_get_brg_clk(void)
166 struct device_node *qe;
174 qe = qe_get_device_node();
178 prop = of_get_property(qe, "brg-frequency", &size);
179 if (prop && size == sizeof(*prop))
184 /* round this if near to a multiple of CLK_GRAN */
185 mod = brg_clk % CLK_GRAN;
187 if (mod < CLK_GRAN_LIMIT)
189 else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
190 brg_clk += CLK_GRAN - mod;
195 EXPORT_SYMBOL(qe_get_brg_clk);
197 #define PVR_VER_836x 0x8083
198 #define PVR_VER_832x 0x8084
200 /* Program the BRG to the given sampling rate and multiplier
202 * @brg: the BRG, QE_BRG1 - QE_BRG16
203 * @rate: the desired sampling rate
204 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
205 * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
206 * then 'multiplier' should be 8.
208 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
210 u32 divisor, tempval;
213 if ((brg < QE_BRG1) || (brg > QE_BRG16))
216 divisor = qe_get_brg_clk() / (rate * multiplier);
218 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
219 div16 = QE_BRGC_DIV16;
223 /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
224 that the BRG divisor must be even if you're not using divide-by-16
226 if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
227 if (!div16 && (divisor & 1) && (divisor > 3))
230 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
231 QE_BRGC_ENABLE | div16;
233 out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
237 EXPORT_SYMBOL(qe_setbrg);
239 /* Convert a string to a QE clock source enum
241 * This function takes a string, typically from a property in the device
242 * tree, and returns the corresponding "enum qe_clock" value.
244 enum qe_clock qe_clock_source(const char *source)
248 if (strcasecmp(source, "none") == 0)
251 if (strcmp(source, "tsync_pin") == 0)
254 if (strcmp(source, "rsync_pin") == 0)
257 if (strncasecmp(source, "brg", 3) == 0) {
258 i = simple_strtoul(source + 3, NULL, 10);
259 if ((i >= 1) && (i <= 16))
260 return (QE_BRG1 - 1) + i;
265 if (strncasecmp(source, "clk", 3) == 0) {
266 i = simple_strtoul(source + 3, NULL, 10);
267 if ((i >= 1) && (i <= 24))
268 return (QE_CLK1 - 1) + i;
275 EXPORT_SYMBOL(qe_clock_source);
277 /* Initialize SNUMs (thread serial numbers) according to
278 * QE Module Control chapter, SNUM table
280 static void qe_snums_init(void)
282 static const u8 snum_init_76[] = {
283 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
284 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
285 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
286 0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
287 0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
288 0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
289 0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
290 0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
291 0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
292 0xF4, 0xF5, 0xFC, 0xFD,
294 static const u8 snum_init_46[] = {
295 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
296 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
297 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
298 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
299 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
300 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
302 struct device_node *qe;
306 bitmap_zero(snum_state, QE_NUM_OF_SNUM);
307 qe_num_of_snum = 28; /* The default number of snum for threads is 28 */
308 qe = qe_get_device_node();
310 i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
311 snums, 1, QE_NUM_OF_SNUM);
318 * Fall back to legacy binding of using the value of
319 * fsl,qe-num-snums to choose one of the static arrays
322 of_property_read_u32(qe, "fsl,qe-num-snums", &qe_num_of_snum);
326 if (qe_num_of_snum == 76) {
327 snum_init = snum_init_76;
328 } else if (qe_num_of_snum == 28 || qe_num_of_snum == 46) {
329 snum_init = snum_init_46;
331 pr_err("QE: unsupported value of fsl,qe-num-snums: %u\n", qe_num_of_snum);
334 memcpy(snums, snum_init, qe_num_of_snum);
337 int qe_get_snum(void)
343 spin_lock_irqsave(&qe_lock, flags);
344 i = find_first_zero_bit(snum_state, qe_num_of_snum);
345 if (i < qe_num_of_snum) {
346 set_bit(i, snum_state);
349 spin_unlock_irqrestore(&qe_lock, flags);
353 EXPORT_SYMBOL(qe_get_snum);
355 void qe_put_snum(u8 snum)
357 const u8 *p = memchr(snums, snum, qe_num_of_snum);
360 clear_bit(p - snums, snum_state);
362 EXPORT_SYMBOL(qe_put_snum);
364 static int qe_sdma_init(void)
366 struct sdma __iomem *sdma = &qe_immr->sdma;
367 static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM;
372 /* allocate 2 internal temporary buffers (512 bytes size each) for
374 if (IS_ERR_VALUE(sdma_buf_offset)) {
375 sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
376 if (IS_ERR_VALUE(sdma_buf_offset))
380 out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
381 out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
382 (0x1 << QE_SDMR_CEN_SHIFT)));
387 /* The maximum number of RISCs we support */
388 #define MAX_QE_RISC 4
390 /* Firmware information stored here for qe_get_firmware_info() */
391 static struct qe_firmware_info qe_firmware_info;
394 * Set to 1 if QE firmware has been uploaded, and therefore
395 * qe_firmware_info contains valid data.
397 static int qe_firmware_uploaded;
400 * Upload a QE microcode
402 * This function is a worker function for qe_upload_firmware(). It does
403 * the actual uploading of the microcode.
405 static void qe_upload_microcode(const void *base,
406 const struct qe_microcode *ucode)
408 const __be32 *code = base + be32_to_cpu(ucode->code_offset);
411 if (ucode->major || ucode->minor || ucode->revision)
412 printk(KERN_INFO "qe-firmware: "
413 "uploading microcode '%s' version %u.%u.%u\n",
414 ucode->id, ucode->major, ucode->minor, ucode->revision);
416 printk(KERN_INFO "qe-firmware: "
417 "uploading microcode '%s'\n", ucode->id);
419 /* Use auto-increment */
420 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
421 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
423 for (i = 0; i < be32_to_cpu(ucode->count); i++)
424 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
426 /* Set I-RAM Ready Register */
427 out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
431 * Upload a microcode to the I-RAM at a specific address.
433 * See Documentation/powerpc/qe_firmware.rst for information on QE microcode
436 * Currently, only version 1 is supported, so the 'version' field must be
439 * The SOC model and revision are not validated, they are only displayed for
440 * informational purposes.
442 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
443 * all of the microcode structures, minus the CRC.
445 * 'length' is the size that the structure says it is, including the CRC.
447 int qe_upload_firmware(const struct qe_firmware *firmware)
452 size_t calc_size = sizeof(struct qe_firmware);
454 const struct qe_header *hdr;
457 printk(KERN_ERR "qe-firmware: invalid pointer\n");
461 hdr = &firmware->header;
462 length = be32_to_cpu(hdr->length);
464 /* Check the magic */
465 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
466 (hdr->magic[2] != 'F')) {
467 printk(KERN_ERR "qe-firmware: not a microcode\n");
471 /* Check the version */
472 if (hdr->version != 1) {
473 printk(KERN_ERR "qe-firmware: unsupported version\n");
477 /* Validate some of the fields */
478 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
479 printk(KERN_ERR "qe-firmware: invalid data\n");
483 /* Validate the length and check if there's a CRC */
484 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
486 for (i = 0; i < firmware->count; i++)
488 * For situations where the second RISC uses the same microcode
489 * as the first, the 'code_offset' and 'count' fields will be
490 * zero, so it's okay to add those.
492 calc_size += sizeof(__be32) *
493 be32_to_cpu(firmware->microcode[i].count);
495 /* Validate the length */
496 if (length != calc_size + sizeof(__be32)) {
497 printk(KERN_ERR "qe-firmware: invalid length\n");
501 /* Validate the CRC */
502 crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
503 if (crc != crc32(0, firmware, calc_size)) {
504 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
509 * If the microcode calls for it, split the I-RAM.
511 if (!firmware->split)
512 setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
514 if (firmware->soc.model)
516 "qe-firmware: firmware '%s' for %u V%u.%u\n",
517 firmware->id, be16_to_cpu(firmware->soc.model),
518 firmware->soc.major, firmware->soc.minor);
520 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
524 * The QE only supports one microcode per RISC, so clear out all the
525 * saved microcode information and put in the new.
527 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
528 strlcpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
529 qe_firmware_info.extended_modes = firmware->extended_modes;
530 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
531 sizeof(firmware->vtraps));
533 /* Loop through each microcode. */
534 for (i = 0; i < firmware->count; i++) {
535 const struct qe_microcode *ucode = &firmware->microcode[i];
537 /* Upload a microcode if it's present */
538 if (ucode->code_offset)
539 qe_upload_microcode(firmware, ucode);
541 /* Program the traps for this processor */
542 for (j = 0; j < 16; j++) {
543 u32 trap = be32_to_cpu(ucode->traps[j]);
546 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
550 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
553 qe_firmware_uploaded = 1;
557 EXPORT_SYMBOL(qe_upload_firmware);
560 * Get info on the currently-loaded firmware
562 * This function also checks the device tree to see if the boot loader has
563 * uploaded a firmware already.
565 struct qe_firmware_info *qe_get_firmware_info(void)
567 static int initialized;
568 struct property *prop;
569 struct device_node *qe;
570 struct device_node *fw = NULL;
575 * If we haven't checked yet, and a driver hasn't uploaded a firmware
576 * yet, then check the device tree for information.
578 if (qe_firmware_uploaded)
579 return &qe_firmware_info;
586 qe = qe_get_device_node();
590 /* Find the 'firmware' child node */
591 fw = of_get_child_by_name(qe, "firmware");
594 /* Did we find the 'firmware' node? */
598 qe_firmware_uploaded = 1;
600 /* Copy the data into qe_firmware_info*/
601 sprop = of_get_property(fw, "id", NULL);
603 strlcpy(qe_firmware_info.id, sprop,
604 sizeof(qe_firmware_info.id));
606 prop = of_find_property(fw, "extended-modes", NULL);
607 if (prop && (prop->length == sizeof(u64))) {
608 const u64 *iprop = prop->value;
610 qe_firmware_info.extended_modes = *iprop;
613 prop = of_find_property(fw, "virtual-traps", NULL);
614 if (prop && (prop->length == 32)) {
615 const u32 *iprop = prop->value;
617 for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
618 qe_firmware_info.vtraps[i] = iprop[i];
623 return &qe_firmware_info;
625 EXPORT_SYMBOL(qe_get_firmware_info);
627 unsigned int qe_get_num_of_risc(void)
629 struct device_node *qe;
631 unsigned int num_of_risc = 0;
634 qe = qe_get_device_node();
638 prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
639 if (prop && size == sizeof(*prop))
646 EXPORT_SYMBOL(qe_get_num_of_risc);
648 unsigned int qe_get_num_of_snums(void)
650 return qe_num_of_snum;
652 EXPORT_SYMBOL(qe_get_num_of_snums);
654 static int __init qe_init(void)
656 struct device_node *np;
658 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
665 subsys_initcall(qe_init);
667 #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
668 static int qe_resume(struct platform_device *ofdev)
670 if (!qe_alive_during_sleep())
675 static int qe_probe(struct platform_device *ofdev)
680 static const struct of_device_id qe_ids[] = {
681 { .compatible = "fsl,qe", },
685 static struct platform_driver qe_driver = {
688 .of_match_table = qe_ids,
694 builtin_platform_driver(qe_driver);
695 #endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */