1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
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15 * GNU General Public License ("GPL") as published by the Free Software
16 * Foundation, either version 2 of that License or (at your option) any
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31 #include "qman_priv.h"
33 #define DQRR_MAXFILL 15
34 #define EQCR_ITHRESH 4 /* if EQCR congests, interrupt threshold */
35 #define IRQNAME "QMan portal %d"
36 #define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */
37 #define QMAN_POLL_LIMIT 32
38 #define QMAN_PIRQ_DQRR_ITHRESH 12
39 #define QMAN_PIRQ_MR_ITHRESH 4
40 #define QMAN_PIRQ_IPERIOD 100
42 /* Portal register assists */
44 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
45 /* Cache-inhibited register offsets */
46 #define QM_REG_EQCR_PI_CINH 0x3000
47 #define QM_REG_EQCR_CI_CINH 0x3040
48 #define QM_REG_EQCR_ITR 0x3080
49 #define QM_REG_DQRR_PI_CINH 0x3100
50 #define QM_REG_DQRR_CI_CINH 0x3140
51 #define QM_REG_DQRR_ITR 0x3180
52 #define QM_REG_DQRR_DCAP 0x31C0
53 #define QM_REG_DQRR_SDQCR 0x3200
54 #define QM_REG_DQRR_VDQCR 0x3240
55 #define QM_REG_DQRR_PDQCR 0x3280
56 #define QM_REG_MR_PI_CINH 0x3300
57 #define QM_REG_MR_CI_CINH 0x3340
58 #define QM_REG_MR_ITR 0x3380
59 #define QM_REG_CFG 0x3500
60 #define QM_REG_ISR 0x3600
61 #define QM_REG_IER 0x3640
62 #define QM_REG_ISDR 0x3680
63 #define QM_REG_IIR 0x36C0
64 #define QM_REG_ITPR 0x3740
66 /* Cache-enabled register offsets */
67 #define QM_CL_EQCR 0x0000
68 #define QM_CL_DQRR 0x1000
69 #define QM_CL_MR 0x2000
70 #define QM_CL_EQCR_PI_CENA 0x3000
71 #define QM_CL_EQCR_CI_CENA 0x3040
72 #define QM_CL_DQRR_PI_CENA 0x3100
73 #define QM_CL_DQRR_CI_CENA 0x3140
74 #define QM_CL_MR_PI_CENA 0x3300
75 #define QM_CL_MR_CI_CENA 0x3340
76 #define QM_CL_CR 0x3800
77 #define QM_CL_RR0 0x3900
78 #define QM_CL_RR1 0x3940
81 /* Cache-inhibited register offsets */
82 #define QM_REG_EQCR_PI_CINH 0x0000
83 #define QM_REG_EQCR_CI_CINH 0x0004
84 #define QM_REG_EQCR_ITR 0x0008
85 #define QM_REG_DQRR_PI_CINH 0x0040
86 #define QM_REG_DQRR_CI_CINH 0x0044
87 #define QM_REG_DQRR_ITR 0x0048
88 #define QM_REG_DQRR_DCAP 0x0050
89 #define QM_REG_DQRR_SDQCR 0x0054
90 #define QM_REG_DQRR_VDQCR 0x0058
91 #define QM_REG_DQRR_PDQCR 0x005c
92 #define QM_REG_MR_PI_CINH 0x0080
93 #define QM_REG_MR_CI_CINH 0x0084
94 #define QM_REG_MR_ITR 0x0088
95 #define QM_REG_CFG 0x0100
96 #define QM_REG_ISR 0x0e00
97 #define QM_REG_IER 0x0e04
98 #define QM_REG_ISDR 0x0e08
99 #define QM_REG_IIR 0x0e0c
100 #define QM_REG_ITPR 0x0e14
102 /* Cache-enabled register offsets */
103 #define QM_CL_EQCR 0x0000
104 #define QM_CL_DQRR 0x1000
105 #define QM_CL_MR 0x2000
106 #define QM_CL_EQCR_PI_CENA 0x3000
107 #define QM_CL_EQCR_CI_CENA 0x3100
108 #define QM_CL_DQRR_PI_CENA 0x3200
109 #define QM_CL_DQRR_CI_CENA 0x3300
110 #define QM_CL_MR_PI_CENA 0x3400
111 #define QM_CL_MR_CI_CENA 0x3500
112 #define QM_CL_CR 0x3800
113 #define QM_CL_RR0 0x3900
114 #define QM_CL_RR1 0x3940
118 * BTW, the drivers (and h/w programming model) already obtain the required
119 * synchronisation for portal accesses and data-dependencies. Use of barrier()s
120 * or other order-preserving primitives simply degrade performance. Hence the
121 * use of the __raw_*() interfaces, which simply ensure that the compiler treats
122 * the portal registers as volatile
125 /* Cache-enabled ring access */
126 #define qm_cl(base, idx) ((void *)base + ((idx) << 6))
131 * pmode == production mode
132 * cmode == consumption mode,
133 * dmode == h/w dequeue mode.
134 * Enum values use 3 letter codes. First letter matches the portal mode,
135 * remaining two letters indicate;
136 * ci == cache-inhibited portal register
137 * ce == cache-enabled portal register
138 * vb == in-band valid-bit (cache-enabled)
139 * dc == DCA (Discrete Consumption Acknowledgment), DQRR-only
140 * As for "enum qm_dqrr_dmode", it should be self-explanatory.
142 enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */
143 qm_eqcr_pci = 0, /* PI index, cache-inhibited */
144 qm_eqcr_pce = 1, /* PI index, cache-enabled */
145 qm_eqcr_pvb = 2 /* valid-bit */
147 enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */
148 qm_dqrr_dpush = 0, /* SDQCR + VDQCR */
149 qm_dqrr_dpull = 1 /* PDQCR */
151 enum qm_dqrr_pmode { /* s/w-only */
152 qm_dqrr_pci, /* reads DQRR_PI_CINH */
153 qm_dqrr_pce, /* reads DQRR_PI_CENA */
154 qm_dqrr_pvb /* reads valid-bit */
156 enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */
157 qm_dqrr_cci = 0, /* CI index, cache-inhibited */
158 qm_dqrr_cce = 1, /* CI index, cache-enabled */
159 qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */
161 enum qm_mr_pmode { /* s/w-only */
162 qm_mr_pci, /* reads MR_PI_CINH */
163 qm_mr_pce, /* reads MR_PI_CENA */
164 qm_mr_pvb /* reads valid-bit */
166 enum qm_mr_cmode { /* matches QCSP_CFG::MM */
167 qm_mr_cci = 0, /* CI index, cache-inhibited */
168 qm_mr_cce = 1 /* CI index, cache-enabled */
171 /* --- Portal structures --- */
173 #define QM_EQCR_SIZE 8
174 #define QM_DQRR_SIZE 16
177 /* "Enqueue Command" */
178 struct qm_eqcr_entry {
179 u8 _ncw_verb; /* writes to this are non-coherent */
183 __be32 fqid; /* 24-bit */
188 #define QM_EQCR_VERB_VBIT 0x80
189 #define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
190 #define QM_EQCR_VERB_CMD_ENQUEUE 0x01
191 #define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
192 #define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
193 #define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
196 struct qm_eqcr_entry *ring, *cursor;
197 u8 ci, available, ithresh, vbit;
198 #ifdef CONFIG_FSL_DPAA_CHECKING
200 enum qm_eqcr_pmode pmode;
205 const struct qm_dqrr_entry *ring, *cursor;
206 u8 pi, ci, fill, ithresh, vbit;
207 #ifdef CONFIG_FSL_DPAA_CHECKING
208 enum qm_dqrr_dmode dmode;
209 enum qm_dqrr_pmode pmode;
210 enum qm_dqrr_cmode cmode;
215 union qm_mr_entry *ring, *cursor;
216 u8 pi, ci, fill, ithresh, vbit;
217 #ifdef CONFIG_FSL_DPAA_CHECKING
218 enum qm_mr_pmode pmode;
219 enum qm_mr_cmode cmode;
223 /* MC (Management Command) command */
224 /* "FQ" command layout */
228 __be32 fqid; /* 24-bit */
232 /* "CGR" command layout */
240 #define QM_MCC_VERB_VBIT 0x80
241 #define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
242 #define QM_MCC_VERB_INITFQ_PARKED 0x40
243 #define QM_MCC_VERB_INITFQ_SCHED 0x41
244 #define QM_MCC_VERB_QUERYFQ 0x44
245 #define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
246 #define QM_MCC_VERB_QUERYWQ 0x46
247 #define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
248 #define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
249 #define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
250 #define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
251 #define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
252 #define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */
253 #define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */
254 #define QM_MCC_VERB_INITCGR 0x50
255 #define QM_MCC_VERB_MODIFYCGR 0x51
256 #define QM_MCC_VERB_CGRTESTWRITE 0x52
257 #define QM_MCC_VERB_QUERYCGR 0x58
258 #define QM_MCC_VERB_QUERYCONGESTION 0x59
259 union qm_mc_command {
261 u8 _ncw_verb; /* writes to this are non-coherent */
264 struct qm_mcc_initfq initfq;
265 struct qm_mcc_initcgr initcgr;
267 struct qm_mcc_cgr cgr;
270 /* MC (Management Command) result */
272 struct qm_mcr_queryfq {
276 struct qm_fqd fqd; /* the FQD fields are here */
280 /* "Alter FQ State Commands" */
281 struct qm_mcr_alterfq {
284 u8 fqs; /* Frame Queue Status */
287 #define QM_MCR_VERB_RRID 0x80
288 #define QM_MCR_VERB_MASK QM_MCC_VERB_MASK
289 #define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED
290 #define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED
291 #define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ
292 #define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP
293 #define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ
294 #define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED
295 #define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED
296 #define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE
297 #define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE
298 #define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS
299 #define QM_MCR_RESULT_NULL 0x00
300 #define QM_MCR_RESULT_OK 0xf0
301 #define QM_MCR_RESULT_ERR_FQID 0xf1
302 #define QM_MCR_RESULT_ERR_FQSTATE 0xf2
303 #define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */
304 #define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4
305 #define QM_MCR_RESULT_PENDING 0xf8
306 #define QM_MCR_RESULT_ERR_BADCOMMAND 0xff
307 #define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
308 #define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
309 #define QM_MCR_TIMEOUT 10000 /* us */
316 struct qm_mcr_queryfq queryfq;
317 struct qm_mcr_alterfq alterfq;
318 struct qm_mcr_querycgr querycgr;
319 struct qm_mcr_querycongestion querycongestion;
320 struct qm_mcr_querywq querywq;
321 struct qm_mcr_queryfq_np queryfq_np;
325 union qm_mc_command *cr;
326 union qm_mc_result *rr;
328 #ifdef CONFIG_FSL_DPAA_CHECKING
330 /* Can be _mc_start()ed */
332 /* Can be _mc_commit()ed or _mc_abort()ed */
334 /* Can only be _mc_retry()ed */
341 void *ce; /* cache-enabled */
342 __be32 *ce_be; /* same value as above but for direct access */
343 void __iomem *ci; /* cache-inhibited */
348 * In the non-CONFIG_FSL_DPAA_CHECKING case, the following stuff up to
349 * and including 'mc' fits within a cacheline (yay!). The 'config' part
350 * is setup-only, so isn't a cause for a concern. In other words, don't
351 * rearrange this structure on a whim, there be dragons ...
358 } ____cacheline_aligned;
360 /* Cache-inhibited register access. */
361 static inline u32 qm_in(struct qm_portal *p, u32 offset)
363 return ioread32be(p->addr.ci + offset);
366 static inline void qm_out(struct qm_portal *p, u32 offset, u32 val)
368 iowrite32be(val, p->addr.ci + offset);
371 /* Cache Enabled Portal Access */
372 static inline void qm_cl_invalidate(struct qm_portal *p, u32 offset)
374 dpaa_invalidate(p->addr.ce + offset);
377 static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset)
379 dpaa_touch_ro(p->addr.ce + offset);
382 static inline u32 qm_ce_in(struct qm_portal *p, u32 offset)
384 return be32_to_cpu(*(p->addr.ce_be + (offset/4)));
387 /* --- EQCR API --- */
389 #define EQCR_SHIFT ilog2(sizeof(struct qm_eqcr_entry))
390 #define EQCR_CARRY (uintptr_t)(QM_EQCR_SIZE << EQCR_SHIFT)
392 /* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
393 static struct qm_eqcr_entry *eqcr_carryclear(struct qm_eqcr_entry *p)
395 uintptr_t addr = (uintptr_t)p;
399 return (struct qm_eqcr_entry *)addr;
402 /* Bit-wise logic to convert a ring pointer to a ring index */
403 static int eqcr_ptr2idx(struct qm_eqcr_entry *e)
405 return ((uintptr_t)e >> EQCR_SHIFT) & (QM_EQCR_SIZE - 1);
408 /* Increment the 'cursor' ring pointer, taking 'vbit' into account */
409 static inline void eqcr_inc(struct qm_eqcr *eqcr)
411 /* increment to the next EQCR pointer and handle overflow and 'vbit' */
412 struct qm_eqcr_entry *partial = eqcr->cursor + 1;
414 eqcr->cursor = eqcr_carryclear(partial);
415 if (partial != eqcr->cursor)
416 eqcr->vbit ^= QM_EQCR_VERB_VBIT;
419 static inline int qm_eqcr_init(struct qm_portal *portal,
420 enum qm_eqcr_pmode pmode,
421 unsigned int eq_stash_thresh,
424 struct qm_eqcr *eqcr = &portal->eqcr;
428 eqcr->ring = portal->addr.ce + QM_CL_EQCR;
429 eqcr->ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
430 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
431 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
432 eqcr->cursor = eqcr->ring + pi;
433 eqcr->vbit = (qm_in(portal, QM_REG_EQCR_PI_CINH) & QM_EQCR_SIZE) ?
434 QM_EQCR_VERB_VBIT : 0;
435 eqcr->available = QM_EQCR_SIZE - 1 -
436 dpaa_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi);
437 eqcr->ithresh = qm_in(portal, QM_REG_EQCR_ITR);
438 #ifdef CONFIG_FSL_DPAA_CHECKING
442 cfg = (qm_in(portal, QM_REG_CFG) & 0x00ffffff) |
443 (eq_stash_thresh << 28) | /* QCSP_CFG: EST */
444 (eq_stash_prio << 26) | /* QCSP_CFG: EP */
445 ((pmode & 0x3) << 24); /* QCSP_CFG::EPM */
446 qm_out(portal, QM_REG_CFG, cfg);
450 static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal)
452 return (qm_in(portal, QM_REG_CFG) >> 28) & 0x7;
455 static inline void qm_eqcr_finish(struct qm_portal *portal)
457 struct qm_eqcr *eqcr = &portal->eqcr;
458 u8 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
459 u8 ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
461 DPAA_ASSERT(!eqcr->busy);
462 if (pi != eqcr_ptr2idx(eqcr->cursor))
463 pr_crit("losing uncommitted EQCR entries\n");
465 pr_crit("missing existing EQCR completions\n");
466 if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor))
467 pr_crit("EQCR destroyed unquiesced\n");
470 static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal
473 struct qm_eqcr *eqcr = &portal->eqcr;
475 DPAA_ASSERT(!eqcr->busy);
476 if (!eqcr->available)
479 #ifdef CONFIG_FSL_DPAA_CHECKING
482 dpaa_zero(eqcr->cursor);
486 static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
489 struct qm_eqcr *eqcr = &portal->eqcr;
492 DPAA_ASSERT(!eqcr->busy);
493 if (!eqcr->available) {
495 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) &
497 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
498 eqcr->available += diff;
502 #ifdef CONFIG_FSL_DPAA_CHECKING
505 dpaa_zero(eqcr->cursor);
509 static inline void eqcr_commit_checks(struct qm_eqcr *eqcr)
511 DPAA_ASSERT(eqcr->busy);
512 DPAA_ASSERT(!(be32_to_cpu(eqcr->cursor->fqid) & ~QM_FQID_MASK));
513 DPAA_ASSERT(eqcr->available >= 1);
516 static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb)
518 struct qm_eqcr *eqcr = &portal->eqcr;
519 struct qm_eqcr_entry *eqcursor;
521 eqcr_commit_checks(eqcr);
522 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
524 eqcursor = eqcr->cursor;
525 eqcursor->_ncw_verb = myverb | eqcr->vbit;
526 dpaa_flush(eqcursor);
529 #ifdef CONFIG_FSL_DPAA_CHECKING
534 static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal)
536 qm_cl_touch_ro(portal, QM_CL_EQCR_CI_CENA);
539 static inline u8 qm_eqcr_cce_update(struct qm_portal *portal)
541 struct qm_eqcr *eqcr = &portal->eqcr;
542 u8 diff, old_ci = eqcr->ci;
544 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & (QM_EQCR_SIZE - 1);
545 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
546 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
547 eqcr->available += diff;
551 static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh)
553 struct qm_eqcr *eqcr = &portal->eqcr;
555 eqcr->ithresh = ithresh;
556 qm_out(portal, QM_REG_EQCR_ITR, ithresh);
559 static inline u8 qm_eqcr_get_avail(struct qm_portal *portal)
561 struct qm_eqcr *eqcr = &portal->eqcr;
563 return eqcr->available;
566 static inline u8 qm_eqcr_get_fill(struct qm_portal *portal)
568 struct qm_eqcr *eqcr = &portal->eqcr;
570 return QM_EQCR_SIZE - 1 - eqcr->available;
573 /* --- DQRR API --- */
575 #define DQRR_SHIFT ilog2(sizeof(struct qm_dqrr_entry))
576 #define DQRR_CARRY (uintptr_t)(QM_DQRR_SIZE << DQRR_SHIFT)
578 static const struct qm_dqrr_entry *dqrr_carryclear(
579 const struct qm_dqrr_entry *p)
581 uintptr_t addr = (uintptr_t)p;
585 return (const struct qm_dqrr_entry *)addr;
588 static inline int dqrr_ptr2idx(const struct qm_dqrr_entry *e)
590 return ((uintptr_t)e >> DQRR_SHIFT) & (QM_DQRR_SIZE - 1);
593 static const struct qm_dqrr_entry *dqrr_inc(const struct qm_dqrr_entry *e)
595 return dqrr_carryclear(e + 1);
598 static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf)
600 qm_out(portal, QM_REG_CFG, (qm_in(portal, QM_REG_CFG) & 0xff0fffff) |
601 ((mf & (QM_DQRR_SIZE - 1)) << 20));
604 static inline int qm_dqrr_init(struct qm_portal *portal,
605 const struct qm_portal_config *config,
606 enum qm_dqrr_dmode dmode,
607 enum qm_dqrr_pmode pmode,
608 enum qm_dqrr_cmode cmode, u8 max_fill)
610 struct qm_dqrr *dqrr = &portal->dqrr;
613 /* Make sure the DQRR will be idle when we enable */
614 qm_out(portal, QM_REG_DQRR_SDQCR, 0);
615 qm_out(portal, QM_REG_DQRR_VDQCR, 0);
616 qm_out(portal, QM_REG_DQRR_PDQCR, 0);
617 dqrr->ring = portal->addr.ce + QM_CL_DQRR;
618 dqrr->pi = qm_in(portal, QM_REG_DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
619 dqrr->ci = qm_in(portal, QM_REG_DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
620 dqrr->cursor = dqrr->ring + dqrr->ci;
621 dqrr->fill = dpaa_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
622 dqrr->vbit = (qm_in(portal, QM_REG_DQRR_PI_CINH) & QM_DQRR_SIZE) ?
623 QM_DQRR_VERB_VBIT : 0;
624 dqrr->ithresh = qm_in(portal, QM_REG_DQRR_ITR);
625 #ifdef CONFIG_FSL_DPAA_CHECKING
630 /* Invalidate every ring entry before beginning */
631 for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++)
632 dpaa_invalidate(qm_cl(dqrr->ring, cfg));
633 cfg = (qm_in(portal, QM_REG_CFG) & 0xff000f00) |
634 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */
635 ((dmode & 1) << 18) | /* DP */
636 ((cmode & 3) << 16) | /* DCM */
638 (0 ? 0x40 : 0) | /* Ignore RP */
639 (0 ? 0x10 : 0); /* Ignore SP */
640 qm_out(portal, QM_REG_CFG, cfg);
641 qm_dqrr_set_maxfill(portal, max_fill);
645 static inline void qm_dqrr_finish(struct qm_portal *portal)
647 #ifdef CONFIG_FSL_DPAA_CHECKING
648 struct qm_dqrr *dqrr = &portal->dqrr;
650 if (dqrr->cmode != qm_dqrr_cdc &&
651 dqrr->ci != dqrr_ptr2idx(dqrr->cursor))
652 pr_crit("Ignoring completed DQRR entries\n");
656 static inline const struct qm_dqrr_entry *qm_dqrr_current(
657 struct qm_portal *portal)
659 struct qm_dqrr *dqrr = &portal->dqrr;
666 static inline u8 qm_dqrr_next(struct qm_portal *portal)
668 struct qm_dqrr *dqrr = &portal->dqrr;
670 DPAA_ASSERT(dqrr->fill);
671 dqrr->cursor = dqrr_inc(dqrr->cursor);
675 static inline void qm_dqrr_pvb_update(struct qm_portal *portal)
677 struct qm_dqrr *dqrr = &portal->dqrr;
678 struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
680 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
681 #ifndef CONFIG_FSL_PAMU
683 * If PAMU is not available we need to invalidate the cache.
684 * When PAMU is available the cache is updated by stash
686 dpaa_invalidate_touch_ro(res);
688 if ((res->verb & QM_DQRR_VERB_VBIT) == dqrr->vbit) {
689 dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);
691 dqrr->vbit ^= QM_DQRR_VERB_VBIT;
696 static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal,
697 const struct qm_dqrr_entry *dq,
700 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
701 int idx = dqrr_ptr2idx(dq);
703 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
704 DPAA_ASSERT((dqrr->ring + idx) == dq);
705 DPAA_ASSERT(idx < QM_DQRR_SIZE);
706 qm_out(portal, QM_REG_DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
707 ((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */
708 idx); /* DQRR_DCAP::DCAP_CI */
711 static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u32 bitmask)
713 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
715 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
716 qm_out(portal, QM_REG_DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
717 (bitmask << 16)); /* DQRR_DCAP::DCAP_CI */
720 static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr)
722 qm_out(portal, QM_REG_DQRR_SDQCR, sdqcr);
725 static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr)
727 qm_out(portal, QM_REG_DQRR_VDQCR, vdqcr);
730 static inline void qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh)
732 qm_out(portal, QM_REG_DQRR_ITR, ithresh);
737 #define MR_SHIFT ilog2(sizeof(union qm_mr_entry))
738 #define MR_CARRY (uintptr_t)(QM_MR_SIZE << MR_SHIFT)
740 static union qm_mr_entry *mr_carryclear(union qm_mr_entry *p)
742 uintptr_t addr = (uintptr_t)p;
746 return (union qm_mr_entry *)addr;
749 static inline int mr_ptr2idx(const union qm_mr_entry *e)
751 return ((uintptr_t)e >> MR_SHIFT) & (QM_MR_SIZE - 1);
754 static inline union qm_mr_entry *mr_inc(union qm_mr_entry *e)
756 return mr_carryclear(e + 1);
759 static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode,
760 enum qm_mr_cmode cmode)
762 struct qm_mr *mr = &portal->mr;
765 mr->ring = portal->addr.ce + QM_CL_MR;
766 mr->pi = qm_in(portal, QM_REG_MR_PI_CINH) & (QM_MR_SIZE - 1);
767 mr->ci = qm_in(portal, QM_REG_MR_CI_CINH) & (QM_MR_SIZE - 1);
768 mr->cursor = mr->ring + mr->ci;
769 mr->fill = dpaa_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi);
770 mr->vbit = (qm_in(portal, QM_REG_MR_PI_CINH) & QM_MR_SIZE)
771 ? QM_MR_VERB_VBIT : 0;
772 mr->ithresh = qm_in(portal, QM_REG_MR_ITR);
773 #ifdef CONFIG_FSL_DPAA_CHECKING
777 cfg = (qm_in(portal, QM_REG_CFG) & 0xfffff0ff) |
778 ((cmode & 1) << 8); /* QCSP_CFG:MM */
779 qm_out(portal, QM_REG_CFG, cfg);
783 static inline void qm_mr_finish(struct qm_portal *portal)
785 struct qm_mr *mr = &portal->mr;
787 if (mr->ci != mr_ptr2idx(mr->cursor))
788 pr_crit("Ignoring completed MR entries\n");
791 static inline const union qm_mr_entry *qm_mr_current(struct qm_portal *portal)
793 struct qm_mr *mr = &portal->mr;
800 static inline int qm_mr_next(struct qm_portal *portal)
802 struct qm_mr *mr = &portal->mr;
804 DPAA_ASSERT(mr->fill);
805 mr->cursor = mr_inc(mr->cursor);
809 static inline void qm_mr_pvb_update(struct qm_portal *portal)
811 struct qm_mr *mr = &portal->mr;
812 union qm_mr_entry *res = qm_cl(mr->ring, mr->pi);
814 DPAA_ASSERT(mr->pmode == qm_mr_pvb);
816 if ((res->verb & QM_MR_VERB_VBIT) == mr->vbit) {
817 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);
819 mr->vbit ^= QM_MR_VERB_VBIT;
823 dpaa_invalidate_touch_ro(res);
826 static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num)
828 struct qm_mr *mr = &portal->mr;
830 DPAA_ASSERT(mr->cmode == qm_mr_cci);
831 mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
832 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
835 static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal)
837 struct qm_mr *mr = &portal->mr;
839 DPAA_ASSERT(mr->cmode == qm_mr_cci);
840 mr->ci = mr_ptr2idx(mr->cursor);
841 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
844 static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh)
846 qm_out(portal, QM_REG_MR_ITR, ithresh);
849 /* --- Management command API --- */
851 static inline int qm_mc_init(struct qm_portal *portal)
853 struct qm_mc *mc = &portal->mc;
855 mc->cr = portal->addr.ce + QM_CL_CR;
856 mc->rr = portal->addr.ce + QM_CL_RR0;
857 mc->rridx = (mc->cr->_ncw_verb & QM_MCC_VERB_VBIT)
859 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
860 #ifdef CONFIG_FSL_DPAA_CHECKING
861 mc->state = qman_mc_idle;
866 static inline void qm_mc_finish(struct qm_portal *portal)
868 #ifdef CONFIG_FSL_DPAA_CHECKING
869 struct qm_mc *mc = &portal->mc;
871 DPAA_ASSERT(mc->state == qman_mc_idle);
872 if (mc->state != qman_mc_idle)
873 pr_crit("Losing incomplete MC command\n");
877 static inline union qm_mc_command *qm_mc_start(struct qm_portal *portal)
879 struct qm_mc *mc = &portal->mc;
881 DPAA_ASSERT(mc->state == qman_mc_idle);
882 #ifdef CONFIG_FSL_DPAA_CHECKING
883 mc->state = qman_mc_user;
889 static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb)
891 struct qm_mc *mc = &portal->mc;
892 union qm_mc_result *rr = mc->rr + mc->rridx;
894 DPAA_ASSERT(mc->state == qman_mc_user);
896 mc->cr->_ncw_verb = myverb | mc->vbit;
898 dpaa_invalidate_touch_ro(rr);
899 #ifdef CONFIG_FSL_DPAA_CHECKING
900 mc->state = qman_mc_hw;
904 static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal)
906 struct qm_mc *mc = &portal->mc;
907 union qm_mc_result *rr = mc->rr + mc->rridx;
909 DPAA_ASSERT(mc->state == qman_mc_hw);
911 * The inactive response register's verb byte always returns zero until
912 * its command is submitted and completed. This includes the valid-bit,
913 * in case you were wondering...
916 dpaa_invalidate_touch_ro(rr);
920 mc->vbit ^= QM_MCC_VERB_VBIT;
921 #ifdef CONFIG_FSL_DPAA_CHECKING
922 mc->state = qman_mc_idle;
927 static inline int qm_mc_result_timeout(struct qm_portal *portal,
928 union qm_mc_result **mcr)
930 int timeout = QM_MCR_TIMEOUT;
933 *mcr = qm_mc_result(portal);
942 static inline void fq_set(struct qman_fq *fq, u32 mask)
947 static inline void fq_clear(struct qman_fq *fq, u32 mask)
952 static inline int fq_isset(struct qman_fq *fq, u32 mask)
954 return fq->flags & mask;
957 static inline int fq_isclear(struct qman_fq *fq, u32 mask)
959 return !(fq->flags & mask);
964 /* PORTAL_BITS_*** - dynamic, strictly internal */
966 /* interrupt sources processed by portal_isr(), configurable */
967 unsigned long irq_sources;
968 u32 use_eqcr_ci_stashing;
969 /* only 1 volatile dequeue at a time */
970 struct qman_fq *vdqcr_owned;
972 /* probing time config params for cpu-affine portals */
973 const struct qm_portal_config *config;
974 /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */
975 struct qman_cgrs *cgrs;
976 /* linked-list of CSCN handlers. */
977 struct list_head cgr_cbs;
980 struct work_struct congestion_work;
981 struct work_struct mr_work;
982 char irqname[MAX_IRQNAME];
985 static cpumask_t affine_mask;
986 static DEFINE_SPINLOCK(affine_mask_lock);
987 static u16 affine_channels[NR_CPUS];
988 static DEFINE_PER_CPU(struct qman_portal, qman_affine_portal);
989 struct qman_portal *affine_portals[NR_CPUS];
991 static inline struct qman_portal *get_affine_portal(void)
993 return &get_cpu_var(qman_affine_portal);
996 static inline void put_affine_portal(void)
998 put_cpu_var(qman_affine_portal);
1001 static struct workqueue_struct *qm_portal_wq;
1003 int qman_wq_alloc(void)
1005 qm_portal_wq = alloc_workqueue("qman_portal_wq", 0, 1);
1012 * This is what everything can wait on, even if it migrates to a different cpu
1013 * to the one whose affine portal it is waiting on.
1015 static DECLARE_WAIT_QUEUE_HEAD(affine_queue);
1017 static struct qman_fq **fq_table;
1018 static u32 num_fqids;
1020 int qman_alloc_fq_table(u32 _num_fqids)
1022 num_fqids = _num_fqids;
1024 fq_table = vzalloc(array3_size(sizeof(struct qman_fq *),
1029 pr_debug("Allocated fq lookup table at %p, entry count %u\n",
1030 fq_table, num_fqids * 2);
1034 static struct qman_fq *idx_to_fq(u32 idx)
1038 #ifdef CONFIG_FSL_DPAA_CHECKING
1039 if (WARN_ON(idx >= num_fqids * 2))
1043 DPAA_ASSERT(!fq || idx == fq->idx);
1049 * Only returns full-service fq objects, not enqueue-only
1050 * references (QMAN_FQ_FLAG_NO_MODIFY).
1052 static struct qman_fq *fqid_to_fq(u32 fqid)
1054 return idx_to_fq(fqid * 2);
1057 static struct qman_fq *tag_to_fq(u32 tag)
1059 #if BITS_PER_LONG == 64
1060 return idx_to_fq(tag);
1062 return (struct qman_fq *)tag;
1066 static u32 fq_to_tag(struct qman_fq *fq)
1068 #if BITS_PER_LONG == 64
1075 static u32 __poll_portal_slow(struct qman_portal *p, u32 is);
1076 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1077 unsigned int poll_limit);
1078 static void qm_congestion_task(struct work_struct *work);
1079 static void qm_mr_process_task(struct work_struct *work);
1081 static irqreturn_t portal_isr(int irq, void *ptr)
1083 struct qman_portal *p = ptr;
1085 u32 clear = QM_DQAVAIL_MASK | p->irq_sources;
1086 u32 is = qm_in(&p->p, QM_REG_ISR) & p->irq_sources;
1091 /* DQRR-handling if it's interrupt-driven */
1092 if (is & QM_PIRQ_DQRI)
1093 __poll_portal_fast(p, QMAN_POLL_LIMIT);
1094 /* Handling of anything else that's interrupt-driven */
1095 clear |= __poll_portal_slow(p, is);
1096 qm_out(&p->p, QM_REG_ISR, clear);
1100 static int drain_mr_fqrni(struct qm_portal *p)
1102 const union qm_mr_entry *msg;
1104 msg = qm_mr_current(p);
1107 * if MR was full and h/w had other FQRNI entries to produce, we
1108 * need to allow it time to produce those entries once the
1109 * existing entries are consumed. A worst-case situation
1110 * (fully-loaded system) means h/w sequencers may have to do 3-4
1111 * other things before servicing the portal's MR pump, each of
1112 * which (if slow) may take ~50 qman cycles (which is ~200
1113 * processor cycles). So rounding up and then multiplying this
1114 * worst-case estimate by a factor of 10, just to be
1115 * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
1116 * one entry at a time, so h/w has an opportunity to produce new
1117 * entries well before the ring has been fully consumed, so
1118 * we're being *really* paranoid here.
1121 msg = qm_mr_current(p);
1125 if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
1126 /* We aren't draining anything but FQRNIs */
1127 pr_err("Found verb 0x%x in MR\n", msg->verb);
1131 qm_mr_cci_consume(p, 1);
1135 static int qman_create_portal(struct qman_portal *portal,
1136 const struct qm_portal_config *c,
1137 const struct qman_cgrs *cgrs)
1139 struct qm_portal *p;
1145 #ifdef CONFIG_FSL_PAMU
1146 /* PAMU is required for stashing */
1147 portal->use_eqcr_ci_stashing = ((qman_ip_rev >= QMAN_REV30) ? 1 : 0);
1149 portal->use_eqcr_ci_stashing = 0;
1152 * prep the low-level portal struct with the mapped addresses from the
1153 * config, everything that follows depends on it and "config" is more
1156 p->addr.ce = c->addr_virt_ce;
1157 p->addr.ce_be = c->addr_virt_ce;
1158 p->addr.ci = c->addr_virt_ci;
1160 * If CI-stashing is used, the current defaults use a threshold of 3,
1161 * and stash with high-than-DQRR priority.
1163 if (qm_eqcr_init(p, qm_eqcr_pvb,
1164 portal->use_eqcr_ci_stashing ? 3 : 0, 1)) {
1165 dev_err(c->dev, "EQCR initialisation failed\n");
1168 if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
1169 qm_dqrr_cdc, DQRR_MAXFILL)) {
1170 dev_err(c->dev, "DQRR initialisation failed\n");
1173 if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
1174 dev_err(c->dev, "MR initialisation failed\n");
1177 if (qm_mc_init(p)) {
1178 dev_err(c->dev, "MC initialisation failed\n");
1181 /* static interrupt-gating controls */
1182 qm_dqrr_set_ithresh(p, QMAN_PIRQ_DQRR_ITHRESH);
1183 qm_mr_set_ithresh(p, QMAN_PIRQ_MR_ITHRESH);
1184 qm_out(p, QM_REG_ITPR, QMAN_PIRQ_IPERIOD);
1185 portal->cgrs = kmalloc_array(2, sizeof(*cgrs), GFP_KERNEL);
1188 /* initial snapshot is no-depletion */
1189 qman_cgrs_init(&portal->cgrs[1]);
1191 portal->cgrs[0] = *cgrs;
1193 /* if the given mask is NULL, assume all CGRs can be seen */
1194 qman_cgrs_fill(&portal->cgrs[0]);
1195 INIT_LIST_HEAD(&portal->cgr_cbs);
1196 spin_lock_init(&portal->cgr_lock);
1197 INIT_WORK(&portal->congestion_work, qm_congestion_task);
1198 INIT_WORK(&portal->mr_work, qm_mr_process_task);
1200 portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 |
1201 QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS |
1202 QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED;
1204 qm_out(p, QM_REG_ISDR, isdr);
1205 portal->irq_sources = 0;
1206 qm_out(p, QM_REG_IER, 0);
1207 qm_out(p, QM_REG_ISR, 0xffffffff);
1208 snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
1209 if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) {
1210 dev_err(c->dev, "request_irq() failed\n");
1213 if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
1214 irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
1215 dev_err(c->dev, "irq_set_affinity() failed\n");
1219 /* Need EQCR to be empty before continuing */
1220 isdr &= ~QM_PIRQ_EQCI;
1221 qm_out(p, QM_REG_ISDR, isdr);
1222 ret = qm_eqcr_get_fill(p);
1224 dev_err(c->dev, "EQCR unclean\n");
1225 goto fail_eqcr_empty;
1227 isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
1228 qm_out(p, QM_REG_ISDR, isdr);
1229 if (qm_dqrr_current(p)) {
1230 dev_err(c->dev, "DQRR unclean\n");
1231 qm_dqrr_cdc_consume_n(p, 0xffff);
1233 if (qm_mr_current(p) && drain_mr_fqrni(p)) {
1234 /* special handling, drain just in case it's a few FQRNIs */
1235 const union qm_mr_entry *e = qm_mr_current(p);
1237 dev_err(c->dev, "MR dirty, VB 0x%x, rc 0x%x, addr 0x%llx\n",
1238 e->verb, e->ern.rc, qm_fd_addr_get64(&e->ern.fd));
1239 goto fail_dqrr_mr_empty;
1243 qm_out(p, QM_REG_ISDR, 0);
1244 qm_out(p, QM_REG_IIR, 0);
1245 /* Write a sane SDQCR */
1246 qm_dqrr_sdqcr_set(p, portal->sdqcr);
1252 free_irq(c->irq, portal);
1254 kfree(portal->cgrs);
1267 struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c,
1268 const struct qman_cgrs *cgrs)
1270 struct qman_portal *portal;
1273 portal = &per_cpu(qman_affine_portal, c->cpu);
1274 err = qman_create_portal(portal, c, cgrs);
1278 spin_lock(&affine_mask_lock);
1279 cpumask_set_cpu(c->cpu, &affine_mask);
1280 affine_channels[c->cpu] = c->channel;
1281 affine_portals[c->cpu] = portal;
1282 spin_unlock(&affine_mask_lock);
1287 static void qman_destroy_portal(struct qman_portal *qm)
1289 const struct qm_portal_config *pcfg;
1291 /* Stop dequeues on the portal */
1292 qm_dqrr_sdqcr_set(&qm->p, 0);
1295 * NB we do this to "quiesce" EQCR. If we add enqueue-completions or
1296 * something related to QM_PIRQ_EQCI, this may need fixing.
1297 * Also, due to the prefetching model used for CI updates in the enqueue
1298 * path, this update will only invalidate the CI cacheline *after*
1299 * working on it, so we need to call this twice to ensure a full update
1300 * irrespective of where the enqueue processing was at when the teardown
1303 qm_eqcr_cce_update(&qm->p);
1304 qm_eqcr_cce_update(&qm->p);
1307 free_irq(pcfg->irq, qm);
1310 qm_mc_finish(&qm->p);
1311 qm_mr_finish(&qm->p);
1312 qm_dqrr_finish(&qm->p);
1313 qm_eqcr_finish(&qm->p);
1318 const struct qm_portal_config *qman_destroy_affine_portal(void)
1320 struct qman_portal *qm = get_affine_portal();
1321 const struct qm_portal_config *pcfg;
1327 qman_destroy_portal(qm);
1329 spin_lock(&affine_mask_lock);
1330 cpumask_clear_cpu(cpu, &affine_mask);
1331 spin_unlock(&affine_mask_lock);
1332 put_affine_portal();
1336 /* Inline helper to reduce nesting in __poll_portal_slow() */
1337 static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq,
1338 const union qm_mr_entry *msg, u8 verb)
1341 case QM_MR_VERB_FQRL:
1342 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL));
1343 fq_clear(fq, QMAN_FQ_STATE_ORL);
1345 case QM_MR_VERB_FQRN:
1346 DPAA_ASSERT(fq->state == qman_fq_state_parked ||
1347 fq->state == qman_fq_state_sched);
1348 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING));
1349 fq_clear(fq, QMAN_FQ_STATE_CHANGING);
1350 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY)
1351 fq_set(fq, QMAN_FQ_STATE_NE);
1352 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT)
1353 fq_set(fq, QMAN_FQ_STATE_ORL);
1354 fq->state = qman_fq_state_retired;
1356 case QM_MR_VERB_FQPN:
1357 DPAA_ASSERT(fq->state == qman_fq_state_sched);
1358 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING));
1359 fq->state = qman_fq_state_parked;
1363 static void qm_congestion_task(struct work_struct *work)
1365 struct qman_portal *p = container_of(work, struct qman_portal,
1367 struct qman_cgrs rr, c;
1368 union qm_mc_result *mcr;
1369 struct qman_cgr *cgr;
1371 spin_lock(&p->cgr_lock);
1373 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
1374 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1375 spin_unlock(&p->cgr_lock);
1376 dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
1377 qman_p_irqsource_add(p, QM_PIRQ_CSCI);
1380 /* mask out the ones I'm not interested in */
1381 qman_cgrs_and(&rr, (struct qman_cgrs *)&mcr->querycongestion.state,
1383 /* check previous snapshot for delta, enter/exit congestion */
1384 qman_cgrs_xor(&c, &rr, &p->cgrs[1]);
1385 /* update snapshot */
1386 qman_cgrs_cp(&p->cgrs[1], &rr);
1387 /* Invoke callback */
1388 list_for_each_entry(cgr, &p->cgr_cbs, node)
1389 if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
1390 cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
1391 spin_unlock(&p->cgr_lock);
1392 qman_p_irqsource_add(p, QM_PIRQ_CSCI);
1395 static void qm_mr_process_task(struct work_struct *work)
1397 struct qman_portal *p = container_of(work, struct qman_portal,
1399 const union qm_mr_entry *msg;
1406 qm_mr_pvb_update(&p->p);
1407 msg = qm_mr_current(&p->p);
1411 verb = msg->verb & QM_MR_VERB_TYPE_MASK;
1412 /* The message is a software ERN iff the 0x20 bit is clear */
1415 case QM_MR_VERB_FQRNI:
1416 /* nada, we drop FQRNIs on the floor */
1418 case QM_MR_VERB_FQRN:
1419 case QM_MR_VERB_FQRL:
1420 /* Lookup in the retirement table */
1421 fq = fqid_to_fq(qm_fqid_get(&msg->fq));
1424 fq_state_change(p, fq, msg, verb);
1426 fq->cb.fqs(p, fq, msg);
1428 case QM_MR_VERB_FQPN:
1430 fq = tag_to_fq(be32_to_cpu(msg->fq.context_b));
1431 fq_state_change(p, fq, msg, verb);
1433 fq->cb.fqs(p, fq, msg);
1435 case QM_MR_VERB_DC_ERN:
1437 pr_crit_once("Leaking DCP ERNs!\n");
1440 pr_crit("Invalid MR verb 0x%02x\n", verb);
1443 /* Its a software ERN */
1444 fq = tag_to_fq(be32_to_cpu(msg->ern.tag));
1445 fq->cb.ern(p, fq, msg);
1451 qm_mr_cci_consume(&p->p, num);
1452 qman_p_irqsource_add(p, QM_PIRQ_MRI);
1456 static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
1458 if (is & QM_PIRQ_CSCI) {
1459 qman_p_irqsource_remove(p, QM_PIRQ_CSCI);
1460 queue_work_on(smp_processor_id(), qm_portal_wq,
1461 &p->congestion_work);
1464 if (is & QM_PIRQ_EQRI) {
1465 qm_eqcr_cce_update(&p->p);
1466 qm_eqcr_set_ithresh(&p->p, 0);
1467 wake_up(&affine_queue);
1470 if (is & QM_PIRQ_MRI) {
1471 qman_p_irqsource_remove(p, QM_PIRQ_MRI);
1472 queue_work_on(smp_processor_id(), qm_portal_wq,
1480 * remove some slowish-path stuff from the "fast path" and make sure it isn't
1483 static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq)
1485 p->vdqcr_owned = NULL;
1486 fq_clear(fq, QMAN_FQ_STATE_VDQCR);
1487 wake_up(&affine_queue);
1491 * The only states that would conflict with other things if they ran at the
1492 * same time on the same cpu are:
1494 * (i) setting/clearing vdqcr_owned, and
1495 * (ii) clearing the NE (Not Empty) flag.
1497 * Both are safe. Because;
1499 * (i) this clearing can only occur after qman_volatile_dequeue() has set the
1500 * vdqcr_owned field (which it does before setting VDQCR), and
1501 * qman_volatile_dequeue() blocks interrupts and preemption while this is
1502 * done so that we can't interfere.
1503 * (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as
1504 * with (i) that API prevents us from interfering until it's safe.
1506 * The good thing is that qman_volatile_dequeue() and qman_retire_fq() run far
1507 * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett
1508 * advantage comes from this function not having to "lock" anything at all.
1510 * Note also that the callbacks are invoked at points which are safe against the
1511 * above potential conflicts, but that this function itself is not re-entrant
1512 * (this is because the function tracks one end of each FIFO in the portal and
1513 * we do *not* want to lock that). So the consequence is that it is safe for
1514 * user callbacks to call into any QMan API.
1516 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1517 unsigned int poll_limit)
1519 const struct qm_dqrr_entry *dq;
1521 enum qman_cb_dqrr_result res;
1522 unsigned int limit = 0;
1525 qm_dqrr_pvb_update(&p->p);
1526 dq = qm_dqrr_current(&p->p);
1530 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
1532 * VDQCR: don't trust context_b as the FQ may have
1533 * been configured for h/w consumption and we're
1534 * draining it post-retirement.
1536 fq = p->vdqcr_owned;
1538 * We only set QMAN_FQ_STATE_NE when retiring, so we
1539 * only need to check for clearing it when doing
1540 * volatile dequeues. It's one less thing to check
1541 * in the critical path (SDQCR).
1543 if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
1544 fq_clear(fq, QMAN_FQ_STATE_NE);
1546 * This is duplicated from the SDQCR code, but we
1547 * have stuff to do before *and* after this callback,
1548 * and we don't want multiple if()s in the critical
1551 res = fq->cb.dqrr(p, fq, dq);
1552 if (res == qman_cb_dqrr_stop)
1554 /* Check for VDQCR completion */
1555 if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1558 /* SDQCR: context_b points to the FQ */
1559 fq = tag_to_fq(be32_to_cpu(dq->context_b));
1560 /* Now let the callback do its stuff */
1561 res = fq->cb.dqrr(p, fq, dq);
1563 * The callback can request that we exit without
1564 * consuming this entry nor advancing;
1566 if (res == qman_cb_dqrr_stop)
1569 /* Interpret 'dq' from a driver perspective. */
1571 * Parking isn't possible unless HELDACTIVE was set. NB,
1572 * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1573 * check for HELDACTIVE to cover both.
1575 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1576 (res != qman_cb_dqrr_park));
1577 /* just means "skip it, I'll consume it myself later on" */
1578 if (res != qman_cb_dqrr_defer)
1579 qm_dqrr_cdc_consume_1ptr(&p->p, dq,
1580 res == qman_cb_dqrr_park);
1582 qm_dqrr_next(&p->p);
1584 * Entry processed and consumed, increment our counter. The
1585 * callback can request that we exit after consuming the
1586 * entry, and we also exit if we reach our processing limit,
1587 * so loop back only if neither of these conditions is met.
1589 } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop);
1594 void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
1596 unsigned long irqflags;
1598 local_irq_save(irqflags);
1599 p->irq_sources |= bits & QM_PIRQ_VISIBLE;
1600 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1601 local_irq_restore(irqflags);
1603 EXPORT_SYMBOL(qman_p_irqsource_add);
1605 void qman_p_irqsource_remove(struct qman_portal *p, u32 bits)
1607 unsigned long irqflags;
1611 * Our interrupt handler only processes+clears status register bits that
1612 * are in p->irq_sources. As we're trimming that mask, if one of them
1613 * were to assert in the status register just before we remove it from
1614 * the enable register, there would be an interrupt-storm when we
1615 * release the IRQ lock. So we wait for the enable register update to
1616 * take effect in h/w (by reading it back) and then clear all other bits
1617 * in the status register. Ie. we clear them from ISR once it's certain
1618 * IER won't allow them to reassert.
1620 local_irq_save(irqflags);
1621 bits &= QM_PIRQ_VISIBLE;
1622 p->irq_sources &= ~bits;
1623 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1624 ier = qm_in(&p->p, QM_REG_IER);
1626 * Using "~ier" (rather than "bits" or "~p->irq_sources") creates a
1627 * data-dependency, ie. to protect against re-ordering.
1629 qm_out(&p->p, QM_REG_ISR, ~ier);
1630 local_irq_restore(irqflags);
1632 EXPORT_SYMBOL(qman_p_irqsource_remove);
1634 const cpumask_t *qman_affine_cpus(void)
1636 return &affine_mask;
1638 EXPORT_SYMBOL(qman_affine_cpus);
1640 u16 qman_affine_channel(int cpu)
1643 struct qman_portal *portal = get_affine_portal();
1645 cpu = portal->config->cpu;
1646 put_affine_portal();
1648 WARN_ON(!cpumask_test_cpu(cpu, &affine_mask));
1649 return affine_channels[cpu];
1651 EXPORT_SYMBOL(qman_affine_channel);
1653 struct qman_portal *qman_get_affine_portal(int cpu)
1655 return affine_portals[cpu];
1657 EXPORT_SYMBOL(qman_get_affine_portal);
1659 int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit)
1661 return __poll_portal_fast(p, limit);
1663 EXPORT_SYMBOL(qman_p_poll_dqrr);
1665 void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools)
1667 unsigned long irqflags;
1669 local_irq_save(irqflags);
1670 pools &= p->config->pools;
1672 qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1673 local_irq_restore(irqflags);
1675 EXPORT_SYMBOL(qman_p_static_dequeue_add);
1677 /* Frame queue API */
1679 static const char *mcr_result_str(u8 result)
1682 case QM_MCR_RESULT_NULL:
1683 return "QM_MCR_RESULT_NULL";
1684 case QM_MCR_RESULT_OK:
1685 return "QM_MCR_RESULT_OK";
1686 case QM_MCR_RESULT_ERR_FQID:
1687 return "QM_MCR_RESULT_ERR_FQID";
1688 case QM_MCR_RESULT_ERR_FQSTATE:
1689 return "QM_MCR_RESULT_ERR_FQSTATE";
1690 case QM_MCR_RESULT_ERR_NOTEMPTY:
1691 return "QM_MCR_RESULT_ERR_NOTEMPTY";
1692 case QM_MCR_RESULT_PENDING:
1693 return "QM_MCR_RESULT_PENDING";
1694 case QM_MCR_RESULT_ERR_BADCOMMAND:
1695 return "QM_MCR_RESULT_ERR_BADCOMMAND";
1697 return "<unknown MCR result>";
1700 int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
1702 if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) {
1703 int ret = qman_alloc_fqid(&fqid);
1710 fq->state = qman_fq_state_oos;
1711 fq->cgr_groupid = 0;
1713 /* A context_b of 0 is allegedly special, so don't use that fqid */
1714 if (fqid == 0 || fqid >= num_fqids) {
1715 WARN(1, "bad fqid %d\n", fqid);
1720 if (flags & QMAN_FQ_FLAG_NO_MODIFY)
1723 WARN_ON(fq_table[fq->idx]);
1724 fq_table[fq->idx] = fq;
1728 EXPORT_SYMBOL(qman_create_fq);
1730 void qman_destroy_fq(struct qman_fq *fq)
1733 * We don't need to lock the FQ as it is a pre-condition that the FQ be
1734 * quiesced. Instead, run some checks.
1736 switch (fq->state) {
1737 case qman_fq_state_parked:
1738 case qman_fq_state_oos:
1739 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID))
1740 qman_release_fqid(fq->fqid);
1742 DPAA_ASSERT(fq_table[fq->idx]);
1743 fq_table[fq->idx] = NULL;
1748 DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!");
1750 EXPORT_SYMBOL(qman_destroy_fq);
1752 u32 qman_fq_fqid(struct qman_fq *fq)
1756 EXPORT_SYMBOL(qman_fq_fqid);
1758 int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
1760 union qm_mc_command *mcc;
1761 union qm_mc_result *mcr;
1762 struct qman_portal *p;
1766 myverb = (flags & QMAN_INITFQ_FLAG_SCHED)
1767 ? QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED;
1769 if (fq->state != qman_fq_state_oos &&
1770 fq->state != qman_fq_state_parked)
1772 #ifdef CONFIG_FSL_DPAA_CHECKING
1773 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1776 if (opts && (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_OAC)) {
1777 /* And can't be set at the same time as TDTHRESH */
1778 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_TDTHRESH)
1781 /* Issue an INITFQ_[PARKED|SCHED] management command */
1782 p = get_affine_portal();
1783 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1784 (fq->state != qman_fq_state_oos &&
1785 fq->state != qman_fq_state_parked)) {
1789 mcc = qm_mc_start(&p->p);
1791 mcc->initfq = *opts;
1792 qm_fqid_set(&mcc->fq, fq->fqid);
1793 mcc->initfq.count = 0;
1795 * If the FQ does *not* have the TO_DCPORTAL flag, context_b is set as a
1796 * demux pointer. Otherwise, the caller-provided value is allowed to
1797 * stand, don't overwrite it.
1799 if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
1802 mcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB);
1803 mcc->initfq.fqd.context_b = cpu_to_be32(fq_to_tag(fq));
1805 * and the physical address - NB, if the user wasn't trying to
1806 * set CONTEXTA, clear the stashing settings.
1808 if (!(be16_to_cpu(mcc->initfq.we_mask) &
1809 QM_INITFQ_WE_CONTEXTA)) {
1810 mcc->initfq.we_mask |=
1811 cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1812 memset(&mcc->initfq.fqd.context_a, 0,
1813 sizeof(mcc->initfq.fqd.context_a));
1815 struct qman_portal *p = qman_dma_portal;
1817 phys_fq = dma_map_single(p->config->dev, fq,
1818 sizeof(*fq), DMA_TO_DEVICE);
1819 if (dma_mapping_error(p->config->dev, phys_fq)) {
1820 dev_err(p->config->dev, "dma_mapping failed\n");
1825 qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq);
1828 if (flags & QMAN_INITFQ_FLAG_LOCAL) {
1831 if (!(be16_to_cpu(mcc->initfq.we_mask) &
1832 QM_INITFQ_WE_DESTWQ)) {
1833 mcc->initfq.we_mask |=
1834 cpu_to_be16(QM_INITFQ_WE_DESTWQ);
1837 qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);
1839 qm_mc_commit(&p->p, myverb);
1840 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1841 dev_err(p->config->dev, "MCR timeout\n");
1846 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1848 if (res != QM_MCR_RESULT_OK) {
1853 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) {
1854 if (be16_to_cpu(opts->fqd.fq_ctrl) & QM_FQCTRL_CGE)
1855 fq_set(fq, QMAN_FQ_STATE_CGR_EN);
1857 fq_clear(fq, QMAN_FQ_STATE_CGR_EN);
1859 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_CGID)
1860 fq->cgr_groupid = opts->fqd.cgid;
1862 fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1863 qman_fq_state_sched : qman_fq_state_parked;
1866 put_affine_portal();
1869 EXPORT_SYMBOL(qman_init_fq);
1871 int qman_schedule_fq(struct qman_fq *fq)
1873 union qm_mc_command *mcc;
1874 union qm_mc_result *mcr;
1875 struct qman_portal *p;
1878 if (fq->state != qman_fq_state_parked)
1880 #ifdef CONFIG_FSL_DPAA_CHECKING
1881 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1884 /* Issue a ALTERFQ_SCHED management command */
1885 p = get_affine_portal();
1886 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1887 fq->state != qman_fq_state_parked) {
1891 mcc = qm_mc_start(&p->p);
1892 qm_fqid_set(&mcc->fq, fq->fqid);
1893 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED);
1894 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1895 dev_err(p->config->dev, "ALTER_SCHED timeout\n");
1900 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED);
1901 if (mcr->result != QM_MCR_RESULT_OK) {
1905 fq->state = qman_fq_state_sched;
1907 put_affine_portal();
1910 EXPORT_SYMBOL(qman_schedule_fq);
1912 int qman_retire_fq(struct qman_fq *fq, u32 *flags)
1914 union qm_mc_command *mcc;
1915 union qm_mc_result *mcr;
1916 struct qman_portal *p;
1920 if (fq->state != qman_fq_state_parked &&
1921 fq->state != qman_fq_state_sched)
1923 #ifdef CONFIG_FSL_DPAA_CHECKING
1924 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1927 p = get_affine_portal();
1928 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1929 fq->state == qman_fq_state_retired ||
1930 fq->state == qman_fq_state_oos) {
1934 mcc = qm_mc_start(&p->p);
1935 qm_fqid_set(&mcc->fq, fq->fqid);
1936 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
1937 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1938 dev_crit(p->config->dev, "ALTER_RETIRE timeout\n");
1943 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE);
1946 * "Elegant" would be to treat OK/PENDING the same way; set CHANGING,
1947 * and defer the flags until FQRNI or FQRN (respectively) show up. But
1948 * "Friendly" is to process OK immediately, and not set CHANGING. We do
1949 * friendly, otherwise the caller doesn't necessarily have a fully
1950 * "retired" FQ on return even if the retirement was immediate. However
1951 * this does mean some code duplication between here and
1952 * fq_state_change().
1954 if (res == QM_MCR_RESULT_OK) {
1956 /* Process 'fq' right away, we'll ignore FQRNI */
1957 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY)
1958 fq_set(fq, QMAN_FQ_STATE_NE);
1959 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)
1960 fq_set(fq, QMAN_FQ_STATE_ORL);
1963 fq->state = qman_fq_state_retired;
1966 * Another issue with supporting "immediate" retirement
1967 * is that we're forced to drop FQRNIs, because by the
1968 * time they're seen it may already be "too late" (the
1969 * fq may have been OOS'd and free()'d already). But if
1970 * the upper layer wants a callback whether it's
1971 * immediate or not, we have to fake a "MR" entry to
1972 * look like an FQRNI...
1974 union qm_mr_entry msg;
1976 msg.verb = QM_MR_VERB_FQRNI;
1977 msg.fq.fqs = mcr->alterfq.fqs;
1978 qm_fqid_set(&msg.fq, fq->fqid);
1979 msg.fq.context_b = cpu_to_be32(fq_to_tag(fq));
1980 fq->cb.fqs(p, fq, &msg);
1982 } else if (res == QM_MCR_RESULT_PENDING) {
1984 fq_set(fq, QMAN_FQ_STATE_CHANGING);
1989 put_affine_portal();
1992 EXPORT_SYMBOL(qman_retire_fq);
1994 int qman_oos_fq(struct qman_fq *fq)
1996 union qm_mc_command *mcc;
1997 union qm_mc_result *mcr;
1998 struct qman_portal *p;
2001 if (fq->state != qman_fq_state_retired)
2003 #ifdef CONFIG_FSL_DPAA_CHECKING
2004 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
2007 p = get_affine_portal();
2008 if (fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS) ||
2009 fq->state != qman_fq_state_retired) {
2013 mcc = qm_mc_start(&p->p);
2014 qm_fqid_set(&mcc->fq, fq->fqid);
2015 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2016 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2020 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS);
2021 if (mcr->result != QM_MCR_RESULT_OK) {
2025 fq->state = qman_fq_state_oos;
2027 put_affine_portal();
2030 EXPORT_SYMBOL(qman_oos_fq);
2032 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
2034 union qm_mc_command *mcc;
2035 union qm_mc_result *mcr;
2036 struct qman_portal *p = get_affine_portal();
2039 mcc = qm_mc_start(&p->p);
2040 qm_fqid_set(&mcc->fq, fq->fqid);
2041 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2042 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2047 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2048 if (mcr->result == QM_MCR_RESULT_OK)
2049 *fqd = mcr->queryfq.fqd;
2053 put_affine_portal();
2057 int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np)
2059 union qm_mc_command *mcc;
2060 union qm_mc_result *mcr;
2061 struct qman_portal *p = get_affine_portal();
2064 mcc = qm_mc_start(&p->p);
2065 qm_fqid_set(&mcc->fq, fq->fqid);
2066 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2067 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2072 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2073 if (mcr->result == QM_MCR_RESULT_OK)
2074 *np = mcr->queryfq_np;
2075 else if (mcr->result == QM_MCR_RESULT_ERR_FQID)
2080 put_affine_portal();
2083 EXPORT_SYMBOL(qman_query_fq_np);
2085 static int qman_query_cgr(struct qman_cgr *cgr,
2086 struct qm_mcr_querycgr *cgrd)
2088 union qm_mc_command *mcc;
2089 union qm_mc_result *mcr;
2090 struct qman_portal *p = get_affine_portal();
2093 mcc = qm_mc_start(&p->p);
2094 mcc->cgr.cgid = cgr->cgrid;
2095 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR);
2096 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2100 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR);
2101 if (mcr->result == QM_MCR_RESULT_OK)
2102 *cgrd = mcr->querycgr;
2104 dev_err(p->config->dev, "QUERY_CGR failed: %s\n",
2105 mcr_result_str(mcr->result));
2109 put_affine_portal();
2113 int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result)
2115 struct qm_mcr_querycgr query_cgr;
2118 err = qman_query_cgr(cgr, &query_cgr);
2122 *result = !!query_cgr.cgr.cs;
2125 EXPORT_SYMBOL(qman_query_cgr_congested);
2127 /* internal function used as a wait_event() expression */
2128 static int set_p_vdqcr(struct qman_portal *p, struct qman_fq *fq, u32 vdqcr)
2130 unsigned long irqflags;
2133 local_irq_save(irqflags);
2136 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2139 fq_set(fq, QMAN_FQ_STATE_VDQCR);
2140 p->vdqcr_owned = fq;
2141 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2144 local_irq_restore(irqflags);
2148 static int set_vdqcr(struct qman_portal **p, struct qman_fq *fq, u32 vdqcr)
2152 *p = get_affine_portal();
2153 ret = set_p_vdqcr(*p, fq, vdqcr);
2154 put_affine_portal();
2158 static int wait_vdqcr_start(struct qman_portal **p, struct qman_fq *fq,
2159 u32 vdqcr, u32 flags)
2163 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2164 ret = wait_event_interruptible(affine_queue,
2165 !set_vdqcr(p, fq, vdqcr));
2167 wait_event(affine_queue, !set_vdqcr(p, fq, vdqcr));
2171 int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr)
2173 struct qman_portal *p;
2176 if (fq->state != qman_fq_state_parked &&
2177 fq->state != qman_fq_state_retired)
2179 if (vdqcr & QM_VDQCR_FQID_MASK)
2181 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2183 vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
2184 if (flags & QMAN_VOLATILE_FLAG_WAIT)
2185 ret = wait_vdqcr_start(&p, fq, vdqcr, flags);
2187 ret = set_vdqcr(&p, fq, vdqcr);
2191 if (flags & QMAN_VOLATILE_FLAG_FINISH) {
2192 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2194 * NB: don't propagate any error - the caller wouldn't
2195 * know whether the VDQCR was issued or not. A signal
2196 * could arrive after returning anyway, so the caller
2197 * can check signal_pending() if that's an issue.
2199 wait_event_interruptible(affine_queue,
2200 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2202 wait_event(affine_queue,
2203 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2207 EXPORT_SYMBOL(qman_volatile_dequeue);
2209 static void update_eqcr_ci(struct qman_portal *p, u8 avail)
2212 qm_eqcr_cce_prefetch(&p->p);
2214 qm_eqcr_cce_update(&p->p);
2217 int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd)
2219 struct qman_portal *p;
2220 struct qm_eqcr_entry *eq;
2221 unsigned long irqflags;
2224 p = get_affine_portal();
2225 local_irq_save(irqflags);
2227 if (p->use_eqcr_ci_stashing) {
2229 * The stashing case is easy, only update if we need to in
2230 * order to try and liberate ring entries.
2232 eq = qm_eqcr_start_stash(&p->p);
2235 * The non-stashing case is harder, need to prefetch ahead of
2238 avail = qm_eqcr_get_avail(&p->p);
2240 update_eqcr_ci(p, avail);
2241 eq = qm_eqcr_start_no_stash(&p->p);
2247 qm_fqid_set(eq, fq->fqid);
2248 eq->tag = cpu_to_be32(fq_to_tag(fq));
2251 qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE);
2253 local_irq_restore(irqflags);
2254 put_affine_portal();
2257 EXPORT_SYMBOL(qman_enqueue);
2259 static int qm_modify_cgr(struct qman_cgr *cgr, u32 flags,
2260 struct qm_mcc_initcgr *opts)
2262 union qm_mc_command *mcc;
2263 union qm_mc_result *mcr;
2264 struct qman_portal *p = get_affine_portal();
2265 u8 verb = QM_MCC_VERB_MODIFYCGR;
2268 mcc = qm_mc_start(&p->p);
2270 mcc->initcgr = *opts;
2271 mcc->initcgr.cgid = cgr->cgrid;
2272 if (flags & QMAN_CGR_FLAG_USE_INIT)
2273 verb = QM_MCC_VERB_INITCGR;
2274 qm_mc_commit(&p->p, verb);
2275 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2280 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb);
2281 if (mcr->result != QM_MCR_RESULT_OK)
2285 put_affine_portal();
2289 #define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0)
2291 /* congestion state change notification target update control */
2292 static void qm_cgr_cscn_targ_set(struct __qm_mc_cgr *cgr, int pi, u32 val)
2294 if (qman_ip_rev >= QMAN_REV30)
2295 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi |
2296 QM_CGR_TARG_UDP_CTRL_WRITE_BIT);
2298 cgr->cscn_targ = cpu_to_be32(val | QM_CGR_TARG_PORTAL(pi));
2301 static void qm_cgr_cscn_targ_clear(struct __qm_mc_cgr *cgr, int pi, u32 val)
2303 if (qman_ip_rev >= QMAN_REV30)
2304 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi);
2306 cgr->cscn_targ = cpu_to_be32(val & ~QM_CGR_TARG_PORTAL(pi));
2309 static u8 qman_cgr_cpus[CGR_NUM];
2311 void qman_init_cgr_all(void)
2313 struct qman_cgr cgr;
2316 for (cgr.cgrid = 0; cgr.cgrid < CGR_NUM; cgr.cgrid++) {
2317 if (qm_modify_cgr(&cgr, QMAN_CGR_FLAG_USE_INIT, NULL))
2322 pr_err("Warning: %d error%s while initialising CGR h/w\n",
2323 err_cnt, (err_cnt > 1) ? "s" : "");
2326 int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
2327 struct qm_mcc_initcgr *opts)
2329 struct qm_mcr_querycgr cgr_state;
2331 struct qman_portal *p;
2334 * We have to check that the provided CGRID is within the limits of the
2335 * data-structures, for obvious reasons. However we'll let h/w take
2336 * care of determining whether it's within the limits of what exists on
2339 if (cgr->cgrid >= CGR_NUM)
2343 p = get_affine_portal();
2344 qman_cgr_cpus[cgr->cgrid] = smp_processor_id();
2347 cgr->chan = p->config->channel;
2348 spin_lock(&p->cgr_lock);
2351 struct qm_mcc_initcgr local_opts = *opts;
2353 ret = qman_query_cgr(cgr, &cgr_state);
2357 qm_cgr_cscn_targ_set(&local_opts.cgr, PORTAL_IDX(p),
2358 be32_to_cpu(cgr_state.cgr.cscn_targ));
2359 local_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG);
2361 /* send init if flags indicate so */
2362 if (flags & QMAN_CGR_FLAG_USE_INIT)
2363 ret = qm_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT,
2366 ret = qm_modify_cgr(cgr, 0, &local_opts);
2371 list_add(&cgr->node, &p->cgr_cbs);
2373 /* Determine if newly added object requires its callback to be called */
2374 ret = qman_query_cgr(cgr, &cgr_state);
2376 /* we can't go back, so proceed and return success */
2377 dev_err(p->config->dev, "CGR HW state partially modified\n");
2381 if (cgr->cb && cgr_state.cgr.cscn_en &&
2382 qman_cgrs_get(&p->cgrs[1], cgr->cgrid))
2385 spin_unlock(&p->cgr_lock);
2386 put_affine_portal();
2389 EXPORT_SYMBOL(qman_create_cgr);
2391 int qman_delete_cgr(struct qman_cgr *cgr)
2393 unsigned long irqflags;
2394 struct qm_mcr_querycgr cgr_state;
2395 struct qm_mcc_initcgr local_opts;
2398 struct qman_portal *p = get_affine_portal();
2400 if (cgr->chan != p->config->channel) {
2401 /* attempt to delete from other portal than creator */
2402 dev_err(p->config->dev, "CGR not owned by current portal");
2403 dev_dbg(p->config->dev, " create 0x%x, delete 0x%x\n",
2404 cgr->chan, p->config->channel);
2409 memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2410 spin_lock_irqsave(&p->cgr_lock, irqflags);
2411 list_del(&cgr->node);
2413 * If there are no other CGR objects for this CGRID in the list,
2414 * update CSCN_TARG accordingly
2416 list_for_each_entry(i, &p->cgr_cbs, node)
2417 if (i->cgrid == cgr->cgrid && i->cb)
2419 ret = qman_query_cgr(cgr, &cgr_state);
2421 /* add back to the list */
2422 list_add(&cgr->node, &p->cgr_cbs);
2426 local_opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_TARG);
2427 qm_cgr_cscn_targ_clear(&local_opts.cgr, PORTAL_IDX(p),
2428 be32_to_cpu(cgr_state.cgr.cscn_targ));
2430 ret = qm_modify_cgr(cgr, 0, &local_opts);
2432 /* add back to the list */
2433 list_add(&cgr->node, &p->cgr_cbs);
2435 spin_unlock_irqrestore(&p->cgr_lock, irqflags);
2437 put_affine_portal();
2440 EXPORT_SYMBOL(qman_delete_cgr);
2443 struct qman_cgr *cgr;
2444 struct completion completion;
2447 static void qman_delete_cgr_smp_call(void *p)
2449 qman_delete_cgr((struct qman_cgr *)p);
2452 void qman_delete_cgr_safe(struct qman_cgr *cgr)
2455 if (qman_cgr_cpus[cgr->cgrid] != smp_processor_id()) {
2456 smp_call_function_single(qman_cgr_cpus[cgr->cgrid],
2457 qman_delete_cgr_smp_call, cgr, true);
2462 qman_delete_cgr(cgr);
2465 EXPORT_SYMBOL(qman_delete_cgr_safe);
2469 static int _qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
2471 const union qm_mr_entry *msg;
2474 qm_mr_pvb_update(p);
2475 msg = qm_mr_current(p);
2477 if ((msg->verb & QM_MR_VERB_TYPE_MASK) == v)
2480 qm_mr_cci_consume_to_current(p);
2481 qm_mr_pvb_update(p);
2482 msg = qm_mr_current(p);
2487 static int _qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s,
2490 const struct qm_dqrr_entry *dqrr;
2494 qm_dqrr_pvb_update(p);
2495 dqrr = qm_dqrr_current(p);
2498 } while (wait && !dqrr);
2501 if (qm_fqid_get(dqrr) == fqid && (dqrr->stat & s))
2503 qm_dqrr_cdc_consume_1ptr(p, dqrr, 0);
2504 qm_dqrr_pvb_update(p);
2506 dqrr = qm_dqrr_current(p);
2511 #define qm_mr_drain(p, V) \
2512 _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V)
2514 #define qm_dqrr_drain(p, f, S) \
2515 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false)
2517 #define qm_dqrr_drain_wait(p, f, S) \
2518 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true)
2520 #define qm_dqrr_drain_nomatch(p) \
2521 _qm_dqrr_consume_and_match(p, 0, 0, false)
2523 static int qman_shutdown_fq(u32 fqid)
2525 struct qman_portal *p;
2527 union qm_mc_command *mcc;
2528 union qm_mc_result *mcr;
2529 int orl_empty, drain = 0, ret = 0;
2530 u32 channel, wq, res;
2533 p = get_affine_portal();
2534 dev = p->config->dev;
2535 /* Determine the state of the FQID */
2536 mcc = qm_mc_start(&p->p);
2537 qm_fqid_set(&mcc->fq, fqid);
2538 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2539 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2540 dev_err(dev, "QUERYFQ_NP timeout\n");
2545 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2546 state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
2547 if (state == QM_MCR_NP_STATE_OOS)
2548 goto out; /* Already OOS, no need to do anymore checks */
2550 /* Query which channel the FQ is using */
2551 mcc = qm_mc_start(&p->p);
2552 qm_fqid_set(&mcc->fq, fqid);
2553 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2554 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2555 dev_err(dev, "QUERYFQ timeout\n");
2560 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2561 /* Need to store these since the MCR gets reused */
2562 channel = qm_fqd_get_chan(&mcr->queryfq.fqd);
2563 wq = qm_fqd_get_wq(&mcr->queryfq.fqd);
2566 case QM_MCR_NP_STATE_TEN_SCHED:
2567 case QM_MCR_NP_STATE_TRU_SCHED:
2568 case QM_MCR_NP_STATE_ACTIVE:
2569 case QM_MCR_NP_STATE_PARKED:
2571 mcc = qm_mc_start(&p->p);
2572 qm_fqid_set(&mcc->fq, fqid);
2573 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
2574 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2575 dev_err(dev, "QUERYFQ_NP timeout\n");
2579 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2580 QM_MCR_VERB_ALTER_RETIRE);
2581 res = mcr->result; /* Make a copy as we reuse MCR below */
2583 if (res == QM_MCR_RESULT_PENDING) {
2585 * Need to wait for the FQRN in the message ring, which
2586 * will only occur once the FQ has been drained. In
2587 * order for the FQ to drain the portal needs to be set
2588 * to dequeue from the channel the FQ is scheduled on
2593 /* Flag that we need to drain FQ */
2596 if (channel >= qm_channel_pool1 &&
2597 channel < qm_channel_pool1 + 15) {
2598 /* Pool channel, enable the bit in the portal */
2599 dequeue_wq = (channel -
2600 qm_channel_pool1 + 1)<<4 | wq;
2601 } else if (channel < qm_channel_pool1) {
2602 /* Dedicated channel */
2605 dev_err(dev, "Can't recover FQ 0x%x, ch: 0x%x",
2610 /* Set the sdqcr to drain this channel */
2611 if (channel < qm_channel_pool1)
2612 qm_dqrr_sdqcr_set(&p->p,
2613 QM_SDQCR_TYPE_ACTIVE |
2614 QM_SDQCR_CHANNELS_DEDICATED);
2616 qm_dqrr_sdqcr_set(&p->p,
2617 QM_SDQCR_TYPE_ACTIVE |
2618 QM_SDQCR_CHANNELS_POOL_CONV
2621 /* Keep draining DQRR while checking the MR*/
2622 qm_dqrr_drain_nomatch(&p->p);
2623 /* Process message ring too */
2624 found_fqrn = qm_mr_drain(&p->p, FQRN);
2626 } while (!found_fqrn);
2629 if (res != QM_MCR_RESULT_OK &&
2630 res != QM_MCR_RESULT_PENDING) {
2631 dev_err(dev, "retire_fq failed: FQ 0x%x, res=0x%x\n",
2636 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
2638 * ORL had no entries, no need to wait until the
2644 * Retirement succeeded, check to see if FQ needs
2647 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
2648 /* FQ is Not Empty, drain using volatile DQ commands */
2650 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
2652 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2654 * Wait for a dequeue and process the dequeues,
2655 * making sure to empty the ring completely
2657 } while (qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY));
2659 qm_dqrr_sdqcr_set(&p->p, 0);
2661 while (!orl_empty) {
2662 /* Wait for the ORL to have been completely drained */
2663 orl_empty = qm_mr_drain(&p->p, FQRL);
2666 mcc = qm_mc_start(&p->p);
2667 qm_fqid_set(&mcc->fq, fqid);
2668 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2669 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2674 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2675 QM_MCR_VERB_ALTER_OOS);
2676 if (mcr->result != QM_MCR_RESULT_OK) {
2677 dev_err(dev, "OOS after drain fail: FQ 0x%x (0x%x)\n",
2684 case QM_MCR_NP_STATE_RETIRED:
2685 /* Send OOS Command */
2686 mcc = qm_mc_start(&p->p);
2687 qm_fqid_set(&mcc->fq, fqid);
2688 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2689 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2694 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2695 QM_MCR_VERB_ALTER_OOS);
2697 dev_err(dev, "OOS fail: FQ 0x%x (0x%x)\n",
2704 case QM_MCR_NP_STATE_OOS:
2713 put_affine_portal();
2717 const struct qm_portal_config *qman_get_qm_portal_config(
2718 struct qman_portal *portal)
2720 return portal->config;
2722 EXPORT_SYMBOL(qman_get_qm_portal_config);
2724 struct gen_pool *qm_fqalloc; /* FQID allocator */
2725 struct gen_pool *qm_qpalloc; /* pool-channel allocator */
2726 struct gen_pool *qm_cgralloc; /* CGR ID allocator */
2728 static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt)
2735 addr = gen_pool_alloc(p, cnt);
2739 *result = addr & ~DPAA_GENALLOC_OFF;
2744 int qman_alloc_fqid_range(u32 *result, u32 count)
2746 return qman_alloc_range(qm_fqalloc, result, count);
2748 EXPORT_SYMBOL(qman_alloc_fqid_range);
2750 int qman_alloc_pool_range(u32 *result, u32 count)
2752 return qman_alloc_range(qm_qpalloc, result, count);
2754 EXPORT_SYMBOL(qman_alloc_pool_range);
2756 int qman_alloc_cgrid_range(u32 *result, u32 count)
2758 return qman_alloc_range(qm_cgralloc, result, count);
2760 EXPORT_SYMBOL(qman_alloc_cgrid_range);
2762 int qman_release_fqid(u32 fqid)
2764 int ret = qman_shutdown_fq(fqid);
2767 pr_debug("FQID %d leaked\n", fqid);
2771 gen_pool_free(qm_fqalloc, fqid | DPAA_GENALLOC_OFF, 1);
2774 EXPORT_SYMBOL(qman_release_fqid);
2776 static int qpool_cleanup(u32 qp)
2779 * We query all FQDs starting from
2780 * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs
2781 * whose destination channel is the pool-channel being released.
2782 * When a non-OOS FQD is found we attempt to clean it up
2784 struct qman_fq fq = {
2785 .fqid = QM_FQID_RANGE_START
2790 struct qm_mcr_queryfq_np np;
2792 err = qman_query_fq_np(&fq, &np);
2794 /* FQID range exceeded, found no problems */
2796 else if (WARN_ON(err))
2799 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2802 err = qman_query_fq(&fq, &fqd);
2805 if (qm_fqd_get_chan(&fqd) == qp) {
2806 /* The channel is the FQ's target, clean it */
2807 err = qman_shutdown_fq(fq.fqid);
2810 * Couldn't shut down the FQ
2811 * so the pool must be leaked
2816 /* Move to the next FQID */
2821 int qman_release_pool(u32 qp)
2825 ret = qpool_cleanup(qp);
2827 pr_debug("CHID %d leaked\n", qp);
2831 gen_pool_free(qm_qpalloc, qp | DPAA_GENALLOC_OFF, 1);
2834 EXPORT_SYMBOL(qman_release_pool);
2836 static int cgr_cleanup(u32 cgrid)
2839 * query all FQDs starting from FQID 1 until we get an "invalid FQID"
2840 * error, looking for non-OOS FQDs whose CGR is the CGR being released
2842 struct qman_fq fq = {
2843 .fqid = QM_FQID_RANGE_START
2848 struct qm_mcr_queryfq_np np;
2850 err = qman_query_fq_np(&fq, &np);
2852 /* FQID range exceeded, found no problems */
2854 else if (WARN_ON(err))
2857 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2860 err = qman_query_fq(&fq, &fqd);
2863 if (be16_to_cpu(fqd.fq_ctrl) & QM_FQCTRL_CGE &&
2864 fqd.cgid == cgrid) {
2865 pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n",
2870 /* Move to the next FQID */
2875 int qman_release_cgrid(u32 cgrid)
2879 ret = cgr_cleanup(cgrid);
2881 pr_debug("CGRID %d leaked\n", cgrid);
2885 gen_pool_free(qm_cgralloc, cgrid | DPAA_GENALLOC_OFF, 1);
2888 EXPORT_SYMBOL(qman_release_cgrid);