1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom STB SoCs Bus Unit Interface controls
5 * Copyright (C) 2015, Broadcom Corporation
8 #define pr_fmt(fmt) "brcmstb: " KBUILD_MODNAME ": " fmt
10 #include <linux/kernel.h>
12 #include <linux/of_address.h>
13 #include <linux/syscore_ops.h>
14 #include <linux/soc/brcmstb/brcmstb.h>
16 #define RACENPREF_MASK 0x3
17 #define RACPREFINST_SHIFT 0
18 #define RACENINST_SHIFT 2
19 #define RACPREFDATA_SHIFT 4
20 #define RACENDATA_SHIFT 6
21 #define RAC_CPU_SHIFT 8
22 #define RACCFG_MASK 0xff
23 #define DPREF_LINE_2_SHIFT 24
24 #define DPREF_LINE_2_MASK 0xff
26 /* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
27 #define RAC_DATA_INST_EN_MASK (1 << RACPREFINST_SHIFT | \
28 RACENPREF_MASK << RACENINST_SHIFT | \
29 1 << RACPREFDATA_SHIFT | \
30 RACENPREF_MASK << RACENDATA_SHIFT)
32 #define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
33 #define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf
34 #define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf
35 #define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) ((x) * 8)
36 #define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4)
38 #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) ((x) * 8)
39 #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK 0xff
41 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK 0xf
42 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK 0xf
43 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT 4
44 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8)
46 static void __iomem *cpubiuctrl_base;
47 static bool mcp_wr_pairing_en;
48 static const int *cpubiuctrl_regs;
50 enum cpubiuctrl_regs {
53 CPU_WRITEBACK_CTRL_REG,
59 static inline u32 cbc_readl(int reg)
61 int offset = cpubiuctrl_regs[reg];
64 (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
67 return readl_relaxed(cpubiuctrl_base + offset);
70 static inline void cbc_writel(u32 val, int reg)
72 int offset = cpubiuctrl_regs[reg];
75 (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
78 writel(val, cpubiuctrl_base + offset);
81 static const int b15_cpubiuctrl_regs[] = {
82 [CPU_CREDIT_REG] = 0x184,
83 [CPU_MCP_FLOW_REG] = -1,
84 [CPU_WRITEBACK_CTRL_REG] = -1,
85 [RAC_CONFIG0_REG] = -1,
86 [RAC_CONFIG1_REG] = -1,
89 /* Odd cases, e.g: 7260A0 */
90 static const int b53_cpubiuctrl_no_wb_regs[] = {
91 [CPU_CREDIT_REG] = 0x0b0,
92 [CPU_MCP_FLOW_REG] = 0x0b4,
93 [CPU_WRITEBACK_CTRL_REG] = -1,
94 [RAC_CONFIG0_REG] = 0x78,
95 [RAC_CONFIG1_REG] = 0x7c,
98 static const int b53_cpubiuctrl_regs[] = {
99 [CPU_CREDIT_REG] = 0x0b0,
100 [CPU_MCP_FLOW_REG] = 0x0b4,
101 [CPU_WRITEBACK_CTRL_REG] = 0x22c,
102 [RAC_CONFIG0_REG] = 0x78,
103 [RAC_CONFIG1_REG] = 0x7c,
106 static const int a72_cpubiuctrl_regs[] = {
107 [CPU_CREDIT_REG] = 0x18,
108 [CPU_MCP_FLOW_REG] = 0x1c,
109 [CPU_WRITEBACK_CTRL_REG] = 0x20,
110 [RAC_CONFIG0_REG] = 0x08,
111 [RAC_CONFIG1_REG] = 0x0c,
114 static int __init mcp_write_pairing_set(void)
118 if (!cpubiuctrl_base)
121 creds = cbc_readl(CPU_CREDIT_REG);
122 if (mcp_wr_pairing_en) {
123 pr_info("MCP: Enabling write pairing\n");
124 cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
126 } else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
127 pr_info("MCP: Disabling write pairing\n");
128 cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
131 pr_info("MCP: Write pairing already disabled\n");
137 static const u32 a72_b53_mach_compat[] = {
151 /* The read-ahead cache present in the Brahma-B53 CPU is a special piece of
152 * hardware after the integrated L2 cache of the B53 CPU complex whose purpose
153 * is to prefetch instruction and/or data with a line size of either 64 bytes
154 * or 256 bytes. The rationale is that the data-bus of the CPU interface is
155 * optimized for 256-byte transactions, and enabling the read-ahead cache
156 * provides a significant performance boost (typically twice the performance
157 * for a memcpy benchmark application).
159 * The read-ahead cache is transparent for Virtual Address cache maintenance
160 * operations: IC IVAU, DC IVAC, DC CVAC, DC CVAU and DC CIVAC. So no special
161 * handling is needed for the DMA API above and beyond what is included in the
162 * arm64 implementation.
164 * In addition, since the Point of Unification is typically between L1 and L2
165 * for the Brahma-B53 processor no special read-ahead cache handling is needed
166 * for the IC IALLU and IC IALLUIS cache maintenance operations.
168 * However, it is not possible to specify the cache level (L3) for the cache
169 * maintenance instructions operating by set/way to operate on the read-ahead
170 * cache. The read-ahead cache will maintain coherency when inner cache lines
171 * are cleaned by set/way, but if it is necessary to invalidate inner cache
172 * lines by set/way to maintain coherency with system masters operating on
173 * shared memory that does not have hardware support for coherency, then it
174 * will also be necessary to explicitly invalidate the read-ahead cache.
176 static void __init a72_b53_rac_enable_all(struct device_node *np)
179 u32 enable = 0, pref_dist, shift;
181 if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
184 if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
187 pref_dist = cbc_readl(RAC_CONFIG1_REG);
188 for_each_possible_cpu(cpu) {
189 shift = cpu * RAC_CPU_SHIFT + RACPREFDATA_SHIFT;
190 enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
191 if (cpubiuctrl_regs == a72_cpubiuctrl_regs) {
192 enable &= ~(RACENPREF_MASK << shift);
193 enable |= 3 << shift;
194 pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
198 cbc_writel(enable, RAC_CONFIG0_REG);
199 cbc_writel(pref_dist, RAC_CONFIG1_REG);
201 pr_info("%pOF: Broadcom %s read-ahead cache\n",
202 np, cpubiuctrl_regs == a72_cpubiuctrl_regs ?
203 "Cortex-A72" : "Brahma-B53");
206 static void __init mcp_a72_b53_set(void)
211 reg = brcmstb_get_family_id();
213 for (i = 0; i < ARRAY_SIZE(a72_b53_mach_compat); i++) {
214 if (BRCM_ID(reg) == a72_b53_mach_compat[i])
218 if (i == ARRAY_SIZE(a72_b53_mach_compat))
221 /* Set all 3 MCP interfaces to 8 credits */
222 reg = cbc_readl(CPU_CREDIT_REG);
223 for (i = 0; i < 3; i++) {
224 reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
225 CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i));
226 reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
227 CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i));
228 reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
229 reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
231 cbc_writel(reg, CPU_CREDIT_REG);
233 /* Max out the number of in-flight Jwords reads on the MCP interface */
234 reg = cbc_readl(CPU_MCP_FLOW_REG);
235 for (i = 0; i < 3; i++)
236 reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
237 CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i);
238 cbc_writel(reg, CPU_MCP_FLOW_REG);
240 /* Enable writeback throttling, set timeout to 128 cycles, 256 cycles
243 reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
244 reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
245 reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
246 reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
247 CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT);
249 reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
250 cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);
253 static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
255 struct device_node *cpu_dn;
259 cpubiuctrl_base = of_iomap(np, 0);
260 if (!cpubiuctrl_base) {
261 pr_err("failed to remap BIU control base\n");
266 mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
268 cpu_dn = of_get_cpu_node(0, NULL);
270 pr_err("failed to obtain CPU device node\n");
275 if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
276 cpubiuctrl_regs = b15_cpubiuctrl_regs;
277 else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
278 cpubiuctrl_regs = b53_cpubiuctrl_regs;
279 else if (of_device_is_compatible(cpu_dn, "arm,cortex-a72"))
280 cpubiuctrl_regs = a72_cpubiuctrl_regs;
282 pr_err("unsupported CPU\n");
287 family_id = brcmstb_get_family_id();
288 if (BRCM_ID(family_id) == 0x7260 && BRCM_REV(family_id) == 0)
289 cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs;
294 #ifdef CONFIG_PM_SLEEP
295 static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS];
297 static int brcmstb_cpu_credit_reg_suspend(void)
301 if (!cpubiuctrl_base)
304 for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
305 cpubiuctrl_reg_save[i] = cbc_readl(i);
310 static void brcmstb_cpu_credit_reg_resume(void)
314 if (!cpubiuctrl_base)
317 for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
318 cbc_writel(cpubiuctrl_reg_save[i], i);
321 static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
322 .suspend = brcmstb_cpu_credit_reg_suspend,
323 .resume = brcmstb_cpu_credit_reg_resume,
328 static int __init brcmstb_biuctrl_init(void)
330 struct device_node *np;
333 /* We might be running on a multi-platform kernel, don't make this a
334 * fatal error, just bail out early
336 np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
340 ret = setup_hifcpubiuctrl_regs(np);
344 ret = mcp_write_pairing_set();
346 pr_err("MCP: Unable to disable write pairing!\n");
350 a72_b53_rac_enable_all(np);
352 #ifdef CONFIG_PM_SLEEP
353 register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
360 early_initcall(brcmstb_biuctrl_init);