2 * SuperH Pin Function Controller support.
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
12 #define DRV_NAME "sh-pfc"
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/platform_device.h>
24 #include <linux/sh_pfc.h>
25 #include <linux/slab.h>
29 static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
34 if (pdev->num_resources == 0) {
39 pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
40 sizeof(*pfc->window), GFP_NOWAIT);
44 pfc->num_windows = pdev->num_resources;
46 for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
47 WARN_ON(resource_type(res) != IORESOURCE_MEM);
48 pfc->window[k].phys = res->start;
49 pfc->window[k].size = resource_size(res);
50 pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
52 if (!pfc->window[k].virt)
59 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
60 unsigned long address)
62 struct sh_pfc_window *window;
65 /* scan through physical windows and convert address */
66 for (k = 0; k < pfc->num_windows; k++) {
67 window = pfc->window + k;
69 if (address < window->phys)
72 if (address >= (window->phys + window->size))
75 return window->virt + (address - window->phys);
78 /* no windows defined, register must be 1:1 mapped virt:phys */
79 return (void __iomem *)address;
82 static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
84 if (enum_id < r->begin)
93 static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
94 unsigned long reg_width)
98 return ioread8(mapped_reg);
100 return ioread16(mapped_reg);
102 return ioread32(mapped_reg);
109 static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
110 unsigned long reg_width, unsigned long data)
114 iowrite8(data, mapped_reg);
117 iowrite16(data, mapped_reg);
120 iowrite32(data, mapped_reg);
127 int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
131 pos = dr->reg_width - (in_pos + 1);
133 pr_debug("read_bit: addr = %lx, pos = %ld, "
134 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
136 return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
139 void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
144 pos = dr->reg_width - (in_pos + 1);
146 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
148 dr->reg, !!value, pos, dr->reg_width);
151 set_bit(pos, &dr->reg_shadow);
153 clear_bit(pos, &dr->reg_shadow);
155 sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
158 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
159 struct pinmux_cfg_reg *crp,
160 unsigned long in_pos,
161 void __iomem **mapped_regp,
162 unsigned long *maskp,
167 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
169 if (crp->field_width) {
170 *maskp = (1 << crp->field_width) - 1;
171 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
173 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
174 *posp = crp->reg_width;
175 for (k = 0; k <= in_pos; k++)
176 *posp -= crp->var_field_width[k];
180 static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
181 struct pinmux_cfg_reg *crp,
184 void __iomem *mapped_reg;
185 unsigned long mask, pos;
187 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
189 pr_debug("read_reg: addr = %lx, field = %ld, "
190 "r_width = %ld, f_width = %ld\n",
191 crp->reg, field, crp->reg_width, crp->field_width);
193 return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
196 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
197 struct pinmux_cfg_reg *crp,
198 unsigned long field, unsigned long value)
200 void __iomem *mapped_reg;
201 unsigned long mask, pos, data;
203 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
205 pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
206 "r_width = %ld, f_width = %ld\n",
207 crp->reg, value, field, crp->reg_width, crp->field_width);
209 mask = ~(mask << pos);
210 value = value << pos;
212 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
216 if (pfc->pdata->unlock_reg)
217 sh_pfc_write_raw_reg(
218 sh_pfc_phys_to_virt(pfc, pfc->pdata->unlock_reg), 32,
221 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
224 static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
226 struct pinmux_gpio *gpiop = &pfc->pdata->gpios[gpio];
227 struct pinmux_data_reg *data_reg;
230 if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->pdata->data))
235 data_reg = pfc->pdata->data_regs + k;
237 if (!data_reg->reg_width)
240 data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
242 for (n = 0; n < data_reg->reg_width; n++) {
243 if (data_reg->enum_ids[n] == gpiop->enum_id) {
244 gpiop->flags &= ~PINMUX_FLAG_DREG;
245 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
246 gpiop->flags &= ~PINMUX_FLAG_DBIT;
247 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
259 static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
261 struct pinmux_data_reg *drp;
264 for (k = pfc->pdata->first_gpio; k <= pfc->pdata->last_gpio; k++)
265 sh_pfc_setup_data_reg(pfc, k);
269 drp = pfc->pdata->data_regs + k;
274 drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
280 int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
281 struct pinmux_data_reg **drp, int *bitp)
283 struct pinmux_gpio *gpiop = &pfc->pdata->gpios[gpio];
286 if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->pdata->data))
289 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
290 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
291 *drp = pfc->pdata->data_regs + k;
296 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
297 struct pinmux_cfg_reg **crp, int *fieldp,
298 int *valuep, unsigned long **cntp)
300 struct pinmux_cfg_reg *config_reg;
301 unsigned long r_width, f_width, curr_width, ncomb;
302 int k, m, n, pos, bit_pos;
306 config_reg = pfc->pdata->cfg_regs + k;
308 r_width = config_reg->reg_width;
309 f_width = config_reg->field_width;
316 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
318 curr_width = f_width;
320 curr_width = config_reg->var_field_width[m];
322 ncomb = 1 << curr_width;
323 for (n = 0; n < ncomb; n++) {
324 if (config_reg->enum_ids[pos + n] == enum_id) {
328 *cntp = &config_reg->cnt[m];
341 int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
342 pinmux_enum_t *enum_idp)
344 pinmux_enum_t enum_id = pfc->pdata->gpios[gpio].enum_id;
345 pinmux_enum_t *data = pfc->pdata->gpio_data;
348 if (!sh_pfc_enum_in_range(enum_id, &pfc->pdata->data)) {
349 if (!sh_pfc_enum_in_range(enum_id, &pfc->pdata->mark)) {
350 pr_err("non data/mark enum_id for gpio %d\n", gpio);
356 *enum_idp = data[pos + 1];
360 for (k = 0; k < pfc->pdata->gpio_data_size; k++) {
361 if (data[k] == enum_id) {
362 *enum_idp = data[k + 1];
367 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
371 int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
374 struct pinmux_cfg_reg *cr = NULL;
375 pinmux_enum_t enum_id;
376 struct pinmux_range *range;
377 int in_range, pos, field, value;
380 switch (pinmux_type) {
382 case PINMUX_TYPE_FUNCTION:
386 case PINMUX_TYPE_OUTPUT:
387 range = &pfc->pdata->output;
390 case PINMUX_TYPE_INPUT:
391 range = &pfc->pdata->input;
394 case PINMUX_TYPE_INPUT_PULLUP:
395 range = &pfc->pdata->input_pu;
398 case PINMUX_TYPE_INPUT_PULLDOWN:
399 range = &pfc->pdata->input_pd;
411 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
418 /* first check if this is a function enum */
419 in_range = sh_pfc_enum_in_range(enum_id, &pfc->pdata->function);
421 /* not a function enum */
424 * other range exists, so this pin is
425 * a regular GPIO pin that now is being
426 * bound to a specific direction.
428 * for this case we only allow function enums
429 * and the enums that match the other range.
431 in_range = sh_pfc_enum_in_range(enum_id, range);
434 * special case pass through for fixed
435 * input-only or output-only pins without
436 * function enum register association.
438 if (in_range && enum_id == range->force)
442 * no other range exists, so this pin
443 * must then be of the function type.
445 * allow function type pins to select
446 * any combination of function/in/out
447 * in their MARK lists.
456 if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
457 &field, &value, &cntp) != 0)
461 case GPIO_CFG_DRYRUN:
463 (sh_pfc_read_config_reg(pfc, cr, field) != value))
468 sh_pfc_write_config_reg(pfc, cr, field, value);
483 static int sh_pfc_probe(struct platform_device *pdev)
485 struct sh_pfc_platform_data *pdata = pdev->dev.platform_data;
490 * Ensure that the type encoding fits
492 BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
497 pfc = devm_kzalloc(&pdev->dev, sizeof(pfc), GFP_KERNEL);
502 pfc->dev = &pdev->dev;
504 ret = sh_pfc_ioremap(pfc, pdev);
505 if (unlikely(ret < 0))
508 spin_lock_init(&pfc->lock);
510 pinctrl_provide_dummies();
511 sh_pfc_setup_data_regs(pfc);
514 * Initialize pinctrl bindings first
516 ret = sh_pfc_register_pinctrl(pfc);
517 if (unlikely(ret != 0))
520 #ifdef CONFIG_GPIO_SH_PFC
524 ret = sh_pfc_register_gpiochip(pfc);
525 if (unlikely(ret != 0)) {
527 * If the GPIO chip fails to come up we still leave the
528 * PFC state as it is, given that there are already
529 * extant users of it that have succeeded by this point.
531 pr_notice("failed to init GPIO chip, ignoring...\n");
535 platform_set_drvdata(pdev, pfc);
537 pr_info("%s support registered\n", pdata->name);
542 static int sh_pfc_remove(struct platform_device *pdev)
544 struct sh_pfc *pfc = platform_get_drvdata(pdev);
546 #ifdef CONFIG_GPIO_SH_PFC
547 sh_pfc_unregister_gpiochip(pfc);
549 sh_pfc_unregister_pinctrl(pfc);
551 platform_set_drvdata(pdev, NULL);
556 static const struct platform_device_id sh_pfc_id_table[] = {
560 MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
562 static struct platform_driver sh_pfc_driver = {
563 .probe = sh_pfc_probe,
564 .remove = sh_pfc_remove,
565 .id_table = sh_pfc_id_table,
568 .owner = THIS_MODULE,
572 static int __init sh_pfc_init(void)
574 return platform_driver_register(&sh_pfc_driver);
576 postcore_initcall(sh_pfc_init);
578 static void __exit sh_pfc_exit(void)
580 platform_driver_unregister(&sh_pfc_driver);
582 module_exit(sh_pfc_exit);
584 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
585 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
586 MODULE_LICENSE("GPL v2");