1 #include <linux/serial_core.h>
5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6 #include <asm/regs306x.h>
8 #if defined(CONFIG_H8S2678)
9 #include <asm/regs267x.h>
12 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20 # define SCIF0 0xA4400000
21 # define SCIF2 0xA4410000
22 # define SCSMR_Ir 0xA44A0000
23 # define IRDA_SCIF SCIF0
24 # define SCPCR 0xA4000116
25 # define SCPDR 0xA4000136
27 /* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
31 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721)
34 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
35 #define SCIF_ORER 0x0200 /* overrun error bit */
36 #elif defined(CONFIG_SH_RTS7751R2D)
37 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
38 # define SCIF_ORER 0x0001 /* overrun error bit */
39 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
40 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
41 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
42 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
43 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
44 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7751R)
46 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
47 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
48 # define SCIF_ORER 0x0001 /* overrun error bit */
49 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
50 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
51 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
52 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
53 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
54 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
55 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
56 # define SCIF_ORER 0x0001 /* overrun error bit */
57 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
58 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
59 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
60 # define SCIF_ORER 0x0001 /* overrun error bit */
61 # define PACR 0xa4050100
62 # define PBCR 0xa4050102
63 # define SCSCR_INIT(port) 0x3B
64 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
65 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
66 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
67 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
68 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
69 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
70 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
71 # define PADR 0xA4050120
72 # define PSDR 0xA405013e
73 # define PWDR 0xA4050166
74 # define PSCR 0xA405011E
75 # define SCIF_ORER 0x0001 /* overrun error bit */
76 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
77 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
78 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
79 # define SCSPTR0 SCPDR0
80 # define SCIF_ORER 0x0001 /* overrun error bit */
81 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
83 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
84 # define SCSPTR0 0xa4050160
85 # define SCSPTR1 0xa405013e
86 # define SCSPTR2 0xa4050160
87 # define SCSPTR3 0xa405013e
88 # define SCSPTR4 0xa4050128
89 # define SCSPTR5 0xa4050128
90 # define SCIF_ORER 0x0001 /* overrun error bit */
91 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
92 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
93 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
94 # define SCIF_ORER 0x0001 /* overrun error bit */
95 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
96 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
97 # define SCIF_BASE_ADDR 0x01030000
98 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
99 # define SCIF_PTR2_OFFS 0x0000020
100 # define SCIF_LSR2_OFFS 0x0000024
101 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
102 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
103 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
104 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
105 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
106 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
107 #elif defined(CONFIG_H8S2678)
108 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
109 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
110 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
111 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
112 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
113 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
114 # define SCIF_ORER 0x0001 /* overrun error bit */
115 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
116 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
117 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
118 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
119 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
120 # define SCIF_ORER 0x0001 /* overrun error bit */
121 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
122 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
123 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
124 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
125 # define SCIF_ORER 0x0001 /* Overrun error bit */
126 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
127 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
128 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
129 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
130 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
131 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
132 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
133 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
134 # define SCIF_OPER 0x0001 /* Overrun error bit */
135 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
136 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
137 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
138 defined(CONFIG_CPU_SUBTYPE_SH7263)
139 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
140 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
141 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
142 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
143 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
144 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
145 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
146 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
147 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
148 # define SCIF_ORER 0x0001 /* overrun error bit */
149 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
150 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
151 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
152 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
153 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
154 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
155 # define SCIF_ORER 0x0001 /* Overrun error bit */
156 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
158 # error CPU subtype not defined
162 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
163 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
164 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
165 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
166 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
167 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
168 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
169 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
170 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
171 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
172 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
173 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
174 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
175 defined(CONFIG_CPU_SUBTYPE_SHX3)
176 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
178 #define SCI_CTRL_FLAGS_REIE 0
180 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
181 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
182 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
183 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
186 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
187 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
188 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
189 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
190 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
191 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
192 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
193 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
195 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
198 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
199 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
200 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
201 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
202 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
203 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
204 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
205 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
207 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
208 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
209 defined(CONFIG_CPU_SUBTYPE_SH7721)
210 # define SCIF_ORER 0x0200
211 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
212 # define SCIF_RFDC_MASK 0x007f
213 # define SCIF_TXROOM_MAX 64
214 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
215 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
216 # define SCIF_RFDC_MASK 0x007f
217 # define SCIF_TXROOM_MAX 64
218 /* SH7763 SCIF2 support */
219 # define SCIF2_RFDC_MASK 0x001f
220 # define SCIF2_TXROOM_MAX 16
222 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
223 # define SCIF_RFDC_MASK 0x001f
224 # define SCIF_TXROOM_MAX 16
227 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
228 #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
229 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
230 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
231 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
232 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
233 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
235 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
236 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
238 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
241 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
242 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
243 defined(CONFIG_CPU_SUBTYPE_SH7721)
244 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
245 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
246 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
247 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
249 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
250 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
251 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
252 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
256 #define SCFCR_RFRST 0x0002
257 #define SCFCR_TFRST 0x0004
258 #define SCFCR_TCRST 0x4000
259 #define SCFCR_MCE 0x0008
261 #define SCI_MAJOR 204
262 #define SCI_MINOR_START 8
264 /* Generic serial flags */
265 #define SCI_RX_THROTTLE 0x0000001
267 #define SCI_MAGIC 0xbabeface
270 * Events are used to schedule things to happen at timer-interrupt
271 * time, instead of at rs interrupt time.
273 #define SCI_EVENT_WRITE_WAKEUP 0
275 #define SCI_IN(size, offset) \
277 return ioread8(port->membase + (offset)); \
279 return ioread16(port->membase + (offset)); \
281 #define SCI_OUT(size, offset, value) \
283 iowrite8(value, port->membase + (offset)); \
284 } else if ((size) == 16) { \
285 iowrite16(value, port->membase + (offset)); \
288 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
289 static inline unsigned int sci_##name##_in(struct uart_port *port) \
291 if (port->type == PORT_SCI) { \
292 SCI_IN(sci_size, sci_offset) \
294 SCI_IN(scif_size, scif_offset); \
297 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
299 if (port->type == PORT_SCI) { \
300 SCI_OUT(sci_size, sci_offset, value) \
302 SCI_OUT(scif_size, scif_offset, value); \
306 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
307 static inline unsigned int sci_##name##_in(struct uart_port *port) \
309 SCI_IN(scif_size, scif_offset); \
311 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
313 SCI_OUT(scif_size, scif_offset, value); \
316 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
317 static inline unsigned int sci_##name##_in(struct uart_port* port) \
319 SCI_IN(sci_size, sci_offset); \
321 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
323 SCI_OUT(sci_size, sci_offset, value); \
326 #ifdef CONFIG_CPU_SH3
327 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
328 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
329 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
330 h8_sci_offset, h8_sci_size) \
331 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
332 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
333 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
334 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
335 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
336 defined(CONFIG_CPU_SUBTYPE_SH7721)
337 #define SCIF_FNS(name, scif_offset, scif_size) \
338 CPU_SCIF_FNS(name, scif_offset, scif_size)
340 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
341 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
342 h8_sci_offset, h8_sci_size) \
343 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
344 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
345 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
347 #elif defined(__H8300H__) || defined(__H8300S__)
348 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
349 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
350 h8_sci_offset, h8_sci_size) \
351 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
352 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
353 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
354 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
355 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
356 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
357 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
359 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
360 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
361 h8_sci_offset, h8_sci_size) \
362 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
363 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
364 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
367 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
368 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
369 defined(CONFIG_CPU_SUBTYPE_SH7721)
371 SCIF_FNS(SCSMR, 0x00, 16)
372 SCIF_FNS(SCBRR, 0x04, 8)
373 SCIF_FNS(SCSCR, 0x08, 16)
374 SCIF_FNS(SCTDSR, 0x0c, 8)
375 SCIF_FNS(SCFER, 0x10, 16)
376 SCIF_FNS(SCxSR, 0x14, 16)
377 SCIF_FNS(SCFCR, 0x18, 16)
378 SCIF_FNS(SCFDR, 0x1c, 16)
379 SCIF_FNS(SCxTDR, 0x20, 8)
380 SCIF_FNS(SCxRDR, 0x24, 8)
381 SCIF_FNS(SCLSR, 0x24, 16)
382 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
383 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
384 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
385 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
386 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
387 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
388 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
389 SCIF_FNS(SCTDSR, 0x0c, 8)
390 SCIF_FNS(SCFER, 0x10, 16)
391 SCIF_FNS(SCFCR, 0x18, 16)
392 SCIF_FNS(SCFDR, 0x1c, 16)
393 SCIF_FNS(SCLSR, 0x24, 16)
395 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
396 /* name off sz off sz off sz off sz off sz*/
397 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
398 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
399 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
400 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
401 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
402 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
403 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
404 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
405 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
406 defined(CONFIG_CPU_SUBTYPE_SH7785)
407 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
408 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
409 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
410 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
411 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
412 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
413 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
414 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
415 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
416 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
417 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
418 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
419 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
421 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
422 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
423 SCIF_FNS(SCSPTR, 0, 0, 0, 0)
425 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
427 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
430 #define sci_in(port, reg) sci_##reg##_in(port)
431 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
433 /* H8/300 series SCI pins assignment */
434 #if defined(__H8300H__) || defined(__H8300S__)
435 static const struct __attribute__((packed)) {
436 int port; /* GPIO port no */
437 unsigned short rx,tx; /* GPIO bit no */
438 } h8300_sci_pins[] = {
439 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
441 .port = H8300_GPIO_P9,
446 .port = H8300_GPIO_P9,
451 .port = H8300_GPIO_PB,
455 #elif defined(CONFIG_H8S2678)
457 .port = H8300_GPIO_P3,
462 .port = H8300_GPIO_P3,
467 .port = H8300_GPIO_P5,
475 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
476 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
477 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
478 defined(CONFIG_CPU_SUBTYPE_SH7709)
479 static inline int sci_rxd_in(struct uart_port *port)
481 if (port->mapbase == 0xfffffe80)
482 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
483 if (port->mapbase == 0xa4000150)
484 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
485 if (port->mapbase == 0xa4000140)
486 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
489 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
490 static inline int sci_rxd_in(struct uart_port *port)
492 if (port->mapbase == SCIF0)
493 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
494 if (port->mapbase == SCIF2)
495 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
498 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
499 static inline int sci_rxd_in(struct uart_port *port)
501 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
503 static inline void set_sh771x_scif_pfc(struct uart_port *port)
505 if (port->mapbase == 0xA4400000){
506 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
507 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
510 if (port->mapbase == 0xA4410000){
511 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
515 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
516 defined(CONFIG_CPU_SUBTYPE_SH7721)
517 static inline int sci_rxd_in(struct uart_port *port)
519 if (port->mapbase == 0xa4430000)
520 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
521 else if (port->mapbase == 0xa4438000)
522 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
525 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
526 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
527 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
528 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
529 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
530 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
531 defined(CONFIG_CPU_SUBTYPE_SH4_202)
532 static inline int sci_rxd_in(struct uart_port *port)
534 if (port->mapbase == 0xffe00000)
535 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
536 if (port->mapbase == 0xffe80000)
537 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
540 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
541 static inline int sci_rxd_in(struct uart_port *port)
543 if (port->mapbase == 0xfe600000)
544 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
545 if (port->mapbase == 0xfe610000)
546 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
547 if (port->mapbase == 0xfe620000)
548 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
551 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
552 static inline int sci_rxd_in(struct uart_port *port)
554 if (port->mapbase == 0xffe00000)
555 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
556 if (port->mapbase == 0xffe10000)
557 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
558 if (port->mapbase == 0xffe20000)
559 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
560 if (port->mapbase == 0xffe30000)
561 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
564 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
565 static inline int sci_rxd_in(struct uart_port *port)
567 if (port->mapbase == 0xffe00000)
568 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
571 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
572 static inline int sci_rxd_in(struct uart_port *port)
574 if (port->mapbase == 0xffe00000)
575 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
576 if (port->mapbase == 0xffe10000)
577 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
578 if (port->mapbase == 0xffe20000)
579 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
583 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
584 static inline int sci_rxd_in(struct uart_port *port)
586 if (port->mapbase == 0xffe00000)
587 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
588 if (port->mapbase == 0xffe10000)
589 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
590 if (port->mapbase == 0xffe20000)
591 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
592 if (port->mapbase == 0xa4e30000)
593 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
594 if (port->mapbase == 0xa4e40000)
595 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
596 if (port->mapbase == 0xa4e50000)
597 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
600 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
601 static inline int sci_rxd_in(struct uart_port *port)
603 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
605 #elif defined(__H8300H__) || defined(__H8300S__)
606 static inline int sci_rxd_in(struct uart_port *port)
608 int ch = (port->mapbase - SMR0) >> 3;
609 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
611 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
612 static inline int sci_rxd_in(struct uart_port *port)
614 if (port->mapbase == 0xffe00000)
615 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
616 if (port->mapbase == 0xffe08000)
617 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
618 if (port->mapbase == 0xffe10000)
619 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
623 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
624 static inline int sci_rxd_in(struct uart_port *port)
626 if (port->mapbase == 0xff923000)
627 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
628 if (port->mapbase == 0xff924000)
629 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
630 if (port->mapbase == 0xff925000)
631 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
634 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
635 static inline int sci_rxd_in(struct uart_port *port)
637 if (port->mapbase == 0xffe00000)
638 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
639 if (port->mapbase == 0xffe10000)
640 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
643 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
644 static inline int sci_rxd_in(struct uart_port *port)
646 if (port->mapbase == 0xffea0000)
647 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
648 if (port->mapbase == 0xffeb0000)
649 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
650 if (port->mapbase == 0xffec0000)
651 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
652 if (port->mapbase == 0xffed0000)
653 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
654 if (port->mapbase == 0xffee0000)
655 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
656 if (port->mapbase == 0xffef0000)
657 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
660 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
661 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
662 defined(CONFIG_CPU_SUBTYPE_SH7263)
663 static inline int sci_rxd_in(struct uart_port *port)
665 if (port->mapbase == 0xfffe8000)
666 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
667 if (port->mapbase == 0xfffe8800)
668 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
669 if (port->mapbase == 0xfffe9000)
670 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
671 if (port->mapbase == 0xfffe9800)
672 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
675 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
676 static inline int sci_rxd_in(struct uart_port *port)
678 if (port->mapbase == 0xf8400000)
679 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
680 if (port->mapbase == 0xf8410000)
681 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
682 if (port->mapbase == 0xf8420000)
683 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
686 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
687 static inline int sci_rxd_in(struct uart_port *port)
689 if (port->mapbase == 0xffc30000)
690 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
691 if (port->mapbase == 0xffc40000)
692 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
693 if (port->mapbase == 0xffc50000)
694 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
695 if (port->mapbase == 0xffc60000)
696 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
702 * Values for the BitRate Register (SCBRR)
704 * The values are actually divisors for a frequency which can
705 * be internal to the SH3 (14.7456MHz) or derived from an external
706 * clock source. This driver assumes the internal clock is used;
707 * to support using an external clock source, config options or
708 * possibly command-line options would need to be added.
710 * Also, to support speeds below 2400 (why?) the lower 2 bits of
711 * the SCSMR register would also need to be set to non-zero values.
713 * -- Greg Banks 27Feb2000
715 * Answer: The SCBRR register is only eight bits, and the value in
716 * it gets larger with lower baud rates. At around 2400 (depending on
717 * the peripherial module clock) you run out of bits. However the
718 * lower two bits of SCSMR allow the module clock to be divided down,
719 * scaling the value which is needed in SCBRR.
721 * -- Stuart Menefy - 23 May 2000
723 * I meant, why would anyone bother with bitrates below 2400.
725 * -- Greg Banks - 7Jul2000
727 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
728 * tape reader as a console!
730 * -- Mitch Davis - 15 Jul 2000
733 #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
734 defined(CONFIG_CPU_SUBTYPE_SH7785)
735 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
736 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
737 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
738 defined(CONFIG_CPU_SUBTYPE_SH7721)
739 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
740 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
741 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
743 if (port->type == PORT_SCIF)
744 return (clk+16*bps)/(32*bps)-1;
746 return ((clk*2)+16*bps)/(16*bps)-1;
748 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
749 #elif defined(__H8300H__) || defined(__H8300S__)
750 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
751 #else /* Generic SH */
752 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)