drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/string.h>
  18 #include <linux/kernel.h>
  19 #include <linux/slab.h>
  20 #include <linux/delay.h>
  21 #include <linux/tty.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/8250_pci.h>
  24 #include <linux/bitops.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include "8250.h"
  30
  31 #undef SERIAL_DEBUG_PCI
  32
  33 /*
  34  * init function returns:
  35  *  > 0 - number of ports
  36  *  = 0 - use board->num_ports
  37  *  < 0 - error
  38  */
  39 struct pci_serial_quirk {
  40         u32     vendor;
  41         u32     device;
  42         u32     subvendor;
  43         u32     subdevice;
  44         int     (*init)(struct pci_dev *dev);
  45         int     (*setup)(struct serial_private *,
  46                          const struct pciserial_board *,
  47                          struct uart_port *, int);
  48         void    (*exit)(struct pci_dev *dev);
  49 };
  50
  51 #define PCI_NUM_BAR_RESOURCES   6
  52
  53 struct serial_private {
  54         struct pci_dev          *dev;
  55         unsigned int            nr;
  56         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  57         struct pci_serial_quirk *quirk;
  58         int                     line[0];
  59 };
  60
  61 static void moan_device(const char *str, struct pci_dev *dev)
  62 {
  63         printk(KERN_WARNING
  64                "%s: %s\n"
  65                "Please send the output of lspci -vv, this\n"
  66                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  67                "manufacturer and name of serial board or\n"
  68                "modem board to rmk+serial@arm.linux.org.uk.\n",
  69                pci_name(dev), str, dev->vendor, dev->device,
  70                dev->subsystem_vendor, dev->subsystem_device);
  71 }
  72
  73 static int
  74 setup_port(struct serial_private *priv, struct uart_port *port,
  75            int bar, int offset, int regshift)
  76 {
  77         struct pci_dev *dev = priv->dev;
  78         unsigned long base, len;
  79
  80         if (bar >= PCI_NUM_BAR_RESOURCES)
  81                 return -EINVAL;
  82
  83         base = pci_resource_start(dev, bar);
  84
  85         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  86                 len =  pci_resource_len(dev, bar);
  87
  88                 if (!priv->remapped_bar[bar])
  89                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  90                 if (!priv->remapped_bar[bar])
  91                         return -ENOMEM;
  92
  93                 port->iotype = UPIO_MEM;
  94                 port->iobase = 0;
  95                 port->mapbase = base + offset;
  96                 port->membase = priv->remapped_bar[bar] + offset;
  97                 port->regshift = regshift;
  98         } else {
  99                 port->iotype = UPIO_PORT;
 100                 port->iobase = base + offset;
 101                 port->mapbase = 0;
 102                 port->membase = NULL;
 103                 port->regshift = 0;
 104         }
 105         return 0;
 106 }
 107
 108 /*
 109  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 110  */
 111 static int addidata_apci7800_setup(struct serial_private *priv,
 112                                 const struct pciserial_board *board,
 113                                 struct uart_port *port, int idx)
 114 {
 115         unsigned int bar = 0, offset = board->first_offset;
 116         bar = FL_GET_BASE(board->flags);
 117
 118         if (idx < 2) {
 119                 offset += idx * board->uart_offset;
 120         } else if ((idx >= 2) && (idx < 4)) {
 121                 bar += 1;
 122                 offset += ((idx - 2) * board->uart_offset);
 123         } else if ((idx >= 4) && (idx < 6)) {
 124                 bar += 2;
 125                 offset += ((idx - 4) * board->uart_offset);
 126         } else if (idx >= 6) {
 127                 bar += 3;
 128                 offset += ((idx - 6) * board->uart_offset);
 129         }
 130
 131         return setup_port(priv, port, bar, offset, board->reg_shift);
 132 }
 133
 134 /*
 135  * AFAVLAB uses a different mixture of BARs and offsets
 136  * Not that ugly ;) -- HW
 137  */
 138 static int
 139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 140               struct uart_port *port, int idx)
 141 {
 142         unsigned int bar, offset = board->first_offset;
 143
 144         bar = FL_GET_BASE(board->flags);
 145         if (idx < 4)
 146                 bar += idx;
 147         else {
 148                 bar = 4;
 149                 offset += (idx - 4) * board->uart_offset;
 150         }
 151
 152         return setup_port(priv, port, bar, offset, board->reg_shift);
 153 }
 154
 155 /*
 156  * HP's Remote Management Console.  The Diva chip came in several
 157  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 158  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 159  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 160  * one Diva chip, but it has been expanded to 5 UARTs.
 161  */
 162 static int pci_hp_diva_init(struct pci_dev *dev)
 163 {
 164         int rc = 0;
 165
 166         switch (dev->subsystem_device) {
 167         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 168         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 169         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 170         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 171                 rc = 3;
 172                 break;
 173         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 174                 rc = 2;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 177                 rc = 4;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 180         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 181                 rc = 1;
 182                 break;
 183         }
 184
 185         return rc;
 186 }
 187
 188 /*
 189  * HP's Diva chip puts the 4th/5th serial port further out, and
 190  * some serial ports are supposed to be hidden on certain models.
 191  */
 192 static int
 193 pci_hp_diva_setup(struct serial_private *priv,
 194                 const struct pciserial_board *board,
 195                 struct uart_port *port, int idx)
 196 {
 197         unsigned int offset = board->first_offset;
 198         unsigned int bar = FL_GET_BASE(board->flags);
 199
 200         switch (priv->dev->subsystem_device) {
 201         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 202                 if (idx == 3)
 203                         idx++;
 204                 break;
 205         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 206                 if (idx > 0)
 207                         idx++;
 208                 if (idx > 2)
 209                         idx++;
 210                 break;
 211         }
 212         if (idx > 2)
 213                 offset = 0x18;
 214
 215         offset += idx * board->uart_offset;
 216
 217         return setup_port(priv, port, bar, offset, board->reg_shift);
 218 }
 219
 220 /*
 221  * Added for EKF Intel i960 serial boards
 222  */
 223 static int pci_inteli960ni_init(struct pci_dev *dev)
 224 {
 225         unsigned long oldval;
 226
 227         if (!(dev->subsystem_device & 0x1000))
 228                 return -ENODEV;
 229
 230         /* is firmware started? */
 231         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 232         if (oldval == 0x00001000L) { /* RESET value */
 233                 printk(KERN_DEBUG "Local i960 firmware missing");
 234                 return -ENODEV;
 235         }
 236         return 0;
 237 }
 238
 239 /*
 240  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 241  * that the card interrupt be explicitly enabled or disabled.  This
 242  * seems to be mainly needed on card using the PLX which also use I/O
 243  * mapped memory.
 244  */
 245 static int pci_plx9050_init(struct pci_dev *dev)
 246 {
 247         u8 irq_config;
 248         void __iomem *p;
 249
 250         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 251                 moan_device("no memory in bar 0", dev);
 252                 return 0;
 253         }
 254
 255         irq_config = 0x41;
 256         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 257             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 258                 irq_config = 0x43;
 259
 260         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 261             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 262                 /*
 263                  * As the megawolf cards have the int pins active
 264                  * high, and have 2 UART chips, both ints must be
 265                  * enabled on the 9050. Also, the UARTS are set in
 266                  * 16450 mode by default, so we have to enable the
 267                  * 16C950 'enhanced' mode so that we can use the
 268                  * deep FIFOs
 269                  */
 270                 irq_config = 0x5b;
 271         /*
 272          * enable/disable interrupts
 273          */
 274         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 275         if (p == NULL)
 276                 return -ENOMEM;
 277         writel(irq_config, p + 0x4c);
 278
 279         /*
 280          * Read the register back to ensure that it took effect.
 281          */
 282         readl(p + 0x4c);
 283         iounmap(p);
 284
 285         return 0;
 286 }
 287
 288 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 289 {
 290         u8 __iomem *p;
 291
 292         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 293                 return;
 294
 295         /*
 296          * disable interrupts
 297          */
 298         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 299         if (p != NULL) {
 300                 writel(0, p + 0x4c);
 301
 302                 /*
 303                  * Read the register back to ensure that it took effect.
 304                  */
 305                 readl(p + 0x4c);
 306                 iounmap(p);
 307         }
 308 }
 309
 310 #define NI8420_INT_ENABLE_REG   0x38
 311 #define NI8420_INT_ENABLE_BIT   0x2000
 312
 313 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 314 {
 315         void __iomem *p;
 316         unsigned long base, len;
 317         unsigned int bar = 0;
 318
 319         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 320                 moan_device("no memory in bar", dev);
 321                 return;
 322         }
 323
 324         base = pci_resource_start(dev, bar);
 325         len =  pci_resource_len(dev, bar);
 326         p = ioremap_nocache(base, len);
 327         if (p == NULL)
 328                 return;
 329
 330         /* Disable the CPU Interrupt */
 331         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 332                p + NI8420_INT_ENABLE_REG);
 333         iounmap(p);
 334 }
 335
 336
 337 /* MITE registers */
 338 #define MITE_IOWBSR1    0xc4
 339 #define MITE_IOWCR1     0xf4
 340 #define MITE_LCIMR1     0x08
 341 #define MITE_LCIMR2     0x10
 342
 343 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 344
 345 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 346 {
 347         void __iomem *p;
 348         unsigned long base, len;
 349         unsigned int bar = 0;
 350
 351         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 352                 moan_device("no memory in bar", dev);
 353                 return;
 354         }
 355
 356         base = pci_resource_start(dev, bar);
 357         len =  pci_resource_len(dev, bar);
 358         p = ioremap_nocache(base, len);
 359         if (p == NULL)
 360                 return;
 361
 362         /* Disable the CPU Interrupt */
 363         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 364         iounmap(p);
 365 }
 366
 367 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 368 static int
 369 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 370                 struct uart_port *port, int idx)
 371 {
 372         unsigned int bar, offset = board->first_offset;
 373
 374         bar = 0;
 375
 376         if (idx < 4) {
 377                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 378                 offset += idx * board->uart_offset;
 379         } else if (idx < 8) {
 380                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 381                 offset += idx * board->uart_offset + 0xC00;
 382         } else /* we have only 8 ports on PMC-OCTALPRO */
 383                 return 1;
 384
 385         return setup_port(priv, port, bar, offset, board->reg_shift);
 386 }
 387
 388 /*
 389 * This does initialization for PMC OCTALPRO cards:
 390 * maps the device memory, resets the UARTs (needed, bc
 391 * if the module is removed and inserted again, the card
 392 * is in the sleep mode) and enables global interrupt.
 393 */
 394
 395 /* global control register offset for SBS PMC-OctalPro */
 396 #define OCT_REG_CR_OFF          0x500
 397
 398 static int sbs_init(struct pci_dev *dev)
 399 {
 400         u8 __iomem *p;
 401
 402         p = pci_ioremap_bar(dev, 0);
 403
 404         if (p == NULL)
 405                 return -ENOMEM;
 406         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 407         writeb(0x10, p + OCT_REG_CR_OFF);
 408         udelay(50);
 409         writeb(0x0, p + OCT_REG_CR_OFF);
 410
 411         /* Set bit-2 (INTENABLE) of Control Register */
 412         writeb(0x4, p + OCT_REG_CR_OFF);
 413         iounmap(p);
 414
 415         return 0;
 416 }
 417
 418 /*
 419  * Disables the global interrupt of PMC-OctalPro
 420  */
 421
 422 static void __devexit sbs_exit(struct pci_dev *dev)
 423 {
 424         u8 __iomem *p;
 425
 426         p = pci_ioremap_bar(dev, 0);
 427         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 428         if (p != NULL)
 429                 writeb(0, p + OCT_REG_CR_OFF);
 430         iounmap(p);
 431 }
 432
 433 /*
 434  * SIIG serial cards have an PCI interface chip which also controls
 435  * the UART clocking frequency. Each UART can be clocked independently
 436  * (except cards equiped with 4 UARTs) and initial clocking settings
 437  * are stored in the EEPROM chip. It can cause problems because this
 438  * version of serial driver doesn't support differently clocked UART's
 439  * on single PCI card. To prevent this, initialization functions set
 440  * high frequency clocking for all UART's on given card. It is safe (I
 441  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 442  * with other OSes (like M$ DOS).
 443  *
 444  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 445  *
 446  * There is two family of SIIG serial cards with different PCI
 447  * interface chip and different configuration methods:
 448  *     - 10x cards have control registers in IO and/or memory space;
 449  *     - 20x cards have control registers in standard PCI configuration space.
 450  *
 451  * Note: all 10x cards have PCI device ids 0x10..
 452  *       all 20x cards have PCI device ids 0x20..
 453  *
 454  * There are also Quartet Serial cards which use Oxford Semiconductor
 455  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 456  *
 457  * Note: some SIIG cards are probed by the parport_serial object.
 458  */
 459
 460 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 461 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 462
 463 static int pci_siig10x_init(struct pci_dev *dev)
 464 {
 465         u16 data;
 466         void __iomem *p;
 467
 468         switch (dev->device & 0xfff8) {
 469         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 470                 data = 0xffdf;
 471                 break;
 472         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 473                 data = 0xf7ff;
 474                 break;
 475         default:                        /* 1S1P, 4S */
 476                 data = 0xfffb;
 477                 break;
 478         }
 479
 480         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 481         if (p == NULL)
 482                 return -ENOMEM;
 483
 484         writew(readw(p + 0x28) & data, p + 0x28);
 485         readw(p + 0x28);
 486         iounmap(p);
 487         return 0;
 488 }
 489
 490 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 491 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 492
 493 static int pci_siig20x_init(struct pci_dev *dev)
 494 {
 495         u8 data;
 496
 497         /* Change clock frequency for the first UART. */
 498         pci_read_config_byte(dev, 0x6f, &data);
 499         pci_write_config_byte(dev, 0x6f, data & 0xef);
 500
 501         /* If this card has 2 UART, we have to do the same with second UART. */
 502         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 503             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 504                 pci_read_config_byte(dev, 0x73, &data);
 505                 pci_write_config_byte(dev, 0x73, data & 0xef);
 506         }
 507         return 0;
 508 }
 509
 510 static int pci_siig_init(struct pci_dev *dev)
 511 {
 512         unsigned int type = dev->device & 0xff00;
 513
 514         if (type == 0x1000)
 515                 return pci_siig10x_init(dev);
 516         else if (type == 0x2000)
 517                 return pci_siig20x_init(dev);
 518
 519         moan_device("Unknown SIIG card", dev);
 520         return -ENODEV;
 521 }
 522
 523 static int pci_siig_setup(struct serial_private *priv,
 524                           const struct pciserial_board *board,
 525                           struct uart_port *port, int idx)
 526 {
 527         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 528
 529         if (idx > 3) {
 530                 bar = 4;
 531                 offset = (idx - 4) * 8;
 532         }
 533
 534         return setup_port(priv, port, bar, offset, 0);
 535 }
 536
 537 /*
 538  * Timedia has an explosion of boards, and to avoid the PCI table from
 539  * growing *huge*, we use this function to collapse some 70 entries
 540  * in the PCI table into one, for sanity's and compactness's sake.
 541  */
 542 static const unsigned short timedia_single_port[] = {
 543         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 544 };
 545
 546 static const unsigned short timedia_dual_port[] = {
 547         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 548         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 549         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 550         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 551         0xD079, 0
 552 };
 553
 554 static const unsigned short timedia_quad_port[] = {
 555         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 556         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 557         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 558         0xB157, 0
 559 };
 560
 561 static const unsigned short timedia_eight_port[] = {
 562         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 563         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 564 };
 565
 566 static const struct timedia_struct {
 567         int num;
 568         const unsigned short *ids;
 569 } timedia_data[] = {
 570         { 1, timedia_single_port },
 571         { 2, timedia_dual_port },
 572         { 4, timedia_quad_port },
 573         { 8, timedia_eight_port }
 574 };
 575
 576 static int pci_timedia_init(struct pci_dev *dev)
 577 {
 578         const unsigned short *ids;
 579         int i, j;
 580
 581         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 582                 ids = timedia_data[i].ids;
 583                 for (j = 0; ids[j]; j++)
 584                         if (dev->subsystem_device == ids[j])
 585                                 return timedia_data[i].num;
 586         }
 587         return 0;
 588 }
 589
 590 /*
 591  * Timedia/SUNIX uses a mixture of BARs and offsets
 592  * Ugh, this is ugly as all hell --- TYT
 593  */
 594 static int
 595 pci_timedia_setup(struct serial_private *priv,
 596                   const struct pciserial_board *board,
 597                   struct uart_port *port, int idx)
 598 {
 599         unsigned int bar = 0, offset = board->first_offset;
 600
 601         switch (idx) {
 602         case 0:
 603                 bar = 0;
 604                 break;
 605         case 1:
 606                 offset = board->uart_offset;
 607                 bar = 0;
 608                 break;
 609         case 2:
 610                 bar = 1;
 611                 break;
 612         case 3:
 613                 offset = board->uart_offset;
 614                 /* FALLTHROUGH */
 615         case 4: /* BAR 2 */
 616         case 5: /* BAR 3 */
 617         case 6: /* BAR 4 */
 618         case 7: /* BAR 5 */
 619                 bar = idx - 2;
 620         }
 621
 622         return setup_port(priv, port, bar, offset, board->reg_shift);
 623 }
 624
 625 /*
 626  * Some Titan cards are also a little weird
 627  */
 628 static int
 629 titan_400l_800l_setup(struct serial_private *priv,
 630                       const struct pciserial_board *board,
 631                       struct uart_port *port, int idx)
 632 {
 633         unsigned int bar, offset = board->first_offset;
 634
 635         switch (idx) {
 636         case 0:
 637                 bar = 1;
 638                 break;
 639         case 1:
 640                 bar = 2;
 641                 break;
 642         default:
 643                 bar = 4;
 644                 offset = (idx - 2) * board->uart_offset;
 645         }
 646
 647         return setup_port(priv, port, bar, offset, board->reg_shift);
 648 }
 649
 650 static int pci_xircom_init(struct pci_dev *dev)
 651 {
 652         msleep(100);
 653         return 0;
 654 }
 655
 656 static int pci_ni8420_init(struct pci_dev *dev)
 657 {
 658         void __iomem *p;
 659         unsigned long base, len;
 660         unsigned int bar = 0;
 661
 662         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 663                 moan_device("no memory in bar", dev);
 664                 return 0;
 665         }
 666
 667         base = pci_resource_start(dev, bar);
 668         len =  pci_resource_len(dev, bar);
 669         p = ioremap_nocache(base, len);
 670         if (p == NULL)
 671                 return -ENOMEM;
 672
 673         /* Enable CPU Interrupt */
 674         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 675                p + NI8420_INT_ENABLE_REG);
 676
 677         iounmap(p);
 678         return 0;
 679 }
 680
 681 #define MITE_IOWBSR1_WSIZE      0xa
 682 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 683 #define MITE_IOWBSR1_WENAB      (1 << 7)
 684 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 685 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 686 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 687
 688 static int pci_ni8430_init(struct pci_dev *dev)
 689 {
 690         void __iomem *p;
 691         unsigned long base, len;
 692         u32 device_window;
 693         unsigned int bar = 0;
 694
 695         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 696                 moan_device("no memory in bar", dev);
 697                 return 0;
 698         }
 699
 700         base = pci_resource_start(dev, bar);
 701         len =  pci_resource_len(dev, bar);
 702         p = ioremap_nocache(base, len);
 703         if (p == NULL)
 704                 return -ENOMEM;
 705
 706         /* Set device window address and size in BAR0 */
 707         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 708                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 709         writel(device_window, p + MITE_IOWBSR1);
 710
 711         /* Set window access to go to RAMSEL IO address space */
 712         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 713                p + MITE_IOWCR1);
 714
 715         /* Enable IO Bus Interrupt 0 */
 716         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 717
 718         /* Enable CPU Interrupt */
 719         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 720
 721         iounmap(p);
 722         return 0;
 723 }
 724
 725 /* UART Port Control Register */
 726 #define NI8430_PORTCON  0x0f
 727 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 728
 729 static int
 730 pci_ni8430_setup(struct serial_private *priv,
 731                  const struct pciserial_board *board,
 732                  struct uart_port *port, int idx)
 733 {
 734         void __iomem *p;
 735         unsigned long base, len;
 736         unsigned int bar, offset = board->first_offset;
 737
 738         if (idx >= board->num_ports)
 739                 return 1;
 740
 741         bar = FL_GET_BASE(board->flags);
 742         offset += idx * board->uart_offset;
 743
 744         base = pci_resource_start(priv->dev, bar);
 745         len =  pci_resource_len(priv->dev, bar);
 746         p = ioremap_nocache(base, len);
 747
 748         /* enable the transciever */
 749         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 750                p + offset + NI8430_PORTCON);
 751
 752         iounmap(p);
 753
 754         return setup_port(priv, port, bar, offset, board->reg_shift);
 755 }
 756
 757
 758 static int pci_netmos_init(struct pci_dev *dev)
 759 {
 760         /* subdevice 0x00PS means <P> parallel, <S> serial */
 761         unsigned int num_serial = dev->subsystem_device & 0xf;
 762
 763         if (dev->device == PCI_DEVICE_ID_NETMOS_9901)
 764                 return 0;
 765         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 766                         dev->subsystem_device == 0x0299)
 767                 return 0;
 768
 769         if (num_serial == 0)
 770                 return -ENODEV;
 771         return num_serial;
 772 }
 773
 774 /*
 775  * These chips are available with optionally one parallel port and up to
 776  * two serial ports. Unfortunately they all have the same product id.
 777  *
 778  * Basic configuration is done over a region of 32 I/O ports. The base
 779  * ioport is called INTA or INTC, depending on docs/other drivers.
 780  *
 781  * The region of the 32 I/O ports is configured in POSIO0R...
 782  */
 783
 784 /* registers */
 785 #define ITE_887x_MISCR          0x9c
 786 #define ITE_887x_INTCBAR        0x78
 787 #define ITE_887x_UARTBAR        0x7c
 788 #define ITE_887x_PS0BAR         0x10
 789 #define ITE_887x_POSIO0         0x60
 790
 791 /* I/O space size */
 792 #define ITE_887x_IOSIZE         32
 793 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 794 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 795 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 796 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 797 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 798 #define ITE_887x_POSIO_SPEED            (3 << 29)
 799 /* enable IO_Space bit */
 800 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 801
 802 static int pci_ite887x_init(struct pci_dev *dev)
 803 {
 804         /* inta_addr are the configuration addresses of the ITE */
 805         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 806                                                         0x200, 0x280, 0 };
 807         int ret, i, type;
 808         struct resource *iobase = NULL;
 809         u32 miscr, uartbar, ioport;
 810
 811         /* search for the base-ioport */
 812         i = 0;
 813         while (inta_addr[i] && iobase == NULL) {
 814                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 815                                                                 "ite887x");
 816                 if (iobase != NULL) {
 817                         /* write POSIO0R - speed | size | ioport */
 818                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 819                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 820                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 821                         /* write INTCBAR - ioport */
 822                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 823                                                                 inta_addr[i]);
 824                         ret = inb(inta_addr[i]);
 825                         if (ret != 0xff) {
 826                                 /* ioport connected */
 827                                 break;
 828                         }
 829                         release_region(iobase->start, ITE_887x_IOSIZE);
 830                         iobase = NULL;
 831                 }
 832                 i++;
 833         }
 834
 835         if (!inta_addr[i]) {
 836                 printk(KERN_ERR "ite887x: could not find iobase\n");
 837                 return -ENODEV;
 838         }
 839
 840         /* start of undocumented type checking (see parport_pc.c) */
 841         type = inb(iobase->start + 0x18) & 0x0f;
 842
 843         switch (type) {
 844         case 0x2:       /* ITE8871 (1P) */
 845         case 0xa:       /* ITE8875 (1P) */
 846                 ret = 0;
 847                 break;
 848         case 0xe:       /* ITE8872 (2S1P) */
 849                 ret = 2;
 850                 break;
 851         case 0x6:       /* ITE8873 (1S) */
 852                 ret = 1;
 853                 break;
 854         case 0x8:       /* ITE8874 (2S) */
 855                 ret = 2;
 856                 break;
 857         default:
 858                 moan_device("Unknown ITE887x", dev);
 859                 ret = -ENODEV;
 860         }
 861
 862         /* configure all serial ports */
 863         for (i = 0; i < ret; i++) {
 864                 /* read the I/O port from the device */
 865                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 866                                                                 &ioport);
 867                 ioport &= 0x0000FF00;   /* the actual base address */
 868                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 869                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 870                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 871
 872                 /* write the ioport to the UARTBAR */
 873                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 874                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 875                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 876                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 877
 878                 /* get current config */
 879                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 880                 /* disable interrupts (UARTx_Routing[3:0]) */
 881                 miscr &= ~(0xf << (12 - 4 * i));
 882                 /* activate the UART (UARTx_En) */
 883                 miscr |= 1 << (23 - i);
 884                 /* write new config with activated UART */
 885                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 886         }
 887
 888         if (ret <= 0) {
 889                 /* the device has no UARTs if we get here */
 890                 release_region(iobase->start, ITE_887x_IOSIZE);
 891         }
 892
 893         return ret;
 894 }
 895
 896 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 897 {
 898         u32 ioport;
 899         /* the ioport is bit 0-15 in POSIO0R */
 900         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 901         ioport &= 0xffff;
 902         release_region(ioport, ITE_887x_IOSIZE);
 903 }
 904
 905 /*
 906  * Oxford Semiconductor Inc.
 907  * Check that device is part of the Tornado range of devices, then determine
 908  * the number of ports available on the device.
 909  */
 910 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
 911 {
 912         u8 __iomem *p;
 913         unsigned long deviceID;
 914         unsigned int  number_uarts = 0;
 915
 916         /* OxSemi Tornado devices are all 0xCxxx */
 917         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
 918             (dev->device & 0xF000) != 0xC000)
 919                 return 0;
 920
 921         p = pci_iomap(dev, 0, 5);
 922         if (p == NULL)
 923                 return -ENOMEM;
 924
 925         deviceID = ioread32(p);
 926         /* Tornado device */
 927         if (deviceID == 0x07000200) {
 928                 number_uarts = ioread8(p + 4);
 929                 printk(KERN_DEBUG
 930                         "%d ports detected on Oxford PCI Express device\n",
 931                                                                 number_uarts);
 932         }
 933         pci_iounmap(dev, p);
 934         return number_uarts;
 935 }
 936
 937 static int
 938 pci_default_setup(struct serial_private *priv,
 939                   const struct pciserial_board *board,
 940                   struct uart_port *port, int idx)
 941 {
 942         unsigned int bar, offset = board->first_offset, maxnr;
 943
 944         bar = FL_GET_BASE(board->flags);
 945         if (board->flags & FL_BASE_BARS)
 946                 bar += idx;
 947         else
 948                 offset += idx * board->uart_offset;
 949
 950         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 951                 (board->reg_shift + 3);
 952
 953         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 954                 return 1;
 955
 956         return setup_port(priv, port, bar, offset, board->reg_shift);
 957 }
 958
 959 static int skip_tx_en_setup(struct serial_private *priv,
 960                         const struct pciserial_board *board,
 961                         struct uart_port *port, int idx)
 962 {
 963         port->flags |= UPF_NO_TXEN_TEST;
 964         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
 965                           "[%04x:%04x] subsystem [%04x:%04x]\n",
 966                           priv->dev->vendor,
 967                           priv->dev->device,
 968                           priv->dev->subsystem_vendor,
 969                           priv->dev->subsystem_device);
 970
 971         return pci_default_setup(priv, board, port, idx);
 972 }
 973
 974 /* This should be in linux/pci_ids.h */
 975 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 976 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 977 #define PCI_DEVICE_ID_OCTPRO            0x0001
 978 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 979 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 980 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 981 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 982 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
 983 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
 984
 985 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
 986 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
 987
 988 /*
 989  * Master list of serial port init/setup/exit quirks.
 990  * This does not describe the general nature of the port.
 991  * (ie, baud base, number and location of ports, etc)
 992  *
 993  * This list is ordered alphabetically by vendor then device.
 994  * Specific entries must come before more generic entries.
 995  */
 996 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
 997         /*
 998         * ADDI-DATA GmbH communication cards <info@addi-data.com>
 999         */
1000         {
1001                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1002                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1003                 .subvendor      = PCI_ANY_ID,
1004                 .subdevice      = PCI_ANY_ID,
1005                 .setup          = addidata_apci7800_setup,
1006         },
1007         /*
1008          * AFAVLAB cards - these may be called via parport_serial
1009          *  It is not clear whether this applies to all products.
1010          */
1011         {
1012                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1013                 .device         = PCI_ANY_ID,
1014                 .subvendor      = PCI_ANY_ID,
1015                 .subdevice      = PCI_ANY_ID,
1016                 .setup          = afavlab_setup,
1017         },
1018         /*
1019          * HP Diva
1020          */
1021         {
1022                 .vendor         = PCI_VENDOR_ID_HP,
1023                 .device         = PCI_DEVICE_ID_HP_DIVA,
1024                 .subvendor      = PCI_ANY_ID,
1025                 .subdevice      = PCI_ANY_ID,
1026                 .init           = pci_hp_diva_init,
1027                 .setup          = pci_hp_diva_setup,
1028         },
1029         /*
1030          * Intel
1031          */
1032         {
1033                 .vendor         = PCI_VENDOR_ID_INTEL,
1034                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1035                 .subvendor      = 0xe4bf,
1036                 .subdevice      = PCI_ANY_ID,
1037                 .init           = pci_inteli960ni_init,
1038                 .setup          = pci_default_setup,
1039         },
1040         {
1041                 .vendor         = PCI_VENDOR_ID_INTEL,
1042                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1043                 .subvendor      = PCI_ANY_ID,
1044                 .subdevice      = PCI_ANY_ID,
1045                 .setup          = skip_tx_en_setup,
1046         },
1047         {
1048                 .vendor         = PCI_VENDOR_ID_INTEL,
1049                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1050                 .subvendor      = PCI_ANY_ID,
1051                 .subdevice      = PCI_ANY_ID,
1052                 .setup          = skip_tx_en_setup,
1053         },
1054         {
1055                 .vendor         = PCI_VENDOR_ID_INTEL,
1056                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1057                 .subvendor      = PCI_ANY_ID,
1058                 .subdevice      = PCI_ANY_ID,
1059                 .setup          = skip_tx_en_setup,
1060         },
1061         /*
1062          * ITE
1063          */
1064         {
1065                 .vendor         = PCI_VENDOR_ID_ITE,
1066                 .device         = PCI_DEVICE_ID_ITE_8872,
1067                 .subvendor      = PCI_ANY_ID,
1068                 .subdevice      = PCI_ANY_ID,
1069                 .init           = pci_ite887x_init,
1070                 .setup          = pci_default_setup,
1071                 .exit           = __devexit_p(pci_ite887x_exit),
1072         },
1073         /*
1074          * National Instruments
1075          */
1076         {
1077                 .vendor         = PCI_VENDOR_ID_NI,
1078                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1079                 .subvendor      = PCI_ANY_ID,
1080                 .subdevice      = PCI_ANY_ID,
1081                 .init           = pci_ni8420_init,
1082                 .setup          = pci_default_setup,
1083                 .exit           = __devexit_p(pci_ni8420_exit),
1084         },
1085         {
1086                 .vendor         = PCI_VENDOR_ID_NI,
1087                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1088                 .subvendor      = PCI_ANY_ID,
1089                 .subdevice      = PCI_ANY_ID,
1090                 .init           = pci_ni8420_init,
1091                 .setup          = pci_default_setup,
1092                 .exit           = __devexit_p(pci_ni8420_exit),
1093         },
1094         {
1095                 .vendor         = PCI_VENDOR_ID_NI,
1096                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1097                 .subvendor      = PCI_ANY_ID,
1098                 .subdevice      = PCI_ANY_ID,
1099                 .init           = pci_ni8420_init,
1100                 .setup          = pci_default_setup,
1101                 .exit           = __devexit_p(pci_ni8420_exit),
1102         },
1103         {
1104                 .vendor         = PCI_VENDOR_ID_NI,
1105                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1106                 .subvendor      = PCI_ANY_ID,
1107                 .subdevice      = PCI_ANY_ID,
1108                 .init           = pci_ni8420_init,
1109                 .setup          = pci_default_setup,
1110                 .exit           = __devexit_p(pci_ni8420_exit),
1111         },
1112         {
1113                 .vendor         = PCI_VENDOR_ID_NI,
1114                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1115                 .subvendor      = PCI_ANY_ID,
1116                 .subdevice      = PCI_ANY_ID,
1117                 .init           = pci_ni8420_init,
1118                 .setup          = pci_default_setup,
1119                 .exit           = __devexit_p(pci_ni8420_exit),
1120         },
1121         {
1122                 .vendor         = PCI_VENDOR_ID_NI,
1123                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1124                 .subvendor      = PCI_ANY_ID,
1125                 .subdevice      = PCI_ANY_ID,
1126                 .init           = pci_ni8420_init,
1127                 .setup          = pci_default_setup,
1128                 .exit           = __devexit_p(pci_ni8420_exit),
1129         },
1130         {
1131                 .vendor         = PCI_VENDOR_ID_NI,
1132                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1133                 .subvendor      = PCI_ANY_ID,
1134                 .subdevice      = PCI_ANY_ID,
1135                 .init           = pci_ni8420_init,
1136                 .setup          = pci_default_setup,
1137                 .exit           = __devexit_p(pci_ni8420_exit),
1138         },
1139         {
1140                 .vendor         = PCI_VENDOR_ID_NI,
1141                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1142                 .subvendor      = PCI_ANY_ID,
1143                 .subdevice      = PCI_ANY_ID,
1144                 .init           = pci_ni8420_init,
1145                 .setup          = pci_default_setup,
1146                 .exit           = __devexit_p(pci_ni8420_exit),
1147         },
1148         {
1149                 .vendor         = PCI_VENDOR_ID_NI,
1150                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1151                 .subvendor      = PCI_ANY_ID,
1152                 .subdevice      = PCI_ANY_ID,
1153                 .init           = pci_ni8420_init,
1154                 .setup          = pci_default_setup,
1155                 .exit           = __devexit_p(pci_ni8420_exit),
1156         },
1157         {
1158                 .vendor         = PCI_VENDOR_ID_NI,
1159                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1160                 .subvendor      = PCI_ANY_ID,
1161                 .subdevice      = PCI_ANY_ID,
1162                 .init           = pci_ni8420_init,
1163                 .setup          = pci_default_setup,
1164                 .exit           = __devexit_p(pci_ni8420_exit),
1165         },
1166         {
1167                 .vendor         = PCI_VENDOR_ID_NI,
1168                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1169                 .subvendor      = PCI_ANY_ID,
1170                 .subdevice      = PCI_ANY_ID,
1171                 .init           = pci_ni8420_init,
1172                 .setup          = pci_default_setup,
1173                 .exit           = __devexit_p(pci_ni8420_exit),
1174         },
1175         {
1176                 .vendor         = PCI_VENDOR_ID_NI,
1177                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1178                 .subvendor      = PCI_ANY_ID,
1179                 .subdevice      = PCI_ANY_ID,
1180                 .init           = pci_ni8420_init,
1181                 .setup          = pci_default_setup,
1182                 .exit           = __devexit_p(pci_ni8420_exit),
1183         },
1184         {
1185                 .vendor         = PCI_VENDOR_ID_NI,
1186                 .device         = PCI_ANY_ID,
1187                 .subvendor      = PCI_ANY_ID,
1188                 .subdevice      = PCI_ANY_ID,
1189                 .init           = pci_ni8430_init,
1190                 .setup          = pci_ni8430_setup,
1191                 .exit           = __devexit_p(pci_ni8430_exit),
1192         },
1193         /*
1194          * Panacom
1195          */
1196         {
1197                 .vendor         = PCI_VENDOR_ID_PANACOM,
1198                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1199                 .subvendor      = PCI_ANY_ID,
1200                 .subdevice      = PCI_ANY_ID,
1201                 .init           = pci_plx9050_init,
1202                 .setup          = pci_default_setup,
1203                 .exit           = __devexit_p(pci_plx9050_exit),
1204         },
1205         {
1206                 .vendor         = PCI_VENDOR_ID_PANACOM,
1207                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1208                 .subvendor      = PCI_ANY_ID,
1209                 .subdevice      = PCI_ANY_ID,
1210                 .init           = pci_plx9050_init,
1211                 .setup          = pci_default_setup,
1212                 .exit           = __devexit_p(pci_plx9050_exit),
1213         },
1214         /*
1215          * PLX
1216          */
1217         {
1218                 .vendor         = PCI_VENDOR_ID_PLX,
1219                 .device         = PCI_DEVICE_ID_PLX_9030,
1220                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1221                 .subdevice      = PCI_ANY_ID,
1222                 .setup          = pci_default_setup,
1223         },
1224         {
1225                 .vendor         = PCI_VENDOR_ID_PLX,
1226                 .device         = PCI_DEVICE_ID_PLX_9050,
1227                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1228                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1229                 .init           = pci_plx9050_init,
1230                 .setup          = pci_default_setup,
1231                 .exit           = __devexit_p(pci_plx9050_exit),
1232         },
1233         {
1234                 .vendor         = PCI_VENDOR_ID_PLX,
1235                 .device         = PCI_DEVICE_ID_PLX_9050,
1236                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1237                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1238                 .init           = pci_plx9050_init,
1239                 .setup          = pci_default_setup,
1240                 .exit           = __devexit_p(pci_plx9050_exit),
1241         },
1242         {
1243                 .vendor         = PCI_VENDOR_ID_PLX,
1244                 .device         = PCI_DEVICE_ID_PLX_9050,
1245                 .subvendor      = PCI_VENDOR_ID_PLX,
1246                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1247                 .init           = pci_plx9050_init,
1248                 .setup          = pci_default_setup,
1249                 .exit           = __devexit_p(pci_plx9050_exit),
1250         },
1251         {
1252                 .vendor         = PCI_VENDOR_ID_PLX,
1253                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1254                 .subvendor      = PCI_VENDOR_ID_PLX,
1255                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1256                 .init           = pci_plx9050_init,
1257                 .setup          = pci_default_setup,
1258                 .exit           = __devexit_p(pci_plx9050_exit),
1259         },
1260         /*
1261          * SBS Technologies, Inc., PMC-OCTALPRO 232
1262          */
1263         {
1264                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1265                 .device         = PCI_DEVICE_ID_OCTPRO,
1266                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1267                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1268                 .init           = sbs_init,
1269                 .setup          = sbs_setup,
1270                 .exit           = __devexit_p(sbs_exit),
1271         },
1272         /*
1273          * SBS Technologies, Inc., PMC-OCTALPRO 422
1274          */
1275         {
1276                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1277                 .device         = PCI_DEVICE_ID_OCTPRO,
1278                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1279                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1280                 .init           = sbs_init,
1281                 .setup          = sbs_setup,
1282                 .exit           = __devexit_p(sbs_exit),
1283         },
1284         /*
1285          * SBS Technologies, Inc., P-Octal 232
1286          */
1287         {
1288                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1289                 .device         = PCI_DEVICE_ID_OCTPRO,
1290                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1291                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1292                 .init           = sbs_init,
1293                 .setup          = sbs_setup,
1294                 .exit           = __devexit_p(sbs_exit),
1295         },
1296         /*
1297          * SBS Technologies, Inc., P-Octal 422
1298          */
1299         {
1300                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1301                 .device         = PCI_DEVICE_ID_OCTPRO,
1302                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1303                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1304                 .init           = sbs_init,
1305                 .setup          = sbs_setup,
1306                 .exit           = __devexit_p(sbs_exit),
1307         },
1308         /*
1309          * SIIG cards - these may be called via parport_serial
1310          */
1311         {
1312                 .vendor         = PCI_VENDOR_ID_SIIG,
1313                 .device         = PCI_ANY_ID,
1314                 .subvendor      = PCI_ANY_ID,
1315                 .subdevice      = PCI_ANY_ID,
1316                 .init           = pci_siig_init,
1317                 .setup          = pci_siig_setup,
1318         },
1319         /*
1320          * Titan cards
1321          */
1322         {
1323                 .vendor         = PCI_VENDOR_ID_TITAN,
1324                 .device         = PCI_DEVICE_ID_TITAN_400L,
1325                 .subvendor      = PCI_ANY_ID,
1326                 .subdevice      = PCI_ANY_ID,
1327                 .setup          = titan_400l_800l_setup,
1328         },
1329         {
1330                 .vendor         = PCI_VENDOR_ID_TITAN,
1331                 .device         = PCI_DEVICE_ID_TITAN_800L,
1332                 .subvendor      = PCI_ANY_ID,
1333                 .subdevice      = PCI_ANY_ID,
1334                 .setup          = titan_400l_800l_setup,
1335         },
1336         /*
1337          * Timedia cards
1338          */
1339         {
1340                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1341                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1342                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1343                 .subdevice      = PCI_ANY_ID,
1344                 .init           = pci_timedia_init,
1345                 .setup          = pci_timedia_setup,
1346         },
1347         {
1348                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1349                 .device         = PCI_ANY_ID,
1350                 .subvendor      = PCI_ANY_ID,
1351                 .subdevice      = PCI_ANY_ID,
1352                 .setup          = pci_timedia_setup,
1353         },
1354         /*
1355          * Xircom cards
1356          */
1357         {
1358                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1359                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1360                 .subvendor      = PCI_ANY_ID,
1361                 .subdevice      = PCI_ANY_ID,
1362                 .init           = pci_xircom_init,
1363                 .setup          = pci_default_setup,
1364         },
1365         /*
1366          * Netmos cards - these may be called via parport_serial
1367          */
1368         {
1369                 .vendor         = PCI_VENDOR_ID_NETMOS,
1370                 .device         = PCI_ANY_ID,
1371                 .subvendor      = PCI_ANY_ID,
1372                 .subdevice      = PCI_ANY_ID,
1373                 .init           = pci_netmos_init,
1374                 .setup          = pci_default_setup,
1375         },
1376         /*
1377          * For Oxford Semiconductor and Mainpine
1378          */
1379         {
1380                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1381                 .device         = PCI_ANY_ID,
1382                 .subvendor      = PCI_ANY_ID,
1383                 .subdevice      = PCI_ANY_ID,
1384                 .init           = pci_oxsemi_tornado_init,
1385                 .setup          = pci_default_setup,
1386         },
1387         {
1388                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1389                 .device         = PCI_ANY_ID,
1390                 .subvendor      = PCI_ANY_ID,
1391                 .subdevice      = PCI_ANY_ID,
1392                 .init           = pci_oxsemi_tornado_init,
1393                 .setup          = pci_default_setup,
1394         },
1395         /*
1396          * Default "match everything" terminator entry
1397          */
1398         {
1399                 .vendor         = PCI_ANY_ID,
1400                 .device         = PCI_ANY_ID,
1401                 .subvendor      = PCI_ANY_ID,
1402                 .subdevice      = PCI_ANY_ID,
1403                 .setup          = pci_default_setup,
1404         }
1405 };
1406
1407 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1408 {
1409         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1410 }
1411
1412 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1413 {
1414         struct pci_serial_quirk *quirk;
1415
1416         for (quirk = pci_serial_quirks; ; quirk++)
1417                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1418                     quirk_id_matches(quirk->device, dev->device) &&
1419                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1420                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1421                         break;
1422         return quirk;
1423 }
1424
1425 static inline int get_pci_irq(struct pci_dev *dev,
1426                                 const struct pciserial_board *board)
1427 {
1428         if (board->flags & FL_NOIRQ)
1429                 return 0;
1430         else
1431                 return dev->irq;
1432 }
1433
1434 /*
1435  * This is the configuration table for all of the PCI serial boards
1436  * which we support.  It is directly indexed by the pci_board_num_t enum
1437  * value, which is encoded in the pci_device_id PCI probe table's
1438  * driver_data member.
1439  *
1440  * The makeup of these names are:
1441  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1442  *
1443  *  bn          = PCI BAR number
1444  *  bt          = Index using PCI BARs
1445  *  n           = number of serial ports
1446  *  baud        = baud rate
1447  *  offsetinhex = offset for each sequential port (in hex)
1448  *
1449  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1450  *
1451  * Please note: in theory if n = 1, _bt infix should make no difference.
1452  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1453  */
1454 enum pci_board_num_t {
1455         pbn_default = 0,
1456
1457         pbn_b0_1_115200,
1458         pbn_b0_2_115200,
1459         pbn_b0_4_115200,
1460         pbn_b0_5_115200,
1461         pbn_b0_8_115200,
1462
1463         pbn_b0_1_921600,
1464         pbn_b0_2_921600,
1465         pbn_b0_4_921600,
1466
1467         pbn_b0_2_1130000,
1468
1469         pbn_b0_4_1152000,
1470
1471         pbn_b0_2_1843200,
1472         pbn_b0_4_1843200,
1473
1474         pbn_b0_2_1843200_200,
1475         pbn_b0_4_1843200_200,
1476         pbn_b0_8_1843200_200,
1477
1478         pbn_b0_1_4000000,
1479
1480         pbn_b0_bt_1_115200,
1481         pbn_b0_bt_2_115200,
1482         pbn_b0_bt_8_115200,
1483
1484         pbn_b0_bt_1_460800,
1485         pbn_b0_bt_2_460800,
1486         pbn_b0_bt_4_460800,
1487
1488         pbn_b0_bt_1_921600,
1489         pbn_b0_bt_2_921600,
1490         pbn_b0_bt_4_921600,
1491         pbn_b0_bt_8_921600,
1492
1493         pbn_b1_1_115200,
1494         pbn_b1_2_115200,
1495         pbn_b1_4_115200,
1496         pbn_b1_8_115200,
1497         pbn_b1_16_115200,
1498
1499         pbn_b1_1_921600,
1500         pbn_b1_2_921600,
1501         pbn_b1_4_921600,
1502         pbn_b1_8_921600,
1503
1504         pbn_b1_2_1250000,
1505
1506         pbn_b1_bt_1_115200,
1507         pbn_b1_bt_2_115200,
1508         pbn_b1_bt_4_115200,
1509
1510         pbn_b1_bt_2_921600,
1511
1512         pbn_b1_1_1382400,
1513         pbn_b1_2_1382400,
1514         pbn_b1_4_1382400,
1515         pbn_b1_8_1382400,
1516
1517         pbn_b2_1_115200,
1518         pbn_b2_2_115200,
1519         pbn_b2_4_115200,
1520         pbn_b2_8_115200,
1521
1522         pbn_b2_1_460800,
1523         pbn_b2_4_460800,
1524         pbn_b2_8_460800,
1525         pbn_b2_16_460800,
1526
1527         pbn_b2_1_921600,
1528         pbn_b2_4_921600,
1529         pbn_b2_8_921600,
1530
1531         pbn_b2_bt_1_115200,
1532         pbn_b2_bt_2_115200,
1533         pbn_b2_bt_4_115200,
1534
1535         pbn_b2_bt_2_921600,
1536         pbn_b2_bt_4_921600,
1537
1538         pbn_b3_2_115200,
1539         pbn_b3_4_115200,
1540         pbn_b3_8_115200,
1541
1542         /*
1543          * Board-specific versions.
1544          */
1545         pbn_panacom,
1546         pbn_panacom2,
1547         pbn_panacom4,
1548         pbn_exsys_4055,
1549         pbn_plx_romulus,
1550         pbn_oxsemi,
1551         pbn_oxsemi_1_4000000,
1552         pbn_oxsemi_2_4000000,
1553         pbn_oxsemi_4_4000000,
1554         pbn_oxsemi_8_4000000,
1555         pbn_intel_i960,
1556         pbn_sgi_ioc3,
1557         pbn_computone_4,
1558         pbn_computone_6,
1559         pbn_computone_8,
1560         pbn_sbsxrsio,
1561         pbn_exar_XR17C152,
1562         pbn_exar_XR17C154,
1563         pbn_exar_XR17C158,
1564         pbn_pasemi_1682M,
1565         pbn_ni8430_2,
1566         pbn_ni8430_4,
1567         pbn_ni8430_8,
1568         pbn_ni8430_16,
1569         pbn_ADDIDATA_PCIe_1_3906250,
1570         pbn_ADDIDATA_PCIe_2_3906250,
1571         pbn_ADDIDATA_PCIe_4_3906250,
1572         pbn_ADDIDATA_PCIe_8_3906250,
1573 };
1574
1575 /*
1576  * uart_offset - the space between channels
1577  * reg_shift   - describes how the UART registers are mapped
1578  *               to PCI memory by the card.
1579  * For example IER register on SBS, Inc. PMC-OctPro is located at
1580  * offset 0x10 from the UART base, while UART_IER is defined as 1
1581  * in include/linux/serial_reg.h,
1582  * see first lines of serial_in() and serial_out() in 8250.c
1583 */
1584
1585 static struct pciserial_board pci_boards[] __devinitdata = {
1586         [pbn_default] = {
1587                 .flags          = FL_BASE0,
1588                 .num_ports      = 1,
1589                 .base_baud      = 115200,
1590                 .uart_offset    = 8,
1591         },
1592         [pbn_b0_1_115200] = {
1593                 .flags          = FL_BASE0,
1594                 .num_ports      = 1,
1595                 .base_baud      = 115200,
1596                 .uart_offset    = 8,
1597         },
1598         [pbn_b0_2_115200] = {
1599                 .flags          = FL_BASE0,
1600                 .num_ports      = 2,
1601                 .base_baud      = 115200,
1602                 .uart_offset    = 8,
1603         },
1604         [pbn_b0_4_115200] = {
1605                 .flags          = FL_BASE0,
1606                 .num_ports      = 4,
1607                 .base_baud      = 115200,
1608                 .uart_offset    = 8,
1609         },
1610         [pbn_b0_5_115200] = {
1611                 .flags          = FL_BASE0,
1612                 .num_ports      = 5,
1613                 .base_baud      = 115200,
1614                 .uart_offset    = 8,
1615         },
1616         [pbn_b0_8_115200] = {
1617                 .flags          = FL_BASE0,
1618                 .num_ports      = 8,
1619                 .base_baud      = 115200,
1620                 .uart_offset    = 8,
1621         },
1622         [pbn_b0_1_921600] = {
1623                 .flags          = FL_BASE0,
1624                 .num_ports      = 1,
1625                 .base_baud      = 921600,
1626                 .uart_offset    = 8,
1627         },
1628         [pbn_b0_2_921600] = {
1629                 .flags          = FL_BASE0,
1630                 .num_ports      = 2,
1631                 .base_baud      = 921600,
1632                 .uart_offset    = 8,
1633         },
1634         [pbn_b0_4_921600] = {
1635                 .flags          = FL_BASE0,
1636                 .num_ports      = 4,
1637                 .base_baud      = 921600,
1638                 .uart_offset    = 8,
1639         },
1640
1641         [pbn_b0_2_1130000] = {
1642                 .flags          = FL_BASE0,
1643                 .num_ports      = 2,
1644                 .base_baud      = 1130000,
1645                 .uart_offset    = 8,
1646         },
1647
1648         [pbn_b0_4_1152000] = {
1649                 .flags          = FL_BASE0,
1650                 .num_ports      = 4,
1651                 .base_baud      = 1152000,
1652                 .uart_offset    = 8,
1653         },
1654
1655         [pbn_b0_2_1843200] = {
1656                 .flags          = FL_BASE0,
1657                 .num_ports      = 2,
1658                 .base_baud      = 1843200,
1659                 .uart_offset    = 8,
1660         },
1661         [pbn_b0_4_1843200] = {
1662                 .flags          = FL_BASE0,
1663                 .num_ports      = 4,
1664                 .base_baud      = 1843200,
1665                 .uart_offset    = 8,
1666         },
1667
1668         [pbn_b0_2_1843200_200] = {
1669                 .flags          = FL_BASE0,
1670                 .num_ports      = 2,
1671                 .base_baud      = 1843200,
1672                 .uart_offset    = 0x200,
1673         },
1674         [pbn_b0_4_1843200_200] = {
1675                 .flags          = FL_BASE0,
1676                 .num_ports      = 4,
1677                 .base_baud      = 1843200,
1678                 .uart_offset    = 0x200,
1679         },
1680         [pbn_b0_8_1843200_200] = {
1681                 .flags          = FL_BASE0,
1682                 .num_ports      = 8,
1683                 .base_baud      = 1843200,
1684                 .uart_offset    = 0x200,
1685         },
1686         [pbn_b0_1_4000000] = {
1687                 .flags          = FL_BASE0,
1688                 .num_ports      = 1,
1689                 .base_baud      = 4000000,
1690                 .uart_offset    = 8,
1691         },
1692
1693         [pbn_b0_bt_1_115200] = {
1694                 .flags          = FL_BASE0|FL_BASE_BARS,
1695                 .num_ports      = 1,
1696                 .base_baud      = 115200,
1697                 .uart_offset    = 8,
1698         },
1699         [pbn_b0_bt_2_115200] = {
1700                 .flags          = FL_BASE0|FL_BASE_BARS,
1701                 .num_ports      = 2,
1702                 .base_baud      = 115200,
1703                 .uart_offset    = 8,
1704         },
1705         [pbn_b0_bt_8_115200] = {
1706                 .flags          = FL_BASE0|FL_BASE_BARS,
1707                 .num_ports      = 8,
1708                 .base_baud      = 115200,
1709                 .uart_offset    = 8,
1710         },
1711
1712         [pbn_b0_bt_1_460800] = {
1713                 .flags          = FL_BASE0|FL_BASE_BARS,
1714                 .num_ports      = 1,
1715                 .base_baud      = 460800,
1716                 .uart_offset    = 8,
1717         },
1718         [pbn_b0_bt_2_460800] = {
1719                 .flags          = FL_BASE0|FL_BASE_BARS,
1720                 .num_ports      = 2,
1721                 .base_baud      = 460800,
1722                 .uart_offset    = 8,
1723         },
1724         [pbn_b0_bt_4_460800] = {
1725                 .flags          = FL_BASE0|FL_BASE_BARS,
1726                 .num_ports      = 4,
1727                 .base_baud      = 460800,
1728                 .uart_offset    = 8,
1729         },
1730
1731         [pbn_b0_bt_1_921600] = {
1732                 .flags          = FL_BASE0|FL_BASE_BARS,
1733                 .num_ports      = 1,
1734                 .base_baud      = 921600,
1735                 .uart_offset    = 8,
1736         },
1737         [pbn_b0_bt_2_921600] = {
1738                 .flags          = FL_BASE0|FL_BASE_BARS,
1739                 .num_ports      = 2,
1740                 .base_baud      = 921600,
1741                 .uart_offset    = 8,
1742         },
1743         [pbn_b0_bt_4_921600] = {
1744                 .flags          = FL_BASE0|FL_BASE_BARS,
1745                 .num_ports      = 4,
1746                 .base_baud      = 921600,
1747                 .uart_offset    = 8,
1748         },
1749         [pbn_b0_bt_8_921600] = {
1750                 .flags          = FL_BASE0|FL_BASE_BARS,
1751                 .num_ports      = 8,
1752                 .base_baud      = 921600,
1753                 .uart_offset    = 8,
1754         },
1755
1756         [pbn_b1_1_115200] = {
1757                 .flags          = FL_BASE1,
1758                 .num_ports      = 1,
1759                 .base_baud      = 115200,
1760                 .uart_offset    = 8,
1761         },
1762         [pbn_b1_2_115200] = {
1763                 .flags          = FL_BASE1,
1764                 .num_ports      = 2,
1765                 .base_baud      = 115200,
1766                 .uart_offset    = 8,
1767         },
1768         [pbn_b1_4_115200] = {
1769                 .flags          = FL_BASE1,
1770                 .num_ports      = 4,
1771                 .base_baud      = 115200,
1772                 .uart_offset    = 8,
1773         },
1774         [pbn_b1_8_115200] = {
1775                 .flags          = FL_BASE1,
1776                 .num_ports      = 8,
1777                 .base_baud      = 115200,
1778                 .uart_offset    = 8,
1779         },
1780         [pbn_b1_16_115200] = {
1781                 .flags          = FL_BASE1,
1782                 .num_ports      = 16,
1783                 .base_baud      = 115200,
1784                 .uart_offset    = 8,
1785         },
1786
1787         [pbn_b1_1_921600] = {
1788                 .flags          = FL_BASE1,
1789                 .num_ports      = 1,
1790                 .base_baud      = 921600,
1791                 .uart_offset    = 8,
1792         },
1793         [pbn_b1_2_921600] = {
1794                 .flags          = FL_BASE1,
1795                 .num_ports      = 2,
1796                 .base_baud      = 921600,
1797                 .uart_offset    = 8,
1798         },
1799         [pbn_b1_4_921600] = {
1800                 .flags          = FL_BASE1,
1801                 .num_ports      = 4,
1802                 .base_baud      = 921600,
1803                 .uart_offset    = 8,
1804         },
1805         [pbn_b1_8_921600] = {
1806                 .flags          = FL_BASE1,
1807                 .num_ports      = 8,
1808                 .base_baud      = 921600,
1809                 .uart_offset    = 8,
1810         },
1811         [pbn_b1_2_1250000] = {
1812                 .flags          = FL_BASE1,
1813                 .num_ports      = 2,
1814                 .base_baud      = 1250000,
1815                 .uart_offset    = 8,
1816         },
1817
1818         [pbn_b1_bt_1_115200] = {
1819                 .flags          = FL_BASE1|FL_BASE_BARS,
1820                 .num_ports      = 1,
1821                 .base_baud      = 115200,
1822                 .uart_offset    = 8,
1823         },
1824         [pbn_b1_bt_2_115200] = {
1825                 .flags          = FL_BASE1|FL_BASE_BARS,
1826                 .num_ports      = 2,
1827                 .base_baud      = 115200,
1828                 .uart_offset    = 8,
1829         },
1830         [pbn_b1_bt_4_115200] = {
1831                 .flags          = FL_BASE1|FL_BASE_BARS,
1832                 .num_ports      = 4,
1833                 .base_baud      = 115200,
1834                 .uart_offset    = 8,
1835         },
1836
1837         [pbn_b1_bt_2_921600] = {
1838                 .flags          = FL_BASE1|FL_BASE_BARS,
1839                 .num_ports      = 2,
1840                 .base_baud      = 921600,
1841                 .uart_offset    = 8,
1842         },
1843
1844         [pbn_b1_1_1382400] = {
1845                 .flags          = FL_BASE1,
1846                 .num_ports      = 1,
1847                 .base_baud      = 1382400,
1848                 .uart_offset    = 8,
1849         },
1850         [pbn_b1_2_1382400] = {
1851                 .flags          = FL_BASE1,
1852                 .num_ports      = 2,
1853                 .base_baud      = 1382400,
1854                 .uart_offset    = 8,
1855         },
1856         [pbn_b1_4_1382400] = {
1857                 .flags          = FL_BASE1,
1858                 .num_ports      = 4,
1859                 .base_baud      = 1382400,
1860                 .uart_offset    = 8,
1861         },
1862         [pbn_b1_8_1382400] = {
1863                 .flags          = FL_BASE1,
1864                 .num_ports      = 8,
1865                 .base_baud      = 1382400,
1866                 .uart_offset    = 8,
1867         },
1868
1869         [pbn_b2_1_115200] = {
1870                 .flags          = FL_BASE2,
1871                 .num_ports      = 1,
1872                 .base_baud      = 115200,
1873                 .uart_offset    = 8,
1874         },
1875         [pbn_b2_2_115200] = {
1876                 .flags          = FL_BASE2,
1877                 .num_ports      = 2,
1878                 .base_baud      = 115200,
1879                 .uart_offset    = 8,
1880         },
1881         [pbn_b2_4_115200] = {
1882                 .flags          = FL_BASE2,
1883                 .num_ports      = 4,
1884                 .base_baud      = 115200,
1885                 .uart_offset    = 8,
1886         },
1887         [pbn_b2_8_115200] = {
1888                 .flags          = FL_BASE2,
1889                 .num_ports      = 8,
1890                 .base_baud      = 115200,
1891                 .uart_offset    = 8,
1892         },
1893
1894         [pbn_b2_1_460800] = {
1895                 .flags          = FL_BASE2,
1896                 .num_ports      = 1,
1897                 .base_baud      = 460800,
1898                 .uart_offset    = 8,
1899         },
1900         [pbn_b2_4_460800] = {
1901                 .flags          = FL_BASE2,
1902                 .num_ports      = 4,
1903                 .base_baud      = 460800,
1904                 .uart_offset    = 8,
1905         },
1906         [pbn_b2_8_460800] = {
1907                 .flags          = FL_BASE2,
1908                 .num_ports      = 8,
1909                 .base_baud      = 460800,
1910                 .uart_offset    = 8,
1911         },
1912         [pbn_b2_16_460800] = {
1913                 .flags          = FL_BASE2,
1914                 .num_ports      = 16,
1915                 .base_baud      = 460800,
1916                 .uart_offset    = 8,
1917          },
1918
1919         [pbn_b2_1_921600] = {
1920                 .flags          = FL_BASE2,
1921                 .num_ports      = 1,
1922                 .base_baud      = 921600,
1923                 .uart_offset    = 8,
1924         },
1925         [pbn_b2_4_921600] = {
1926                 .flags          = FL_BASE2,
1927                 .num_ports      = 4,
1928                 .base_baud      = 921600,
1929                 .uart_offset    = 8,
1930         },
1931         [pbn_b2_8_921600] = {
1932                 .flags          = FL_BASE2,
1933                 .num_ports      = 8,
1934                 .base_baud      = 921600,
1935                 .uart_offset    = 8,
1936         },
1937
1938         [pbn_b2_bt_1_115200] = {
1939                 .flags          = FL_BASE2|FL_BASE_BARS,
1940                 .num_ports      = 1,
1941                 .base_baud      = 115200,
1942                 .uart_offset    = 8,
1943         },
1944         [pbn_b2_bt_2_115200] = {
1945                 .flags          = FL_BASE2|FL_BASE_BARS,
1946                 .num_ports      = 2,
1947                 .base_baud      = 115200,
1948                 .uart_offset    = 8,
1949         },
1950         [pbn_b2_bt_4_115200] = {
1951                 .flags          = FL_BASE2|FL_BASE_BARS,
1952                 .num_ports      = 4,
1953                 .base_baud      = 115200,
1954                 .uart_offset    = 8,
1955         },
1956
1957         [pbn_b2_bt_2_921600] = {
1958                 .flags          = FL_BASE2|FL_BASE_BARS,
1959                 .num_ports      = 2,
1960                 .base_baud      = 921600,
1961                 .uart_offset    = 8,
1962         },
1963         [pbn_b2_bt_4_921600] = {
1964                 .flags          = FL_BASE2|FL_BASE_BARS,
1965                 .num_ports      = 4,
1966                 .base_baud      = 921600,
1967                 .uart_offset    = 8,
1968         },
1969
1970         [pbn_b3_2_115200] = {
1971                 .flags          = FL_BASE3,
1972                 .num_ports      = 2,
1973                 .base_baud      = 115200,
1974                 .uart_offset    = 8,
1975         },
1976         [pbn_b3_4_115200] = {
1977                 .flags          = FL_BASE3,
1978                 .num_ports      = 4,
1979                 .base_baud      = 115200,
1980                 .uart_offset    = 8,
1981         },
1982         [pbn_b3_8_115200] = {
1983                 .flags          = FL_BASE3,
1984                 .num_ports      = 8,
1985                 .base_baud      = 115200,
1986                 .uart_offset    = 8,
1987         },
1988
1989         /*
1990          * Entries following this are board-specific.
1991          */
1992
1993         /*
1994          * Panacom - IOMEM
1995          */
1996         [pbn_panacom] = {
1997                 .flags          = FL_BASE2,
1998                 .num_ports      = 2,
1999                 .base_baud      = 921600,
2000                 .uart_offset    = 0x400,
2001                 .reg_shift      = 7,
2002         },
2003         [pbn_panacom2] = {
2004                 .flags          = FL_BASE2|FL_BASE_BARS,
2005                 .num_ports      = 2,
2006                 .base_baud      = 921600,
2007                 .uart_offset    = 0x400,
2008                 .reg_shift      = 7,
2009         },
2010         [pbn_panacom4] = {
2011                 .flags          = FL_BASE2|FL_BASE_BARS,
2012                 .num_ports      = 4,
2013                 .base_baud      = 921600,
2014                 .uart_offset    = 0x400,
2015                 .reg_shift      = 7,
2016         },
2017
2018         [pbn_exsys_4055] = {
2019                 .flags          = FL_BASE2,
2020                 .num_ports      = 4,
2021                 .base_baud      = 115200,
2022                 .uart_offset    = 8,
2023         },
2024
2025         /* I think this entry is broken - the first_offset looks wrong --rmk */
2026         [pbn_plx_romulus] = {
2027                 .flags          = FL_BASE2,
2028                 .num_ports      = 4,
2029                 .base_baud      = 921600,
2030                 .uart_offset    = 8 << 2,
2031                 .reg_shift      = 2,
2032                 .first_offset   = 0x03,
2033         },
2034
2035         /*
2036          * This board uses the size of PCI Base region 0 to
2037          * signal now many ports are available
2038          */
2039         [pbn_oxsemi] = {
2040                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2041                 .num_ports      = 32,
2042                 .base_baud      = 115200,
2043                 .uart_offset    = 8,
2044         },
2045         [pbn_oxsemi_1_4000000] = {
2046                 .flags          = FL_BASE0,
2047                 .num_ports      = 1,
2048                 .base_baud      = 4000000,
2049                 .uart_offset    = 0x200,
2050                 .first_offset   = 0x1000,
2051         },
2052         [pbn_oxsemi_2_4000000] = {
2053                 .flags          = FL_BASE0,
2054                 .num_ports      = 2,
2055                 .base_baud      = 4000000,
2056                 .uart_offset    = 0x200,
2057                 .first_offset   = 0x1000,
2058         },
2059         [pbn_oxsemi_4_4000000] = {
2060                 .flags          = FL_BASE0,
2061                 .num_ports      = 4,
2062                 .base_baud      = 4000000,
2063                 .uart_offset    = 0x200,
2064                 .first_offset   = 0x1000,
2065         },
2066         [pbn_oxsemi_8_4000000] = {
2067                 .flags          = FL_BASE0,
2068                 .num_ports      = 8,
2069                 .base_baud      = 4000000,
2070                 .uart_offset    = 0x200,
2071                 .first_offset   = 0x1000,
2072         },
2073
2074
2075         /*
2076          * EKF addition for i960 Boards form EKF with serial port.
2077          * Max 256 ports.
2078          */
2079         [pbn_intel_i960] = {
2080                 .flags          = FL_BASE0,
2081                 .num_ports      = 32,
2082                 .base_baud      = 921600,
2083                 .uart_offset    = 8 << 2,
2084                 .reg_shift      = 2,
2085                 .first_offset   = 0x10000,
2086         },
2087         [pbn_sgi_ioc3] = {
2088                 .flags          = FL_BASE0|FL_NOIRQ,
2089                 .num_ports      = 1,
2090                 .base_baud      = 458333,
2091                 .uart_offset    = 8,
2092                 .reg_shift      = 0,
2093                 .first_offset   = 0x20178,
2094         },
2095
2096         /*
2097          * Computone - uses IOMEM.
2098          */
2099         [pbn_computone_4] = {
2100                 .flags          = FL_BASE0,
2101                 .num_ports      = 4,
2102                 .base_baud      = 921600,
2103                 .uart_offset    = 0x40,
2104                 .reg_shift      = 2,
2105                 .first_offset   = 0x200,
2106         },
2107         [pbn_computone_6] = {
2108                 .flags          = FL_BASE0,
2109                 .num_ports      = 6,
2110                 .base_baud      = 921600,
2111                 .uart_offset    = 0x40,
2112                 .reg_shift      = 2,
2113                 .first_offset   = 0x200,
2114         },
2115         [pbn_computone_8] = {
2116                 .flags          = FL_BASE0,
2117                 .num_ports      = 8,
2118                 .base_baud      = 921600,
2119                 .uart_offset    = 0x40,
2120                 .reg_shift      = 2,
2121                 .first_offset   = 0x200,
2122         },
2123         [pbn_sbsxrsio] = {
2124                 .flags          = FL_BASE0,
2125                 .num_ports      = 8,
2126                 .base_baud      = 460800,
2127                 .uart_offset    = 256,
2128                 .reg_shift      = 4,
2129         },
2130         /*
2131          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2132          *  Only basic 16550A support.
2133          *  XR17C15[24] are not tested, but they should work.
2134          */
2135         [pbn_exar_XR17C152] = {
2136                 .flags          = FL_BASE0,
2137                 .num_ports      = 2,
2138                 .base_baud      = 921600,
2139                 .uart_offset    = 0x200,
2140         },
2141         [pbn_exar_XR17C154] = {
2142                 .flags          = FL_BASE0,
2143                 .num_ports      = 4,
2144                 .base_baud      = 921600,
2145                 .uart_offset    = 0x200,
2146         },
2147         [pbn_exar_XR17C158] = {
2148                 .flags          = FL_BASE0,
2149                 .num_ports      = 8,
2150                 .base_baud      = 921600,
2151                 .uart_offset    = 0x200,
2152         },
2153         /*
2154          * PA Semi PWRficient PA6T-1682M on-chip UART
2155          */
2156         [pbn_pasemi_1682M] = {
2157                 .flags          = FL_BASE0,
2158                 .num_ports      = 1,
2159                 .base_baud      = 8333333,
2160         },
2161         /*
2162          * National Instruments 843x
2163          */
2164         [pbn_ni8430_16] = {
2165                 .flags          = FL_BASE0,
2166                 .num_ports      = 16,
2167                 .base_baud      = 3686400,
2168                 .uart_offset    = 0x10,
2169                 .first_offset   = 0x800,
2170         },
2171         [pbn_ni8430_8] = {
2172                 .flags          = FL_BASE0,
2173                 .num_ports      = 8,
2174                 .base_baud      = 3686400,
2175                 .uart_offset    = 0x10,
2176                 .first_offset   = 0x800,
2177         },
2178         [pbn_ni8430_4] = {
2179                 .flags          = FL_BASE0,
2180                 .num_ports      = 4,
2181                 .base_baud      = 3686400,
2182                 .uart_offset    = 0x10,
2183                 .first_offset   = 0x800,
2184         },
2185         [pbn_ni8430_2] = {
2186                 .flags          = FL_BASE0,
2187                 .num_ports      = 2,
2188                 .base_baud      = 3686400,
2189                 .uart_offset    = 0x10,
2190                 .first_offset   = 0x800,
2191         },
2192         /*
2193          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2194          */
2195         [pbn_ADDIDATA_PCIe_1_3906250] = {
2196                 .flags          = FL_BASE0,
2197                 .num_ports      = 1,
2198                 .base_baud      = 3906250,
2199                 .uart_offset    = 0x200,
2200                 .first_offset   = 0x1000,
2201         },
2202         [pbn_ADDIDATA_PCIe_2_3906250] = {
2203                 .flags          = FL_BASE0,
2204                 .num_ports      = 2,
2205                 .base_baud      = 3906250,
2206                 .uart_offset    = 0x200,
2207                 .first_offset   = 0x1000,
2208         },
2209         [pbn_ADDIDATA_PCIe_4_3906250] = {
2210                 .flags          = FL_BASE0,
2211                 .num_ports      = 4,
2212                 .base_baud      = 3906250,
2213                 .uart_offset    = 0x200,
2214                 .first_offset   = 0x1000,
2215         },
2216         [pbn_ADDIDATA_PCIe_8_3906250] = {
2217                 .flags          = FL_BASE0,
2218                 .num_ports      = 8,
2219                 .base_baud      = 3906250,
2220                 .uart_offset    = 0x200,
2221                 .first_offset   = 0x1000,
2222         },
2223 };
2224
2225 static const struct pci_device_id softmodem_blacklist[] = {
2226         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2227 };
2228
2229 /*
2230  * Given a complete unknown PCI device, try to use some heuristics to
2231  * guess what the configuration might be, based on the pitiful PCI
2232  * serial specs.  Returns 0 on success, 1 on failure.
2233  */
2234 static int __devinit
2235 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2236 {
2237         const struct pci_device_id *blacklist;
2238         int num_iomem, num_port, first_port = -1, i;
2239
2240         /*
2241          * If it is not a communications device or the programming
2242          * interface is greater than 6, give up.
2243          *
2244          * (Should we try to make guesses for multiport serial devices
2245          * later?)
2246          */
2247         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2248              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2249             (dev->class & 0xff) > 6)
2250                 return -ENODEV;
2251
2252         /*
2253          * Do not access blacklisted devices that are known not to
2254          * feature serial ports.
2255          */
2256         for (blacklist = softmodem_blacklist;
2257              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2258              blacklist++) {
2259                 if (dev->vendor == blacklist->vendor &&
2260                     dev->device == blacklist->device)
2261                         return -ENODEV;
2262         }
2263
2264         num_iomem = num_port = 0;
2265         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2266                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2267                         num_port++;
2268                         if (first_port == -1)
2269                                 first_port = i;
2270                 }
2271                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2272                         num_iomem++;
2273         }
2274
2275         /*
2276          * If there is 1 or 0 iomem regions, and exactly one port,
2277          * use it.  We guess the number of ports based on the IO
2278          * region size.
2279          */
2280         if (num_iomem <= 1 && num_port == 1) {
2281                 board->flags = first_port;
2282                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2283                 return 0;
2284         }
2285
2286         /*
2287          * Now guess if we've got a board which indexes by BARs.
2288          * Each IO BAR should be 8 bytes, and they should follow
2289          * consecutively.
2290          */
2291         first_port = -1;
2292         num_port = 0;
2293         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2294                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2295                     pci_resource_len(dev, i) == 8 &&
2296                     (first_port == -1 || (first_port + num_port) == i)) {
2297                         num_port++;
2298                         if (first_port == -1)
2299                                 first_port = i;
2300                 }
2301         }
2302
2303         if (num_port > 1) {
2304                 board->flags = first_port | FL_BASE_BARS;
2305                 board->num_ports = num_port;
2306                 return 0;
2307         }
2308
2309         return -ENODEV;
2310 }
2311
2312 static inline int
2313 serial_pci_matches(const struct pciserial_board *board,
2314                    const struct pciserial_board *guessed)
2315 {
2316         return
2317             board->num_ports == guessed->num_ports &&
2318             board->base_baud == guessed->base_baud &&
2319             board->uart_offset == guessed->uart_offset &&
2320             board->reg_shift == guessed->reg_shift &&
2321             board->first_offset == guessed->first_offset;
2322 }
2323
2324 struct serial_private *
2325 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2326 {
2327         struct uart_port serial_port;
2328         struct serial_private *priv;
2329         struct pci_serial_quirk *quirk;
2330         int rc, nr_ports, i;
2331
2332         nr_ports = board->num_ports;
2333
2334         /*
2335          * Find an init and setup quirks.
2336          */
2337         quirk = find_quirk(dev);
2338
2339         /*
2340          * Run the new-style initialization function.
2341          * The initialization function returns:
2342          *  <0  - error
2343          *   0  - use board->num_ports
2344          *  >0  - number of ports
2345          */
2346         if (quirk->init) {
2347                 rc = quirk->init(dev);
2348                 if (rc < 0) {
2349                         priv = ERR_PTR(rc);
2350                         goto err_out;
2351                 }
2352                 if (rc)
2353                         nr_ports = rc;
2354         }
2355
2356         priv = kzalloc(sizeof(struct serial_private) +
2357                        sizeof(unsigned int) * nr_ports,
2358                        GFP_KERNEL);
2359         if (!priv) {
2360                 priv = ERR_PTR(-ENOMEM);
2361                 goto err_deinit;
2362         }
2363
2364         priv->dev = dev;
2365         priv->quirk = quirk;
2366
2367         memset(&serial_port, 0, sizeof(struct uart_port));
2368         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2369         serial_port.uartclk = board->base_baud * 16;
2370         serial_port.irq = get_pci_irq(dev, board);
2371         serial_port.dev = &dev->dev;
2372
2373         for (i = 0; i < nr_ports; i++) {
2374                 if (quirk->setup(priv, board, &serial_port, i))
2375                         break;
2376
2377 #ifdef SERIAL_DEBUG_PCI
2378                 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
2379                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2380 #endif
2381
2382                 priv->line[i] = serial8250_register_port(&serial_port);
2383                 if (priv->line[i] < 0) {
2384                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2385                         break;
2386                 }
2387         }
2388         priv->nr = i;
2389         return priv;
2390
2391 err_deinit:
2392         if (quirk->exit)
2393                 quirk->exit(dev);
2394 err_out:
2395         return priv;
2396 }
2397 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2398
2399 void pciserial_remove_ports(struct serial_private *priv)
2400 {
2401         struct pci_serial_quirk *quirk;
2402         int i;
2403
2404         for (i = 0; i < priv->nr; i++)
2405                 serial8250_unregister_port(priv->line[i]);
2406
2407         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2408                 if (priv->remapped_bar[i])
2409                         iounmap(priv->remapped_bar[i]);
2410                 priv->remapped_bar[i] = NULL;
2411         }
2412
2413         /*
2414          * Find the exit quirks.
2415          */
2416         quirk = find_quirk(priv->dev);
2417         if (quirk->exit)
2418                 quirk->exit(priv->dev);
2419
2420         kfree(priv);
2421 }
2422 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2423
2424 void pciserial_suspend_ports(struct serial_private *priv)
2425 {
2426         int i;
2427
2428         for (i = 0; i < priv->nr; i++)
2429                 if (priv->line[i] >= 0)
2430                         serial8250_suspend_port(priv->line[i]);
2431 }
2432 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2433
2434 void pciserial_resume_ports(struct serial_private *priv)
2435 {
2436         int i;
2437
2438         /*
2439          * Ensure that the board is correctly configured.
2440          */
2441         if (priv->quirk->init)
2442                 priv->quirk->init(priv->dev);
2443
2444         for (i = 0; i < priv->nr; i++)
2445                 if (priv->line[i] >= 0)
2446                         serial8250_resume_port(priv->line[i]);
2447 }
2448 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2449
2450 /*
2451  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2452  * to the arrangement of serial ports on a PCI card.
2453  */
2454 static int __devinit
2455 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2456 {
2457         struct serial_private *priv;
2458         const struct pciserial_board *board;
2459         struct pciserial_board tmp;
2460         int rc;
2461
2462         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2463                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2464                         ent->driver_data);
2465                 return -EINVAL;
2466         }
2467
2468         board = &pci_boards[ent->driver_data];
2469
2470         rc = pci_enable_device(dev);
2471         if (rc)
2472                 return rc;
2473
2474         if (ent->driver_data == pbn_default) {
2475                 /*
2476                  * Use a copy of the pci_board entry for this;
2477                  * avoid changing entries in the table.
2478                  */
2479                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2480                 board = &tmp;
2481
2482                 /*
2483                  * We matched one of our class entries.  Try to
2484                  * determine the parameters of this board.
2485                  */
2486                 rc = serial_pci_guess_board(dev, &tmp);
2487                 if (rc)
2488                         goto disable;
2489         } else {
2490                 /*
2491                  * We matched an explicit entry.  If we are able to
2492                  * detect this boards settings with our heuristic,
2493                  * then we no longer need this entry.
2494                  */
2495                 memcpy(&tmp, &pci_boards[pbn_default],
2496                        sizeof(struct pciserial_board));
2497                 rc = serial_pci_guess_board(dev, &tmp);
2498                 if (rc == 0 && serial_pci_matches(board, &tmp))
2499                         moan_device("Redundant entry in serial pci_table.",
2500                                     dev);
2501         }
2502
2503         priv = pciserial_init_ports(dev, board);
2504         if (!IS_ERR(priv)) {
2505                 pci_set_drvdata(dev, priv);
2506                 return 0;
2507         }
2508
2509         rc = PTR_ERR(priv);
2510
2511  disable:
2512         pci_disable_device(dev);
2513         return rc;
2514 }
2515
2516 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2517 {
2518         struct serial_private *priv = pci_get_drvdata(dev);
2519
2520         pci_set_drvdata(dev, NULL);
2521
2522         pciserial_remove_ports(priv);
2523
2524         pci_disable_device(dev);
2525 }
2526
2527 #ifdef CONFIG_PM
2528 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2529 {
2530         struct serial_private *priv = pci_get_drvdata(dev);
2531
2532         if (priv)
2533                 pciserial_suspend_ports(priv);
2534
2535         pci_save_state(dev);
2536         pci_set_power_state(dev, pci_choose_state(dev, state));
2537         return 0;
2538 }
2539
2540 static int pciserial_resume_one(struct pci_dev *dev)
2541 {
2542         int err;
2543         struct serial_private *priv = pci_get_drvdata(dev);
2544
2545         pci_set_power_state(dev, PCI_D0);
2546         pci_restore_state(dev);
2547
2548         if (priv) {
2549                 /*
2550                  * The device may have been disabled.  Re-enable it.
2551                  */
2552                 err = pci_enable_device(dev);
2553                 /* FIXME: We cannot simply error out here */
2554                 if (err)
2555                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2556                 pciserial_resume_ports(priv);
2557         }
2558         return 0;
2559 }
2560 #endif
2561
2562 static struct pci_device_id serial_pci_tbl[] = {
2563         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2564         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2565                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2566                 pbn_b2_8_921600 },
2567         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2568                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2569                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2570                 pbn_b1_8_1382400 },
2571         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2572                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2573                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2574                 pbn_b1_4_1382400 },
2575         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2576                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2577                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2578                 pbn_b1_2_1382400 },
2579         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2580                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2581                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2582                 pbn_b1_8_1382400 },
2583         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2584                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2585                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2586                 pbn_b1_4_1382400 },
2587         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2588                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2589                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2590                 pbn_b1_2_1382400 },
2591         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2592                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2593                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2594                 pbn_b1_8_921600 },
2595         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2596                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2597                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2598                 pbn_b1_8_921600 },
2599         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2600                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2601                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2602                 pbn_b1_4_921600 },
2603         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2604                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2605                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2606                 pbn_b1_4_921600 },
2607         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2608                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2609                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2610                 pbn_b1_2_921600 },
2611         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2612                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2613                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2614                 pbn_b1_8_921600 },
2615         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2616                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2617                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2618                 pbn_b1_8_921600 },
2619         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2620                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2621                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2622                 pbn_b1_4_921600 },
2623         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2624                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2625                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2626                 pbn_b1_2_1250000 },
2627         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2628                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2629                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2630                 pbn_b0_2_1843200 },
2631         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2632                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2633                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2634                 pbn_b0_4_1843200 },
2635         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2636                 PCI_VENDOR_ID_AFAVLAB,
2637                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2638                 pbn_b0_4_1152000 },
2639         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2640                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2641                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2642                 pbn_b0_2_1843200_200 },
2643         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2644                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2645                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2646                 pbn_b0_4_1843200_200 },
2647         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2648                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2649                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2650                 pbn_b0_8_1843200_200 },
2651         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2652                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2653                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2654                 pbn_b0_2_1843200_200 },
2655         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2656                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2657                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2658                 pbn_b0_4_1843200_200 },
2659         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2660                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2661                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2662                 pbn_b0_8_1843200_200 },
2663         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2664                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2665                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2666                 pbn_b0_2_1843200_200 },
2667         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2668                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2669                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2670                 pbn_b0_4_1843200_200 },
2671         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2672                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2673                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2674                 pbn_b0_8_1843200_200 },
2675         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2676                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2677                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2678                 pbn_b0_2_1843200_200 },
2679         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2680                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2681                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2682                 pbn_b0_4_1843200_200 },
2683         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2684                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2685                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2686                 pbn_b0_8_1843200_200 },
2687
2688         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2689                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2690                 pbn_b2_bt_1_115200 },
2691         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2692                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2693                 pbn_b2_bt_2_115200 },
2694         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2695                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2696                 pbn_b2_bt_4_115200 },
2697         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2698                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2699                 pbn_b2_bt_2_115200 },
2700         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2701                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2702                 pbn_b2_bt_4_115200 },
2703         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2704                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2705                 pbn_b2_8_115200 },
2706         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2707                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2708                 pbn_b2_8_460800 },
2709         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2710                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2711                 pbn_b2_8_115200 },
2712
2713         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2714                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2715                 pbn_b2_bt_2_115200 },
2716         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2717                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2718                 pbn_b2_bt_2_921600 },
2719         /*
2720          * VScom SPCOM800, from sl@s.pl
2721          */
2722         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2723                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2724                 pbn_b2_8_921600 },
2725         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2726                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2727                 pbn_b2_4_921600 },
2728         /* Unknown card - subdevice 0x1584 */
2729         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2730                 PCI_VENDOR_ID_PLX,
2731                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2732                 pbn_b0_4_115200 },
2733         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2734                 PCI_SUBVENDOR_ID_KEYSPAN,
2735                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2736                 pbn_panacom },
2737         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2738                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2739                 pbn_panacom4 },
2740         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2741                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2742                 pbn_panacom2 },
2743         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2744                 PCI_VENDOR_ID_ESDGMBH,
2745                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2746                 pbn_b2_4_115200 },
2747         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2748                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2749                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2750                 pbn_b2_4_460800 },
2751         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2752                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2753                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2754                 pbn_b2_8_460800 },
2755         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2756                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2757                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2758                 pbn_b2_16_460800 },
2759         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2760                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2761                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2762                 pbn_b2_16_460800 },
2763         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2764                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2765                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2766                 pbn_b2_4_460800 },
2767         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2768                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2769                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2770                 pbn_b2_8_460800 },
2771         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2772                 PCI_SUBVENDOR_ID_EXSYS,
2773                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2774                 pbn_exsys_4055 },
2775         /*
2776          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2777          * (Exoray@isys.ca)
2778          */
2779         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2780                 0x10b5, 0x106a, 0, 0,
2781                 pbn_plx_romulus },
2782         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2783                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2784                 pbn_b1_4_115200 },
2785         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2786                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2787                 pbn_b1_2_115200 },
2788         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2789                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2790                 pbn_b1_8_115200 },
2791         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2792                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2793                 pbn_b1_8_115200 },
2794         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2795                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2796                 0, 0,
2797                 pbn_b0_4_921600 },
2798         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2799                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2800                 0, 0,
2801                 pbn_b0_4_1152000 },
2802
2803                 /*
2804                  * The below card is a little controversial since it is the
2805                  * subject of a PCI vendor/device ID clash.  (See
2806                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2807                  * For now just used the hex ID 0x950a.
2808                  */
2809         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2810                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2811                 pbn_b0_2_115200 },
2812         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2813                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2814                 pbn_b0_2_1130000 },
2815         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2816                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2817                 pbn_b0_1_921600 },
2818         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2819                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2820                 pbn_b0_4_115200 },
2821         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2822                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2823                 pbn_b0_bt_2_921600 },
2824
2825         /*
2826          * Oxford Semiconductor Inc. Tornado PCI express device range.
2827          */
2828         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
2829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2830                 pbn_b0_1_4000000 },
2831         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
2832                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2833                 pbn_b0_1_4000000 },
2834         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
2835                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2836                 pbn_oxsemi_1_4000000 },
2837         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
2838                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2839                 pbn_oxsemi_1_4000000 },
2840         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
2841                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2842                 pbn_b0_1_4000000 },
2843         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
2844                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2845                 pbn_b0_1_4000000 },
2846         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
2847                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2848                 pbn_oxsemi_1_4000000 },
2849         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
2850                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2851                 pbn_oxsemi_1_4000000 },
2852         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
2853                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2854                 pbn_b0_1_4000000 },
2855         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
2856                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2857                 pbn_b0_1_4000000 },
2858         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
2859                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2860                 pbn_b0_1_4000000 },
2861         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
2862                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2863                 pbn_b0_1_4000000 },
2864         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
2865                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2866                 pbn_oxsemi_2_4000000 },
2867         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
2868                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2869                 pbn_oxsemi_2_4000000 },
2870         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
2871                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2872                 pbn_oxsemi_4_4000000 },
2873         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
2874                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2875                 pbn_oxsemi_4_4000000 },
2876         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
2877                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2878                 pbn_oxsemi_8_4000000 },
2879         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
2880                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2881                 pbn_oxsemi_8_4000000 },
2882         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
2883                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2884                 pbn_oxsemi_1_4000000 },
2885         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
2886                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2887                 pbn_oxsemi_1_4000000 },
2888         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
2889                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2890                 pbn_oxsemi_1_4000000 },
2891         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
2892                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2893                 pbn_oxsemi_1_4000000 },
2894         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
2895                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2896                 pbn_oxsemi_1_4000000 },
2897         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
2898                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2899                 pbn_oxsemi_1_4000000 },
2900         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
2901                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2902                 pbn_oxsemi_1_4000000 },
2903         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
2904                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2905                 pbn_oxsemi_1_4000000 },
2906         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
2907                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2908                 pbn_oxsemi_1_4000000 },
2909         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
2910                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2911                 pbn_oxsemi_1_4000000 },
2912         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
2913                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2914                 pbn_oxsemi_1_4000000 },
2915         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
2916                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2917                 pbn_oxsemi_1_4000000 },
2918         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
2919                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2920                 pbn_oxsemi_1_4000000 },
2921         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
2922                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2923                 pbn_oxsemi_1_4000000 },
2924         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
2925                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2926                 pbn_oxsemi_1_4000000 },
2927         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
2928                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2929                 pbn_oxsemi_1_4000000 },
2930         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
2931                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2932                 pbn_oxsemi_1_4000000 },
2933         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
2934                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2935                 pbn_oxsemi_1_4000000 },
2936         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
2937                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2938                 pbn_oxsemi_1_4000000 },
2939         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
2940                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2941                 pbn_oxsemi_1_4000000 },
2942         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
2943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2944                 pbn_oxsemi_1_4000000 },
2945         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
2946                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2947                 pbn_oxsemi_1_4000000 },
2948         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
2949                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2950                 pbn_oxsemi_1_4000000 },
2951         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
2952                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2953                 pbn_oxsemi_1_4000000 },
2954         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
2955                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2956                 pbn_oxsemi_1_4000000 },
2957         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
2958                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2959                 pbn_oxsemi_1_4000000 },
2960         /*
2961          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2962          */
2963         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2964                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2965                 pbn_oxsemi_1_4000000 },
2966         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2967                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2968                 pbn_oxsemi_2_4000000 },
2969         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2970                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2971                 pbn_oxsemi_4_4000000 },
2972         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2973                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2974                 pbn_oxsemi_8_4000000 },
2975         /*
2976          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2977          * from skokodyn@yahoo.com
2978          */
2979         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2980                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2981                 pbn_sbsxrsio },
2982         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2983                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2984                 pbn_sbsxrsio },
2985         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2986                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2987                 pbn_sbsxrsio },
2988         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2989                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2990                 pbn_sbsxrsio },
2991
2992         /*
2993          * Digitan DS560-558, from jimd@esoft.com
2994          */
2995         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2996                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2997                 pbn_b1_1_115200 },
2998
2999         /*
3000          * Titan Electronic cards
3001          *  The 400L and 800L have a custom setup quirk.
3002          */
3003         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3004                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3005                 pbn_b0_1_921600 },
3006         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3007                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3008                 pbn_b0_2_921600 },
3009         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3011                 pbn_b0_4_921600 },
3012         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3013                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3014                 pbn_b0_4_921600 },
3015         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3016                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3017                 pbn_b1_1_921600 },
3018         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3019                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3020                 pbn_b1_bt_2_921600 },
3021         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3022                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3023                 pbn_b0_bt_4_921600 },
3024         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3025                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3026                 pbn_b0_bt_8_921600 },
3027
3028         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3029                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3030                 pbn_b2_1_460800 },
3031         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3032                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3033                 pbn_b2_1_460800 },
3034         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3035                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3036                 pbn_b2_1_460800 },
3037         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3038                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3039                 pbn_b2_bt_2_921600 },
3040         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3041                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3042                 pbn_b2_bt_2_921600 },
3043         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3044                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3045                 pbn_b2_bt_2_921600 },
3046         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3047                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3048                 pbn_b2_bt_4_921600 },
3049         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3050                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3051                 pbn_b2_bt_4_921600 },
3052         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3053                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3054                 pbn_b2_bt_4_921600 },
3055         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3056                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3057                 pbn_b0_1_921600 },
3058         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3059                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3060                 pbn_b0_1_921600 },
3061         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3062                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3063                 pbn_b0_1_921600 },
3064         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3065                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3066                 pbn_b0_bt_2_921600 },
3067         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3068                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3069                 pbn_b0_bt_2_921600 },
3070         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3071                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3072                 pbn_b0_bt_2_921600 },
3073         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3074                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3075                 pbn_b0_bt_4_921600 },
3076         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3077                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3078                 pbn_b0_bt_4_921600 },
3079         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3080                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3081                 pbn_b0_bt_4_921600 },
3082         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3083                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3084                 pbn_b0_bt_8_921600 },
3085         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3086                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3087                 pbn_b0_bt_8_921600 },
3088         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3089                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3090                 pbn_b0_bt_8_921600 },
3091
3092         /*
3093          * Computone devices submitted by Doug McNash dmcnash@computone.com
3094          */
3095         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3096                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3097                 0, 0, pbn_computone_4 },
3098         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3099                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3100                 0, 0, pbn_computone_8 },
3101         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3102                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3103                 0, 0, pbn_computone_6 },
3104
3105         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3107                 pbn_oxsemi },
3108         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3109                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3110                 pbn_b0_bt_1_921600 },
3111
3112         /*
3113          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3114          */
3115         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3117                 pbn_b0_bt_8_115200 },
3118         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3119                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3120                 pbn_b0_bt_8_115200 },
3121
3122         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3123                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3124                 pbn_b0_bt_2_115200 },
3125         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3126                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3127                 pbn_b0_bt_2_115200 },
3128         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3129                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3130                 pbn_b0_bt_2_115200 },
3131         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3132                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3133                 pbn_b0_bt_4_460800 },
3134         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3135                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3136                 pbn_b0_bt_4_460800 },
3137         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3138                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3139                 pbn_b0_bt_2_460800 },
3140         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3141                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3142                 pbn_b0_bt_2_460800 },
3143         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3144                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3145                 pbn_b0_bt_2_460800 },
3146         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3147                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3148                 pbn_b0_bt_1_115200 },
3149         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3150                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3151                 pbn_b0_bt_1_460800 },
3152
3153         /*
3154          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3155          * Cards are identified by their subsystem vendor IDs, which
3156          * (in hex) match the model number.
3157          *
3158          * Note that JC140x are RS422/485 cards which require ox950
3159          * ACR = 0x10, and as such are not currently fully supported.
3160          */
3161         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3162                 0x1204, 0x0004, 0, 0,
3163                 pbn_b0_4_921600 },
3164         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3165                 0x1208, 0x0004, 0, 0,
3166                 pbn_b0_4_921600 },
3167 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3168                 0x1402, 0x0002, 0, 0,
3169                 pbn_b0_2_921600 }, */
3170 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3171                 0x1404, 0x0004, 0, 0,
3172                 pbn_b0_4_921600 }, */
3173         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3174                 0x1208, 0x0004, 0, 0,
3175                 pbn_b0_4_921600 },
3176
3177         /*
3178          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3179          */
3180         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3182                 pbn_b1_1_1382400 },
3183
3184         /*
3185          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3186          */
3187         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3188                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3189                 pbn_b1_1_1382400 },
3190
3191         /*
3192          * RAStel 2 port modem, gerg@moreton.com.au
3193          */
3194         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3195                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3196                 pbn_b2_bt_2_115200 },
3197
3198         /*
3199          * EKF addition for i960 Boards form EKF with serial port
3200          */
3201         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3202                 0xE4BF, PCI_ANY_ID, 0, 0,
3203                 pbn_intel_i960 },
3204
3205         /*
3206          * Xircom Cardbus/Ethernet combos
3207          */
3208         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3209                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3210                 pbn_b0_1_115200 },
3211         /*
3212          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3213          */
3214         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3215                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3216                 pbn_b0_1_115200 },
3217
3218         /*
3219          * Untested PCI modems, sent in from various folks...
3220          */
3221
3222         /*
3223          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3224          */
3225         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3226                 0x1048, 0x1500, 0, 0,
3227                 pbn_b1_1_115200 },
3228
3229         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3230                 0xFF00, 0, 0, 0,
3231                 pbn_sgi_ioc3 },
3232
3233         /*
3234          * HP Diva card
3235          */
3236         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3237                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3238                 pbn_b1_1_115200 },
3239         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3240                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3241                 pbn_b0_5_115200 },
3242         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3243                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244                 pbn_b2_1_115200 },
3245
3246         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248                 pbn_b3_2_115200 },
3249         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251                 pbn_b3_4_115200 },
3252         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254                 pbn_b3_8_115200 },
3255
3256         /*
3257          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3258          */
3259         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3260                 PCI_ANY_ID, PCI_ANY_ID,
3261                 0,
3262                 0, pbn_exar_XR17C152 },
3263         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3264                 PCI_ANY_ID, PCI_ANY_ID,
3265                 0,
3266                 0, pbn_exar_XR17C154 },
3267         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3268                 PCI_ANY_ID, PCI_ANY_ID,
3269                 0,
3270                 0, pbn_exar_XR17C158 },
3271
3272         /*
3273          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3274          */
3275         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3276                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3277                 pbn_b0_1_115200 },
3278         /*
3279          * ITE
3280          */
3281         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3282                 PCI_ANY_ID, PCI_ANY_ID,
3283                 0, 0,
3284                 pbn_b1_bt_1_115200 },
3285
3286         /*
3287          * IntaShield IS-200
3288          */
3289         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3291                 pbn_b2_2_115200 },
3292         /*
3293          * IntaShield IS-400
3294          */
3295         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3297                 pbn_b2_4_115200 },
3298         /*
3299          * Perle PCI-RAS cards
3300          */
3301         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3302                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3303                 0, 0, pbn_b2_4_921600 },
3304         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3305                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3306                 0, 0, pbn_b2_8_921600 },
3307
3308         /*
3309          * Mainpine series cards: Fairly standard layout but fools
3310          * parts of the autodetect in some cases and uses otherwise
3311          * unmatched communications subclasses in the PCI Express case
3312          */
3313
3314         {       /* RockForceDUO */
3315                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3316                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3317                 0, 0, pbn_b0_2_115200 },
3318         {       /* RockForceQUATRO */
3319                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3320                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3321                 0, 0, pbn_b0_4_115200 },
3322         {       /* RockForceDUO+ */
3323                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3324                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3325                 0, 0, pbn_b0_2_115200 },
3326         {       /* RockForceQUATRO+ */
3327                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3328                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3329                 0, 0, pbn_b0_4_115200 },
3330         {       /* RockForce+ */
3331                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3332                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3333                 0, 0, pbn_b0_2_115200 },
3334         {       /* RockForce+ */
3335                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3336                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3337                 0, 0, pbn_b0_4_115200 },
3338         {       /* RockForceOCTO+ */
3339                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3340                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3341                 0, 0, pbn_b0_8_115200 },
3342         {       /* RockForceDUO+ */
3343                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3344                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3345                 0, 0, pbn_b0_2_115200 },
3346         {       /* RockForceQUARTRO+ */
3347                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3348                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3349                 0, 0, pbn_b0_4_115200 },
3350         {       /* RockForceOCTO+ */
3351                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3352                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3353                 0, 0, pbn_b0_8_115200 },
3354         {       /* RockForceD1 */
3355                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3356                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3357                 0, 0, pbn_b0_1_115200 },
3358         {       /* RockForceF1 */
3359                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3360                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3361                 0, 0, pbn_b0_1_115200 },
3362         {       /* RockForceD2 */
3363                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3364                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3365                 0, 0, pbn_b0_2_115200 },
3366         {       /* RockForceF2 */
3367                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3368                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3369                 0, 0, pbn_b0_2_115200 },
3370         {       /* RockForceD4 */
3371                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3372                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3373                 0, 0, pbn_b0_4_115200 },
3374         {       /* RockForceF4 */
3375                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3376                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3377                 0, 0, pbn_b0_4_115200 },
3378         {       /* RockForceD8 */
3379                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3380                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3381                 0, 0, pbn_b0_8_115200 },
3382         {       /* RockForceF8 */
3383                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3384                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3385                 0, 0, pbn_b0_8_115200 },
3386         {       /* IQ Express D1 */
3387                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3388                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3389                 0, 0, pbn_b0_1_115200 },
3390         {       /* IQ Express F1 */
3391                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3392                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3393                 0, 0, pbn_b0_1_115200 },
3394         {       /* IQ Express D2 */
3395                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3396                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3397                 0, 0, pbn_b0_2_115200 },
3398         {       /* IQ Express F2 */
3399                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3400                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3401                 0, 0, pbn_b0_2_115200 },
3402         {       /* IQ Express D4 */
3403                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3404                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3405                 0, 0, pbn_b0_4_115200 },
3406         {       /* IQ Express F4 */
3407                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3408                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3409                 0, 0, pbn_b0_4_115200 },
3410         {       /* IQ Express D8 */
3411                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3412                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3413                 0, 0, pbn_b0_8_115200 },
3414         {       /* IQ Express F8 */
3415                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3416                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3417                 0, 0, pbn_b0_8_115200 },
3418
3419
3420         /*
3421          * PA Semi PA6T-1682M on-chip UART
3422          */
3423         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3424                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425                 pbn_pasemi_1682M },
3426
3427         /*
3428          * National Instruments
3429          */
3430         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3431                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3432                 pbn_b1_16_115200 },
3433         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3434                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3435                 pbn_b1_8_115200 },
3436         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3437                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3438                 pbn_b1_bt_4_115200 },
3439         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3440                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3441                 pbn_b1_bt_2_115200 },
3442         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3443                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3444                 pbn_b1_bt_4_115200 },
3445         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3446                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3447                 pbn_b1_bt_2_115200 },
3448         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3449                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3450                 pbn_b1_16_115200 },
3451         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3452                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3453                 pbn_b1_8_115200 },
3454         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3455                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3456                 pbn_b1_bt_4_115200 },
3457         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3458                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3459                 pbn_b1_bt_2_115200 },
3460         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3461                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3462                 pbn_b1_bt_4_115200 },
3463         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3464                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3465                 pbn_b1_bt_2_115200 },
3466         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3467                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3468                 pbn_ni8430_2 },
3469         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3471                 pbn_ni8430_2 },
3472         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3474                 pbn_ni8430_4 },
3475         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3477                 pbn_ni8430_4 },
3478         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480                 pbn_ni8430_8 },
3481         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483                 pbn_ni8430_8 },
3484         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486                 pbn_ni8430_16 },
3487         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3489                 pbn_ni8430_16 },
3490         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492                 pbn_ni8430_2 },
3493         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495                 pbn_ni8430_2 },
3496         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498                 pbn_ni8430_4 },
3499         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3501                 pbn_ni8430_4 },
3502
3503         /*
3504         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3505         */
3506         {       PCI_VENDOR_ID_ADDIDATA,
3507                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3508                 PCI_ANY_ID,
3509                 PCI_ANY_ID,
3510                 0,
3511                 0,
3512                 pbn_b0_4_115200 },
3513
3514         {       PCI_VENDOR_ID_ADDIDATA,
3515                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3516                 PCI_ANY_ID,
3517                 PCI_ANY_ID,
3518                 0,
3519                 0,
3520                 pbn_b0_2_115200 },
3521
3522         {       PCI_VENDOR_ID_ADDIDATA,
3523                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3524                 PCI_ANY_ID,
3525                 PCI_ANY_ID,
3526                 0,
3527                 0,
3528                 pbn_b0_1_115200 },
3529
3530         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3531                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3532                 PCI_ANY_ID,
3533                 PCI_ANY_ID,
3534                 0,
3535                 0,
3536                 pbn_b1_8_115200 },
3537
3538         {       PCI_VENDOR_ID_ADDIDATA,
3539                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3540                 PCI_ANY_ID,
3541                 PCI_ANY_ID,
3542                 0,
3543                 0,
3544                 pbn_b0_4_115200 },
3545
3546         {       PCI_VENDOR_ID_ADDIDATA,
3547                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3548                 PCI_ANY_ID,
3549                 PCI_ANY_ID,
3550                 0,
3551                 0,
3552                 pbn_b0_2_115200 },
3553
3554         {       PCI_VENDOR_ID_ADDIDATA,
3555                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3556                 PCI_ANY_ID,
3557                 PCI_ANY_ID,
3558                 0,
3559                 0,
3560                 pbn_b0_1_115200 },
3561
3562         {       PCI_VENDOR_ID_ADDIDATA,
3563                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3564                 PCI_ANY_ID,
3565                 PCI_ANY_ID,
3566                 0,
3567                 0,
3568                 pbn_b0_4_115200 },
3569
3570         {       PCI_VENDOR_ID_ADDIDATA,
3571                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3572                 PCI_ANY_ID,
3573                 PCI_ANY_ID,
3574                 0,
3575                 0,
3576                 pbn_b0_2_115200 },
3577
3578         {       PCI_VENDOR_ID_ADDIDATA,
3579                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3580                 PCI_ANY_ID,
3581                 PCI_ANY_ID,
3582                 0,
3583                 0,
3584                 pbn_b0_1_115200 },
3585
3586         {       PCI_VENDOR_ID_ADDIDATA,
3587                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3588                 PCI_ANY_ID,
3589                 PCI_ANY_ID,
3590                 0,
3591                 0,
3592                 pbn_b0_8_115200 },
3593
3594         {       PCI_VENDOR_ID_ADDIDATA,
3595                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3596                 PCI_ANY_ID,
3597                 PCI_ANY_ID,
3598                 0,
3599                 0,
3600                 pbn_ADDIDATA_PCIe_4_3906250 },
3601
3602         {       PCI_VENDOR_ID_ADDIDATA,
3603                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3604                 PCI_ANY_ID,
3605                 PCI_ANY_ID,
3606                 0,
3607                 0,
3608                 pbn_ADDIDATA_PCIe_2_3906250 },
3609
3610         {       PCI_VENDOR_ID_ADDIDATA,
3611                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3612                 PCI_ANY_ID,
3613                 PCI_ANY_ID,
3614                 0,
3615                 0,
3616                 pbn_ADDIDATA_PCIe_1_3906250 },
3617
3618         {       PCI_VENDOR_ID_ADDIDATA,
3619                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3620                 PCI_ANY_ID,
3621                 PCI_ANY_ID,
3622                 0,
3623                 0,
3624                 pbn_ADDIDATA_PCIe_8_3906250 },
3625
3626         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3627                 PCI_VENDOR_ID_IBM, 0x0299,
3628                 0, 0, pbn_b0_bt_2_115200 },
3629
3630         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3631                 0xA000, 0x1000,
3632                 0, 0, pbn_b0_1_115200 },
3633
3634         /*
3635          * These entries match devices with class COMMUNICATION_SERIAL,
3636          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3637          */
3638         {       PCI_ANY_ID, PCI_ANY_ID,
3639                 PCI_ANY_ID, PCI_ANY_ID,
3640                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3641                 0xffff00, pbn_default },
3642         {       PCI_ANY_ID, PCI_ANY_ID,
3643                 PCI_ANY_ID, PCI_ANY_ID,
3644                 PCI_CLASS_COMMUNICATION_MODEM << 8,
3645                 0xffff00, pbn_default },
3646         {       PCI_ANY_ID, PCI_ANY_ID,
3647                 PCI_ANY_ID, PCI_ANY_ID,
3648                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3649                 0xffff00, pbn_default },
3650         { 0, }
3651 };
3652
3653 static struct pci_driver serial_pci_driver = {
3654         .name           = "serial",
3655         .probe          = pciserial_init_one,
3656         .remove         = __devexit_p(pciserial_remove_one),
3657 #ifdef CONFIG_PM
3658         .suspend        = pciserial_suspend_one,
3659         .resume         = pciserial_resume_one,
3660 #endif
3661         .id_table       = serial_pci_tbl,
3662 };
3663
3664 static int __init serial8250_pci_init(void)
3665 {
3666         return pci_register_driver(&serial_pci_driver);
3667 }
3668
3669 static void __exit serial8250_pci_exit(void)
3670 {
3671         pci_unregister_driver(&serial_pci_driver);
3672 }
3673
3674 module_init(serial8250_pci_init);
3675 module_exit(serial8250_pci_exit);
3676
3677 MODULE_LICENSE("GPL");
3678 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3679 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);