1 /* sun_esp.c: ESP front-end for Sparc SBUS systems.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/delay.h>
9 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/dma-mapping.h>
14 #include <linux/of_device.h>
15 #include <linux/gfp.h>
21 #include <scsi/scsi_host.h>
25 #define DRV_MODULE_NAME "sun_esp"
26 #define PFX DRV_MODULE_NAME ": "
27 #define DRV_VERSION "1.100"
28 #define DRV_MODULE_RELDATE "August 27, 2008"
30 #define dma_read32(REG) \
31 sbus_readl(esp->dma_regs + (REG))
32 #define dma_write32(VAL, REG) \
33 sbus_writel((VAL), esp->dma_regs + (REG))
35 /* DVMA chip revisions */
46 static int esp_sbus_setup_dma(struct esp *esp, struct platform_device *dma_of)
50 esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
51 resource_size(&dma_of->resource[0]),
56 switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
58 esp->dmarev = dvmarev0;
61 esp->dmarev = dvmaesc1;
64 esp->dmarev = dvmarev1;
67 esp->dmarev = dvmarev2;
70 esp->dmarev = dvmahme;
73 esp->dmarev = dvmarevplus;
81 static int esp_sbus_map_regs(struct esp *esp, int hme)
83 struct platform_device *op = to_platform_device(esp->dev);
86 /* On HME, two reg sets exist, first is DVMA,
87 * second is ESP registers.
90 res = &op->resource[1];
92 res = &op->resource[0];
94 esp->regs = of_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
101 static int esp_sbus_map_command_block(struct esp *esp)
103 esp->command_block = dma_alloc_coherent(esp->dev, 16,
104 &esp->command_block_dma,
106 if (!esp->command_block)
111 static int esp_sbus_register_irq(struct esp *esp)
113 struct Scsi_Host *host = esp->host;
114 struct platform_device *op = to_platform_device(esp->dev);
116 host->irq = op->archdata.irqs[0];
117 return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
120 static void esp_get_scsi_id(struct esp *esp, struct platform_device *espdma)
122 struct platform_device *op = to_platform_device(esp->dev);
123 struct device_node *dp;
125 dp = op->dev.of_node;
126 esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
127 if (esp->scsi_id != 0xff)
130 esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
131 if (esp->scsi_id != 0xff)
134 esp->scsi_id = of_getintprop_default(espdma->dev.of_node,
135 "scsi-initiator-id", 7);
138 esp->host->this_id = esp->scsi_id;
139 esp->scsi_id_mask = (1 << esp->scsi_id);
142 static void esp_get_differential(struct esp *esp)
144 struct platform_device *op = to_platform_device(esp->dev);
145 struct device_node *dp;
147 dp = op->dev.of_node;
148 if (of_find_property(dp, "differential", NULL))
149 esp->flags |= ESP_FLAG_DIFFERENTIAL;
151 esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
154 static void esp_get_clock_params(struct esp *esp)
156 struct platform_device *op = to_platform_device(esp->dev);
157 struct device_node *bus_dp, *dp;
160 dp = op->dev.of_node;
163 fmhz = of_getintprop_default(dp, "clock-frequency", 0);
165 fmhz = of_getintprop_default(bus_dp, "clock-frequency", 0);
170 static void esp_get_bursts(struct esp *esp, struct platform_device *dma_of)
172 struct device_node *dma_dp = dma_of->dev.of_node;
173 struct platform_device *op = to_platform_device(esp->dev);
174 struct device_node *dp;
177 dp = op->dev.of_node;
178 bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
179 val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
183 val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff);
187 if (bursts == 0xff ||
188 (bursts & DMA_BURST16) == 0 ||
189 (bursts & DMA_BURST32) == 0)
190 bursts = (DMA_BURST32 - 1);
192 esp->bursts = bursts;
195 static void esp_sbus_get_props(struct esp *esp, struct platform_device *espdma)
197 esp_get_scsi_id(esp, espdma);
198 esp_get_differential(esp);
199 esp_get_clock_params(esp);
200 esp_get_bursts(esp, espdma);
203 static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
205 sbus_writeb(val, esp->regs + (reg * 4UL));
208 static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
210 return sbus_readb(esp->regs + (reg * 4UL));
213 static dma_addr_t sbus_esp_map_single(struct esp *esp, void *buf,
216 return dma_map_single(esp->dev, buf, sz, dir);
219 static int sbus_esp_map_sg(struct esp *esp, struct scatterlist *sg,
222 return dma_map_sg(esp->dev, sg, num_sg, dir);
225 static void sbus_esp_unmap_single(struct esp *esp, dma_addr_t addr,
228 dma_unmap_single(esp->dev, addr, sz, dir);
231 static void sbus_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
234 dma_unmap_sg(esp->dev, sg, num_sg, dir);
237 static int sbus_esp_irq_pending(struct esp *esp)
239 if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
244 static void sbus_esp_reset_dma(struct esp *esp)
246 int can_do_burst16, can_do_burst32, can_do_burst64;
247 int can_do_sbus64, lim;
248 struct platform_device *op = to_platform_device(esp->dev);
251 can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
252 can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
255 if (sbus_can_dma_64bit())
257 if (sbus_can_burst64())
258 can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;
260 /* Put the DVMA into a known state. */
261 if (esp->dmarev != dvmahme) {
262 val = dma_read32(DMA_CSR);
263 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
264 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
266 switch (esp->dmarev) {
268 dma_write32(DMA_RESET_FAS366, DMA_CSR);
269 dma_write32(DMA_RST_SCSI, DMA_CSR);
271 esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS |
272 DMA_SCSI_DISAB | DMA_INT_ENAB);
274 esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
278 esp->prev_hme_dmacsr |= DMA_BRST64;
279 else if (can_do_burst32)
280 esp->prev_hme_dmacsr |= DMA_BRST32;
283 esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;
284 sbus_set_sbus64(&op->dev, esp->bursts);
288 while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
290 printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
292 esp->host->unique_id);
298 dma_write32(0, DMA_CSR);
299 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
301 dma_write32(0, DMA_ADDR);
305 if (esp->rev != ESP100) {
306 val = dma_read32(DMA_CSR);
307 dma_write32(val | DMA_3CLKS, DMA_CSR);
312 val = dma_read32(DMA_CSR);
315 if (can_do_burst32) {
319 dma_write32(val, DMA_CSR);
323 val = dma_read32(DMA_CSR);
324 val |= DMA_ADD_ENABLE;
325 val &= ~DMA_BCNT_ENAB;
326 if (!can_do_burst32 && can_do_burst16) {
327 val |= DMA_ESC_BURST;
329 val &= ~(DMA_ESC_BURST);
331 dma_write32(val, DMA_CSR);
338 /* Enable interrupts. */
339 val = dma_read32(DMA_CSR);
340 dma_write32(val | DMA_INT_ENAB, DMA_CSR);
343 static void sbus_esp_dma_drain(struct esp *esp)
348 if (esp->dmarev == dvmahme)
351 csr = dma_read32(DMA_CSR);
352 if (!(csr & DMA_FIFO_ISDRAIN))
355 if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
356 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
359 while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
361 printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
362 esp->host->unique_id);
369 static void sbus_esp_dma_invalidate(struct esp *esp)
371 if (esp->dmarev == dvmahme) {
372 dma_write32(DMA_RST_SCSI, DMA_CSR);
374 esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr |
375 (DMA_PARITY_OFF | DMA_2CLKS |
376 DMA_SCSI_DISAB | DMA_INT_ENAB)) &
377 ~(DMA_ST_WRITE | DMA_ENABLE));
379 dma_write32(0, DMA_CSR);
380 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
382 /* This is necessary to avoid having the SCSI channel
383 * engine lock up on us.
385 dma_write32(0, DMA_ADDR);
391 while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
393 printk(KERN_ALERT PFX "esp%d: DMA will not "
394 "invalidate!\n", esp->host->unique_id);
400 val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
402 dma_write32(val, DMA_CSR);
403 val &= ~DMA_FIFO_INV;
404 dma_write32(val, DMA_CSR);
408 static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
409 u32 dma_count, int write, u8 cmd)
413 BUG_ON(!(cmd & ESP_CMD_DMA));
415 sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
416 sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
417 if (esp->rev == FASHME) {
418 sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
419 sbus_esp_write8(esp, 0, FAS_RHI);
421 scsi_esp_cmd(esp, cmd);
423 csr = esp->prev_hme_dmacsr;
424 csr |= DMA_SCSI_DISAB | DMA_ENABLE;
428 csr &= ~DMA_ST_WRITE;
429 esp->prev_hme_dmacsr = csr;
431 dma_write32(dma_count, DMA_COUNT);
432 dma_write32(addr, DMA_ADDR);
433 dma_write32(csr, DMA_CSR);
435 csr = dma_read32(DMA_CSR);
440 csr &= ~DMA_ST_WRITE;
441 dma_write32(csr, DMA_CSR);
442 if (esp->dmarev == dvmaesc1) {
443 u32 end = PAGE_ALIGN(addr + dma_count + 16U);
444 dma_write32(end - addr, DMA_COUNT);
446 dma_write32(addr, DMA_ADDR);
448 scsi_esp_cmd(esp, cmd);
453 static int sbus_esp_dma_error(struct esp *esp)
455 u32 csr = dma_read32(DMA_CSR);
457 if (csr & DMA_HNDL_ERROR)
463 static const struct esp_driver_ops sbus_esp_ops = {
464 .esp_write8 = sbus_esp_write8,
465 .esp_read8 = sbus_esp_read8,
466 .map_single = sbus_esp_map_single,
467 .map_sg = sbus_esp_map_sg,
468 .unmap_single = sbus_esp_unmap_single,
469 .unmap_sg = sbus_esp_unmap_sg,
470 .irq_pending = sbus_esp_irq_pending,
471 .reset_dma = sbus_esp_reset_dma,
472 .dma_drain = sbus_esp_dma_drain,
473 .dma_invalidate = sbus_esp_dma_invalidate,
474 .send_dma_cmd = sbus_esp_send_dma_cmd,
475 .dma_error = sbus_esp_dma_error,
478 static int esp_sbus_probe_one(struct platform_device *op,
479 struct platform_device *espdma, int hme)
481 struct scsi_host_template *tpnt = &scsi_esp_template;
482 struct Scsi_Host *host;
486 host = scsi_host_alloc(tpnt, sizeof(struct esp));
492 host->max_id = (hme ? 16 : 8);
493 esp = shost_priv(host);
497 esp->ops = &sbus_esp_ops;
500 esp->flags |= ESP_FLAG_WIDE_CAPABLE;
502 err = esp_sbus_setup_dma(esp, espdma);
506 err = esp_sbus_map_regs(esp, hme);
510 err = esp_sbus_map_command_block(esp);
512 goto fail_unmap_regs;
514 err = esp_sbus_register_irq(esp);
516 goto fail_unmap_command_block;
518 esp_sbus_get_props(esp, espdma);
520 /* Before we try to touch the ESP chip, ESC1 dma can
521 * come up with the reset bit set, so make sure that
524 if (esp->dmarev == dvmaesc1) {
525 u32 val = dma_read32(DMA_CSR);
527 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
530 dev_set_drvdata(&op->dev, esp);
532 err = scsi_esp_register(esp, &op->dev);
539 free_irq(host->irq, esp);
540 fail_unmap_command_block:
541 dma_free_coherent(&op->dev, 16,
543 esp->command_block_dma);
545 of_iounmap(&op->resource[(hme ? 1 : 0)], esp->regs, SBUS_ESP_REG_SIZE);
552 static int esp_sbus_probe(struct platform_device *op)
554 struct device_node *dma_node = NULL;
555 struct device_node *dp = op->dev.of_node;
556 struct platform_device *dma_of = NULL;
561 (!strcmp(dp->parent->name, "espdma") ||
562 !strcmp(dp->parent->name, "dma")))
563 dma_node = dp->parent;
564 else if (!strcmp(dp->name, "SUNW,fas")) {
565 dma_node = op->dev.of_node;
569 dma_of = of_find_device_by_node(dma_node);
573 ret = esp_sbus_probe_one(op, dma_of, hme);
575 put_device(&dma_of->dev);
580 static int esp_sbus_remove(struct platform_device *op)
582 struct esp *esp = dev_get_drvdata(&op->dev);
583 struct platform_device *dma_of = esp->dma;
584 unsigned int irq = esp->host->irq;
588 scsi_esp_unregister(esp);
590 /* Disable interrupts. */
591 val = dma_read32(DMA_CSR);
592 dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
596 is_hme = (esp->dmarev == dvmahme);
598 dma_free_coherent(&op->dev, 16,
600 esp->command_block_dma);
601 of_iounmap(&op->resource[(is_hme ? 1 : 0)], esp->regs,
603 of_iounmap(&dma_of->resource[0], esp->dma_regs,
604 resource_size(&dma_of->resource[0]));
606 scsi_host_put(esp->host);
608 dev_set_drvdata(&op->dev, NULL);
610 put_device(&dma_of->dev);
615 static const struct of_device_id esp_match[] = {
627 MODULE_DEVICE_TABLE(of, esp_match);
629 static struct platform_driver esp_sbus_driver = {
632 .of_match_table = esp_match,
634 .probe = esp_sbus_probe,
635 .remove = esp_sbus_remove,
638 static int __init sunesp_init(void)
640 return platform_driver_register(&esp_sbus_driver);
643 static void __exit sunesp_exit(void)
645 platform_driver_unregister(&esp_sbus_driver);
648 MODULE_DESCRIPTION("Sun ESP SCSI driver");
649 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
650 MODULE_LICENSE("GPL");
651 MODULE_VERSION(DRV_VERSION);
653 module_init(sunesp_init);
654 module_exit(sunesp_exit);