2 * SuperTrak EX Series Storage Controller driver for Linux
4 * Copyright (C) 2005, 2006 Promise Technology Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 * Ed Lin <promise_linux@promise.com>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/time.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/interrupt.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
29 #include <asm/byteorder.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_tcq.h>
36 #define DRV_NAME "stex"
37 #define ST_DRIVER_VERSION "3.1.0.1"
38 #define ST_VER_MAJOR 3
39 #define ST_VER_MINOR 1
41 #define ST_BUILD_VER 1
44 /* MU register offset */
45 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
46 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
47 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
48 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
49 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
50 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
51 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
52 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
53 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
54 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
56 /* MU register value */
57 MU_INBOUND_DOORBELL_HANDSHAKE = 1,
58 MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
59 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
60 MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
61 MU_INBOUND_DOORBELL_RESET = 16,
63 MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
64 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
65 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
66 MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
67 MU_OUTBOUND_DOORBELL_HASEVENT = 16,
70 MU_STATE_STARTING = 1,
71 MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
72 MU_STATE_SEND_HANDSHAKE_FRAME = 3,
74 MU_STATE_RESETTING = 5,
77 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
78 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
79 MU_HARD_RESET_WAIT = 30000,
82 /* firmware returned values */
83 SRB_STATUS_SUCCESS = 0x01,
84 SRB_STATUS_ERROR = 0x04,
85 SRB_STATUS_BUSY = 0x05,
86 SRB_STATUS_INVALID_REQUEST = 0x06,
87 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
91 TASK_ATTRIBUTE_SIMPLE = 0x0,
92 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
93 TASK_ATTRIBUTE_ORDERED = 0x2,
94 TASK_ATTRIBUTE_ACA = 0x4,
96 /* request count, etc. */
99 /* one message wasted, use MU_MAX_REQUEST+1
100 to handle MU_MAX_REQUEST messages */
101 MU_REQ_COUNT = (MU_MAX_REQUEST + 1),
102 MU_STATUS_COUNT = (MU_MAX_REQUEST + 1),
104 STEX_CDB_LENGTH = MAX_COMMAND_SIZE,
105 REQ_VARIABLE_LEN = 1024,
106 STATUS_VAR_LEN = 128,
107 ST_CAN_QUEUE = MU_MAX_REQUEST,
108 ST_CMD_PER_LUN = MU_MAX_REQUEST,
112 SG_CF_EOT = 0x80, /* end of table */
113 SG_CF_64B = 0x40, /* 64 bit item */
114 SG_CF_HOST = 0x20, /* sg in host memory */
121 PASSTHRU_REQ_TYPE = 0x00000001,
122 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
123 ST_INTERNAL_TIMEOUT = 30,
128 /* vendor specific commands of Promise */
130 SINBAND_MGT_CMD = 0xd9,
132 CONTROLLER_CMD = 0xe1,
133 DEBUGGING_CMD = 0xe2,
136 PASSTHRU_GET_ADAPTER = 0x05,
137 PASSTHRU_GET_DRVVER = 0x10,
139 CTLR_CONFIG_CMD = 0x03,
140 CTLR_SHUTDOWN = 0x0d,
142 CTLR_POWER_STATE_CHANGE = 0x0e,
143 CTLR_POWER_SAVING = 0x01,
145 PASSTHRU_SIGNATURE = 0x4e415041,
146 MGT_CMD_SIGNATURE = 0xba,
150 ST_ADDITIONAL_MEM = 0x200000,
153 /* SCSI inquiry data */
154 typedef struct st_inq {
156 u8 DeviceTypeQualifier :3;
157 u8 DeviceTypeModifier :7;
158 u8 RemovableMedia :1;
160 u8 ResponseDataFormat :4;
170 u8 LinkedCommands :1;
174 u8 RelativeAddressing :1;
177 u8 ProductRevisionLevel[4];
178 u8 VendorSpecific[20];
183 u8 ctrl; /* SG_CF_xxx */
194 struct st_sgitem table[ST_MAX_SG];
197 struct handshake_frame {
198 __le32 rb_phy; /* request payload queue physical address */
200 __le16 req_sz; /* size of each request payload */
201 __le16 req_cnt; /* count of reqs the buffer can hold */
202 __le16 status_sz; /* size of each status payload */
203 __le16 status_cnt; /* count of status the buffer can hold */
204 __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */
206 u8 partner_type; /* who sends this frame */
208 __le32 partner_ver_major;
209 __le32 partner_ver_minor;
210 __le32 partner_ver_oem;
211 __le32 partner_ver_build;
212 __le32 extra_offset; /* NEW */
213 __le32 extra_size; /* NEW */
224 u8 payload_sz; /* payload size in 4-byte, not used */
225 u8 cdb[STEX_CDB_LENGTH];
226 u8 variable[REQ_VARIABLE_LEN];
236 u8 payload_sz; /* payload size in 4-byte */
237 u8 variable[STATUS_VAR_LEN];
252 struct ver_info drv_ver;
253 struct ver_info bios_ver;
282 #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg))
283 #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg))
284 #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
285 #define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ))
286 #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
290 struct scsi_cmnd *cmd;
293 unsigned int sense_bufflen;
302 void __iomem *mmio_base; /* iomapped PCI memory space */
304 dma_addr_t dma_handle;
307 struct Scsi_Host *host;
308 struct pci_dev *pdev;
315 struct status_msg *status_buffer;
316 void *copy_buffer; /* temp buffer for driver-handled commands */
317 struct st_ccb ccb[MU_MAX_REQUEST];
318 struct st_ccb *wait_ccb;
319 wait_queue_head_t waitq;
321 unsigned int mu_status;
324 unsigned int cardtype;
327 static const char console_inq_page[] =
329 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
330 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
331 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
332 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
333 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
334 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
335 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
336 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
339 MODULE_AUTHOR("Ed Lin");
340 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
341 MODULE_LICENSE("GPL");
342 MODULE_VERSION(ST_DRIVER_VERSION);
344 static void stex_gettime(__le32 *time)
347 do_gettimeofday(&tv);
349 *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
350 *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
353 static struct status_msg *stex_get_status(struct st_hba *hba)
355 struct status_msg *status =
356 hba->status_buffer + hba->status_tail;
359 hba->status_tail %= MU_STATUS_COUNT;
364 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
366 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
368 cmd->sense_buffer[0] = 0x70; /* fixed format, current */
369 cmd->sense_buffer[2] = sk;
370 cmd->sense_buffer[7] = 18 - 8; /* additional sense length */
371 cmd->sense_buffer[12] = asc;
372 cmd->sense_buffer[13] = ascq;
375 static void stex_invalid_field(struct scsi_cmnd *cmd,
376 void (*done)(struct scsi_cmnd *))
378 /* "Invalid field in cbd" */
379 stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
383 static struct req_msg *stex_alloc_req(struct st_hba *hba)
385 struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
389 hba->req_head %= MU_REQ_COUNT;
394 static int stex_map_sg(struct st_hba *hba,
395 struct req_msg *req, struct st_ccb *ccb)
397 struct pci_dev *pdev = hba->pdev;
398 struct scsi_cmnd *cmd;
399 dma_addr_t dma_handle;
400 struct scatterlist *src;
401 struct st_sgtable *dst;
405 dst = (struct st_sgtable *)req->variable;
406 dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
407 dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
412 src = (struct scatterlist *) cmd->request_buffer;
413 n_elem = pci_map_sg(pdev, src,
414 cmd->use_sg, cmd->sc_data_direction);
418 ccb->sg_count = n_elem;
419 dst->sg_count = cpu_to_le16((u16)n_elem);
421 for (i = 0; i < n_elem; i++, src++) {
422 dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
424 cpu_to_le32(sg_dma_address(src) & 0xffffffff);
425 dst->table[i].addr_hi =
426 cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
427 dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
429 dst->table[--i].ctrl |= SG_CF_EOT;
433 dma_handle = pci_map_single(pdev, cmd->request_buffer,
434 cmd->request_bufflen, cmd->sc_data_direction);
435 cmd->SCp.dma_handle = dma_handle;
438 dst->sg_count = cpu_to_le16(1);
439 dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
440 dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
441 dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
442 dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
447 static void stex_internal_copy(struct scsi_cmnd *cmd,
448 const void *src, size_t *count, int sg_count, int direction)
452 void *s, *d, *base = NULL;
453 if (*count > cmd->request_bufflen)
454 *count = cmd->request_bufflen;
460 size_t offset = *count - lcount;
462 base = scsi_kmap_atomic_sg(cmd->request_buffer,
463 sg_count, &offset, &len);
470 d = cmd->request_buffer;
472 if (direction == ST_TO_CMD)
479 scsi_kunmap_atomic_sg(base);
483 static int stex_direct_copy(struct scsi_cmnd *cmd,
484 const void *src, size_t count)
486 struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
487 size_t cp_len = count;
491 n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
492 cmd->use_sg, cmd->sc_data_direction);
497 stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
500 pci_unmap_sg(hba->pdev, cmd->request_buffer,
501 cmd->use_sg, cmd->sc_data_direction);
502 return cp_len == count;
505 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
508 size_t count = sizeof(struct st_frame);
510 p = hba->copy_buffer;
511 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
512 memset(p->base, 0, sizeof(u32)*6);
513 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
516 p->drv_ver.major = ST_VER_MAJOR;
517 p->drv_ver.minor = ST_VER_MINOR;
518 p->drv_ver.oem = ST_OEM;
519 p->drv_ver.build = ST_BUILD_VER;
521 p->bus = hba->pdev->bus->number;
522 p->slot = hba->pdev->devfn;
524 p->irq_vec = hba->pdev->irq;
525 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
527 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
529 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
533 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
535 req->tag = cpu_to_le16(tag);
536 req->task_attr = TASK_ATTRIBUTE_SIMPLE;
537 req->task_manage = 0; /* not supported yet */
539 hba->ccb[tag].req = req;
542 writel(hba->req_head, hba->mmio_base + IMR0);
543 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
544 readl(hba->mmio_base + IDBL); /* flush */
548 stex_slave_alloc(struct scsi_device *sdev)
550 /* Cheat: usually extracted from Inquiry data */
551 sdev->tagged_supported = 1;
553 scsi_activate_tcq(sdev, sdev->host->can_queue);
559 stex_slave_config(struct scsi_device *sdev)
561 sdev->use_10_for_rw = 1;
562 sdev->use_10_for_ms = 1;
563 sdev->timeout = 60 * HZ;
564 sdev->tagged_supported = 1;
570 stex_slave_destroy(struct scsi_device *sdev)
572 scsi_deactivate_tcq(sdev, 1);
576 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
579 struct Scsi_Host *host;
583 host = cmd->device->host;
584 id = cmd->device->id;
585 lun = cmd->device->lun;
586 hba = (struct st_hba *) &host->hostdata[0];
588 switch (cmd->cmnd[0]) {
591 static char ms10_caching_page[12] =
592 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
594 page = cmd->cmnd[2] & 0x3f;
595 if (page == 0x8 || page == 0x3f) {
596 stex_direct_copy(cmd, ms10_caching_page,
597 sizeof(ms10_caching_page));
598 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
601 stex_invalid_field(cmd, done);
606 * The shasta firmware does not report actual luns in the
607 * target, so fail the command to force sequential lun scan.
608 * Also, the console device does not support this command.
610 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
611 stex_invalid_field(cmd, done);
616 if (id != host->max_id - 1)
618 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
619 stex_direct_copy(cmd, console_inq_page,
620 sizeof(console_inq_page));
621 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
624 stex_invalid_field(cmd, done);
627 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
628 struct st_drvver ver;
629 ver.major = ST_VER_MAJOR;
630 ver.minor = ST_VER_MINOR;
632 ver.build = ST_BUILD_VER;
633 ver.signature[0] = PASSTHRU_SIGNATURE;
634 ver.console_id = host->max_id - 1;
635 ver.host_no = hba->host->host_no;
636 cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
637 DID_OK << 16 | COMMAND_COMPLETE << 8 :
638 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
646 cmd->scsi_done = done;
648 tag = cmd->request->tag;
650 if (unlikely(tag >= host->can_queue))
651 return SCSI_MLQUEUE_HOST_BUSY;
653 req = stex_alloc_req(hba);
659 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
661 hba->ccb[tag].cmd = cmd;
662 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
663 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
664 hba->ccb[tag].req_type = 0;
666 if (cmd->sc_data_direction != DMA_NONE)
667 stex_map_sg(hba, req, &hba->ccb[tag]);
669 stex_send_cmd(hba, req, tag);
673 static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
675 if (cmd->sc_data_direction != DMA_NONE) {
677 pci_unmap_sg(hba->pdev, cmd->request_buffer,
678 cmd->use_sg, cmd->sc_data_direction);
680 pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
681 cmd->request_bufflen, cmd->sc_data_direction);
685 static void stex_scsi_done(struct st_ccb *ccb)
687 struct scsi_cmnd *cmd = ccb->cmd;
690 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
691 result = ccb->scsi_status;
692 switch (ccb->scsi_status) {
694 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
696 case SAM_STAT_CHECK_CONDITION:
697 result |= DRIVER_SENSE << 24;
700 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
703 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
707 else if (ccb->srb_status & SRB_SEE_SENSE)
708 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
709 else switch (ccb->srb_status) {
710 case SRB_STATUS_SELECTION_TIMEOUT:
711 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
713 case SRB_STATUS_BUSY:
714 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
716 case SRB_STATUS_INVALID_REQUEST:
717 case SRB_STATUS_ERROR:
719 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
723 cmd->result = result;
727 static void stex_copy_data(struct st_ccb *ccb,
728 struct status_msg *resp, unsigned int variable)
730 size_t count = variable;
731 if (resp->scsi_status != SAM_STAT_GOOD) {
732 if (ccb->sense_buffer != NULL)
733 memcpy(ccb->sense_buffer, resp->variable,
734 min(variable, ccb->sense_bufflen));
738 if (ccb->cmd == NULL)
740 stex_internal_copy(ccb->cmd,
741 resp->variable, &count, ccb->sg_count, ST_TO_CMD);
744 static void stex_ys_commands(struct st_hba *hba,
745 struct st_ccb *ccb, struct status_msg *resp)
749 if (ccb->cmd->cmnd[0] == MGT_CMD &&
750 resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
751 ccb->cmd->request_bufflen =
752 le32_to_cpu(*(__le32 *)&resp->variable[0]);
756 if (resp->srb_status != 0)
759 /* determine inquiry command status by DeviceTypeQualifier */
760 if (ccb->cmd->cmnd[0] == INQUIRY &&
761 resp->scsi_status == SAM_STAT_GOOD) {
764 count = STEX_EXTRA_SIZE;
765 stex_internal_copy(ccb->cmd, hba->copy_buffer,
766 &count, ccb->sg_count, ST_FROM_CMD);
767 inq_data = (ST_INQ *)hba->copy_buffer;
768 if (inq_data->DeviceTypeQualifier != 0)
769 ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
771 ccb->srb_status = SRB_STATUS_SUCCESS;
775 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
777 void __iomem *base = hba->mmio_base;
778 struct status_msg *resp;
783 if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
786 /* status payloads */
787 hba->status_head = readl(base + OMR1);
788 if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
789 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
790 pci_name(hba->pdev));
795 * it's not a valid status payload if:
796 * 1. there are no pending requests(e.g. during init stage)
797 * 2. there are some pending requests, but the controller is in
798 * reset status, and its type is not st_yosemite
799 * firmware of st_yosemite in reset status will return pending requests
800 * to driver, so we allow it to pass
802 if (unlikely(hba->out_req_cnt <= 0 ||
803 (hba->mu_status == MU_STATE_RESETTING &&
804 hba->cardtype != st_yosemite))) {
805 hba->status_tail = hba->status_head;
809 while (hba->status_tail != hba->status_head) {
810 resp = stex_get_status(hba);
811 tag = le16_to_cpu(resp->tag);
812 if (unlikely(tag >= hba->host->can_queue)) {
813 printk(KERN_WARNING DRV_NAME
814 "(%s): invalid tag\n", pci_name(hba->pdev));
818 ccb = &hba->ccb[tag];
819 if (hba->wait_ccb == ccb)
820 hba->wait_ccb = NULL;
821 if (unlikely(ccb->req == NULL)) {
822 printk(KERN_WARNING DRV_NAME
823 "(%s): lagging req\n", pci_name(hba->pdev));
828 size = resp->payload_sz * sizeof(u32); /* payload size */
829 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
830 size > sizeof(*resp))) {
831 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
832 pci_name(hba->pdev));
834 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
836 stex_copy_data(ccb, resp, size);
839 ccb->srb_status = resp->srb_status;
840 ccb->scsi_status = resp->scsi_status;
842 if (likely(ccb->cmd != NULL)) {
843 if (hba->cardtype == st_yosemite)
844 stex_ys_commands(hba, ccb, resp);
846 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
847 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
848 stex_controller_info(hba, ccb);
850 stex_unmap_sg(hba, ccb->cmd);
853 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
855 if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
860 if (waitqueue_active(&hba->waitq))
861 wake_up(&hba->waitq);
866 writel(hba->status_head, base + IMR1);
867 readl(base + IMR1); /* flush */
870 static irqreturn_t stex_intr(int irq, void *__hba)
872 struct st_hba *hba = __hba;
873 void __iomem *base = hba->mmio_base;
878 spin_lock_irqsave(hba->host->host_lock, flags);
880 data = readl(base + ODBL);
882 if (data && data != 0xffffffff) {
883 /* clear the interrupt */
884 writel(data, base + ODBL);
885 readl(base + ODBL); /* flush */
886 stex_mu_intr(hba, data);
890 spin_unlock_irqrestore(hba->host->host_lock, flags);
892 return IRQ_RETVAL(handled);
895 static int stex_handshake(struct st_hba *hba)
897 void __iomem *base = hba->mmio_base;
898 struct handshake_frame *h;
899 dma_addr_t status_phys;
901 unsigned long before;
903 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
904 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
907 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
908 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
909 printk(KERN_ERR DRV_NAME
910 "(%s): no handshake signature\n",
911 pci_name(hba->pdev));
921 data = readl(base + OMR1);
922 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
924 if (hba->host->can_queue > data)
925 hba->host->can_queue = data;
928 h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
929 h->rb_phy = cpu_to_le32(hba->dma_handle);
930 h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
931 h->req_sz = cpu_to_le16(sizeof(struct req_msg));
932 h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
933 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
934 h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
935 stex_gettime(&h->hosttime);
936 h->partner_type = HMU_PARTNER_TYPE;
937 if (hba->dma_size > STEX_BUFFER_SIZE) {
938 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
939 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
941 h->extra_offset = h->extra_size = 0;
943 status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
944 writel(status_phys, base + IMR0);
946 writel((status_phys >> 16) >> 16, base + IMR1);
949 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
951 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
952 readl(base + IDBL); /* flush */
956 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
957 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
958 printk(KERN_ERR DRV_NAME
959 "(%s): no signature after handshake frame\n",
960 pci_name(hba->pdev));
967 writel(0, base + IMR0);
969 writel(0, base + OMR0);
971 writel(0, base + IMR1);
973 writel(0, base + OMR1);
974 readl(base + OMR1); /* flush */
975 hba->mu_status = MU_STATE_STARTED;
979 static int stex_abort(struct scsi_cmnd *cmd)
981 struct Scsi_Host *host = cmd->device->host;
982 struct st_hba *hba = (struct st_hba *)host->hostdata;
983 u16 tag = cmd->request->tag;
986 int result = SUCCESS;
988 base = hba->mmio_base;
989 spin_lock_irqsave(host->host_lock, flags);
990 if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
991 hba->wait_ccb = &hba->ccb[tag];
993 for (tag = 0; tag < host->can_queue; tag++)
994 if (hba->ccb[tag].cmd == cmd) {
995 hba->wait_ccb = &hba->ccb[tag];
998 if (tag >= host->can_queue)
1002 data = readl(base + ODBL);
1003 if (data == 0 || data == 0xffffffff)
1006 writel(data, base + ODBL);
1007 readl(base + ODBL); /* flush */
1009 stex_mu_intr(hba, data);
1011 if (hba->wait_ccb == NULL) {
1012 printk(KERN_WARNING DRV_NAME
1013 "(%s): lost interrupt\n", pci_name(hba->pdev));
1018 stex_unmap_sg(hba, cmd);
1019 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1020 hba->wait_ccb = NULL;
1023 spin_unlock_irqrestore(host->host_lock, flags);
1027 static void stex_hard_reset(struct st_hba *hba)
1029 struct pci_bus *bus;
1034 for (i = 0; i < 16; i++)
1035 pci_read_config_dword(hba->pdev, i * 4,
1036 &hba->pdev->saved_config_space[i]);
1038 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1039 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1040 bus = hba->pdev->bus;
1041 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1042 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1043 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1046 * 1 ms may be enough for 8-port controllers. But 16-port controllers
1047 * require more time to finish bus reset. Use 100 ms here for safety
1050 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1051 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1053 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1054 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1055 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1061 for (i = 0; i < 16; i++)
1062 pci_write_config_dword(hba->pdev, i * 4,
1063 hba->pdev->saved_config_space[i]);
1066 static int stex_reset(struct scsi_cmnd *cmd)
1069 unsigned long flags;
1070 unsigned long before;
1071 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1073 hba->mu_status = MU_STATE_RESETTING;
1075 if (hba->cardtype == st_shasta)
1076 stex_hard_reset(hba);
1078 if (hba->cardtype != st_yosemite) {
1079 if (stex_handshake(hba)) {
1080 printk(KERN_WARNING DRV_NAME
1081 "(%s): resetting: handshake failed\n",
1082 pci_name(hba->pdev));
1085 spin_lock_irqsave(hba->host->host_lock, flags);
1088 hba->status_head = 0;
1089 hba->status_tail = 0;
1090 hba->out_req_cnt = 0;
1091 spin_unlock_irqrestore(hba->host->host_lock, flags);
1096 writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1097 readl(hba->mmio_base + IDBL); /* flush */
1099 while (hba->out_req_cnt > 0) {
1100 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1101 printk(KERN_WARNING DRV_NAME
1102 "(%s): reset timeout\n", pci_name(hba->pdev));
1108 hba->mu_status = MU_STATE_STARTED;
1112 static int stex_biosparam(struct scsi_device *sdev,
1113 struct block_device *bdev, sector_t capacity, int geom[])
1115 int heads = 255, sectors = 63;
1117 if (capacity < 0x200000) {
1122 sector_div(capacity, heads * sectors);
1131 static struct scsi_host_template driver_template = {
1132 .module = THIS_MODULE,
1134 .proc_name = DRV_NAME,
1135 .bios_param = stex_biosparam,
1136 .queuecommand = stex_queuecommand,
1137 .slave_alloc = stex_slave_alloc,
1138 .slave_configure = stex_slave_config,
1139 .slave_destroy = stex_slave_destroy,
1140 .eh_abort_handler = stex_abort,
1141 .eh_host_reset_handler = stex_reset,
1142 .can_queue = ST_CAN_QUEUE,
1144 .sg_tablesize = ST_MAX_SG,
1145 .cmd_per_lun = ST_CMD_PER_LUN,
1148 static int stex_set_dma_mask(struct pci_dev * pdev)
1151 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1152 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1154 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1156 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1160 static int __devinit
1161 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1164 struct Scsi_Host *host;
1167 err = pci_enable_device(pdev);
1171 pci_set_master(pdev);
1173 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1176 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1182 hba = (struct st_hba *)host->hostdata;
1183 memset(hba, 0, sizeof(struct st_hba));
1185 err = pci_request_regions(pdev, DRV_NAME);
1187 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1189 goto out_scsi_host_put;
1192 hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
1193 pci_resource_len(pdev, 0));
1194 if ( !hba->mmio_base) {
1195 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1198 goto out_release_regions;
1201 err = stex_set_dma_mask(pdev);
1203 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1208 hba->cardtype = (unsigned int) id->driver_data;
1209 if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
1210 hba->cardtype = st_vsc1;
1211 hba->dma_size = (hba->cardtype == st_vsc1) ?
1212 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1213 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1214 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1215 if (!hba->dma_mem) {
1217 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1222 hba->status_buffer =
1223 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1224 hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1225 hba->mu_status = MU_STATE_STARTING;
1227 if (hba->cardtype == st_shasta) {
1229 host->max_id = 16 + 1;
1230 } else if (hba->cardtype == st_yosemite) {
1231 host->max_lun = 128;
1232 host->max_id = 1 + 1;
1234 /* st_vsc and st_vsc1 */
1236 host->max_id = 128 + 1;
1238 host->max_channel = 0;
1239 host->unique_id = host->host_no;
1240 host->max_cmd_len = STEX_CDB_LENGTH;
1244 init_waitqueue_head(&hba->waitq);
1246 err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1248 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1253 err = stex_handshake(hba);
1257 err = scsi_init_shared_tag_map(host, host->can_queue);
1259 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1264 pci_set_drvdata(pdev, hba);
1266 err = scsi_add_host(host, &pdev->dev);
1268 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1273 scsi_scan_host(host);
1278 free_irq(pdev->irq, hba);
1280 dma_free_coherent(&pdev->dev, hba->dma_size,
1281 hba->dma_mem, hba->dma_handle);
1283 iounmap(hba->mmio_base);
1284 out_release_regions:
1285 pci_release_regions(pdev);
1287 scsi_host_put(host);
1289 pci_disable_device(pdev);
1294 static void stex_hba_stop(struct st_hba *hba)
1296 struct req_msg *req;
1297 unsigned long flags;
1298 unsigned long before;
1301 spin_lock_irqsave(hba->host->host_lock, flags);
1302 req = stex_alloc_req(hba);
1303 memset(req->cdb, 0, STEX_CDB_LENGTH);
1305 if (hba->cardtype == st_yosemite) {
1306 req->cdb[0] = MGT_CMD;
1307 req->cdb[1] = MGT_CMD_SIGNATURE;
1308 req->cdb[2] = CTLR_CONFIG_CMD;
1309 req->cdb[3] = CTLR_SHUTDOWN;
1311 req->cdb[0] = CONTROLLER_CMD;
1312 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1313 req->cdb[2] = CTLR_POWER_SAVING;
1316 hba->ccb[tag].cmd = NULL;
1317 hba->ccb[tag].sg_count = 0;
1318 hba->ccb[tag].sense_bufflen = 0;
1319 hba->ccb[tag].sense_buffer = NULL;
1320 hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1322 stex_send_cmd(hba, req, tag);
1323 spin_unlock_irqrestore(hba->host->host_lock, flags);
1326 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1327 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1333 static void stex_hba_free(struct st_hba *hba)
1335 free_irq(hba->pdev->irq, hba);
1337 iounmap(hba->mmio_base);
1339 pci_release_regions(hba->pdev);
1341 dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1342 hba->dma_mem, hba->dma_handle);
1345 static void stex_remove(struct pci_dev *pdev)
1347 struct st_hba *hba = pci_get_drvdata(pdev);
1349 scsi_remove_host(hba->host);
1351 pci_set_drvdata(pdev, NULL);
1357 scsi_host_put(hba->host);
1359 pci_disable_device(pdev);
1362 static void stex_shutdown(struct pci_dev *pdev)
1364 struct st_hba *hba = pci_get_drvdata(pdev);
1369 static struct pci_device_id stex_pci_tbl[] = {
1371 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1372 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1373 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1374 st_shasta }, /* SuperTrak EX12350 */
1375 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1376 st_shasta }, /* SuperTrak EX4350 */
1377 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1378 st_shasta }, /* SuperTrak EX24350 */
1381 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1384 { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
1385 st_yosemite }, /* SuperTrak EX4650 */
1386 { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
1387 st_yosemite }, /* SuperTrak EX4650o */
1388 { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
1389 st_yosemite }, /* SuperTrak EX8650EL */
1390 { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
1391 st_yosemite }, /* SuperTrak EX8650 */
1392 { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
1393 st_yosemite }, /* SuperTrak EX8654 */
1394 { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1395 st_yosemite }, /* generic st_yosemite */
1396 { } /* terminate list */
1398 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1400 static struct pci_driver stex_pci_driver = {
1402 .id_table = stex_pci_tbl,
1403 .probe = stex_probe,
1404 .remove = __devexit_p(stex_remove),
1405 .shutdown = stex_shutdown,
1408 static int __init stex_init(void)
1410 printk(KERN_INFO DRV_NAME
1411 ": Promise SuperTrak EX Driver version: %s\n",
1414 return pci_register_driver(&stex_pci_driver);
1417 static void __exit stex_exit(void)
1419 pci_unregister_driver(&stex_pci_driver);
1422 module_init(stex_init);
1423 module_exit(stex_exit);