drivers/scsi/stex.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * SuperTrak EX Series Storage Controller driver for Linux
   4  *
   5  *      Copyright (C) 2005-2015 Promise Technology Inc.
   6  *
   7  *      Written By:
   8  *              Ed Lin <promise_linux@promise.com>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/delay.h>
  15 #include <linux/slab.h>
  16 #include <linux/time.h>
  17 #include <linux/pci.h>
  18 #include <linux/blkdev.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/types.h>
  21 #include <linux/module.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/ktime.h>
  24 #include <linux/reboot.h>
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27 #include <asm/byteorder.h>
  28 #include <scsi/scsi.h>
  29 #include <scsi/scsi_device.h>
  30 #include <scsi/scsi_cmnd.h>
  31 #include <scsi/scsi_host.h>
  32 #include <scsi/scsi_tcq.h>
  33 #include <scsi/scsi_dbg.h>
  34 #include <scsi/scsi_eh.h>
  35
  36 #define DRV_NAME "stex"
  37 #define ST_DRIVER_VERSION       "6.02.0000.01"
  38 #define ST_VER_MAJOR            6
  39 #define ST_VER_MINOR            02
  40 #define ST_OEM                          0000
  41 #define ST_BUILD_VER            01
  42
  43 enum {
  44         /* MU register offset */
  45         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  46         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  47         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  48         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  49         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  50         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  51         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  52         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  53         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  54         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  55
  56         YIOA_STATUS                             = 0x00,
  57         YH2I_INT                                = 0x20,
  58         YINT_EN                                 = 0x34,
  59         YI2H_INT                                = 0x9c,
  60         YI2H_INT_C                              = 0xa0,
  61         YH2I_REQ                                = 0xc0,
  62         YH2I_REQ_HI                             = 0xc4,
  63         PSCRATCH0                               = 0xb0,
  64         PSCRATCH1                               = 0xb4,
  65         PSCRATCH2                               = 0xb8,
  66         PSCRATCH3                               = 0xbc,
  67         PSCRATCH4                               = 0xc8,
  68         MAILBOX_BASE                    = 0x1000,
  69         MAILBOX_HNDSHK_STS              = 0x0,
  70
  71         /* MU register value */
  72         MU_INBOUND_DOORBELL_HANDSHAKE           = (1 << 0),
  73         MU_INBOUND_DOORBELL_REQHEADCHANGED      = (1 << 1),
  74         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
  75         MU_INBOUND_DOORBELL_HMUSTOPPED          = (1 << 3),
  76         MU_INBOUND_DOORBELL_RESET               = (1 << 4),
  77
  78         MU_OUTBOUND_DOORBELL_HANDSHAKE          = (1 << 0),
  79         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  80         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
  81         MU_OUTBOUND_DOORBELL_BUSCHANGE          = (1 << 3),
  82         MU_OUTBOUND_DOORBELL_HASEVENT           = (1 << 4),
  83         MU_OUTBOUND_DOORBELL_REQUEST_RESET      = (1 << 27),
  84
  85         /* MU status code */
  86         MU_STATE_STARTING                       = 1,
  87         MU_STATE_STARTED                        = 2,
  88         MU_STATE_RESETTING                      = 3,
  89         MU_STATE_FAILED                         = 4,
  90         MU_STATE_STOP                           = 5,
  91         MU_STATE_NOCONNECT                      = 6,
  92
  93         MU_MAX_DELAY                            = 50,
  94         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  95         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  96         MU_HARD_RESET_WAIT                      = 30000,
  97         HMU_PARTNER_TYPE                        = 2,
  98
  99         /* firmware returned values */
 100         SRB_STATUS_SUCCESS                      = 0x01,
 101         SRB_STATUS_ERROR                        = 0x04,
 102         SRB_STATUS_BUSY                         = 0x05,
 103         SRB_STATUS_INVALID_REQUEST              = 0x06,
 104         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
 105         SRB_SEE_SENSE                           = 0x80,
 106
 107         /* task attribute */
 108         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
 109         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
 110         TASK_ATTRIBUTE_ORDERED                  = 0x2,
 111         TASK_ATTRIBUTE_ACA                      = 0x4,
 112
 113         SS_STS_NORMAL                           = 0x80000000,
 114         SS_STS_DONE                             = 0x40000000,
 115         SS_STS_HANDSHAKE                        = 0x20000000,
 116
 117         SS_HEAD_HANDSHAKE                       = 0x80,
 118
 119         SS_H2I_INT_RESET                        = 0x100,
 120
 121         SS_I2H_REQUEST_RESET                    = 0x2000,
 122
 123         SS_MU_OPERATIONAL                       = 0x80000000,
 124
 125         STEX_CDB_LENGTH                         = 16,
 126         STATUS_VAR_LEN                          = 128,
 127
 128         /* sg flags */
 129         SG_CF_EOT                               = 0x80, /* end of table */
 130         SG_CF_64B                               = 0x40, /* 64 bit item */
 131         SG_CF_HOST                              = 0x20, /* sg in host memory */
 132         MSG_DATA_DIR_ND                         = 0,
 133         MSG_DATA_DIR_IN                         = 1,
 134         MSG_DATA_DIR_OUT                        = 2,
 135
 136         st_shasta                               = 0,
 137         st_vsc                                  = 1,
 138         st_yosemite                             = 2,
 139         st_seq                                  = 3,
 140         st_yel                                  = 4,
 141         st_P3                                   = 5,
 142
 143         PASSTHRU_REQ_TYPE                       = 0x00000001,
 144         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 145         ST_INTERNAL_TIMEOUT                     = 180,
 146
 147         ST_TO_CMD                               = 0,
 148         ST_FROM_CMD                             = 1,
 149
 150         /* vendor specific commands of Promise */
 151         MGT_CMD                                 = 0xd8,
 152         SINBAND_MGT_CMD                         = 0xd9,
 153         ARRAY_CMD                               = 0xe0,
 154         CONTROLLER_CMD                          = 0xe1,
 155         DEBUGGING_CMD                           = 0xe2,
 156         PASSTHRU_CMD                            = 0xe3,
 157
 158         PASSTHRU_GET_ADAPTER                    = 0x05,
 159         PASSTHRU_GET_DRVVER                     = 0x10,
 160
 161         CTLR_CONFIG_CMD                         = 0x03,
 162         CTLR_SHUTDOWN                           = 0x0d,
 163
 164         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 165         CTLR_POWER_SAVING                       = 0x01,
 166
 167         PASSTHRU_SIGNATURE                      = 0x4e415041,
 168         MGT_CMD_SIGNATURE                       = 0xba,
 169
 170         INQUIRY_EVPD                            = 0x01,
 171
 172         ST_ADDITIONAL_MEM                       = 0x200000,
 173         ST_ADDITIONAL_MEM_MIN                   = 0x80000,
 174         PMIC_SHUTDOWN                           = 0x0D,
 175         PMIC_REUMSE                                     = 0x10,
 176         ST_IGNORED                                      = -1,
 177         ST_NOTHANDLED                           = 7,
 178         ST_S3                                           = 3,
 179         ST_S4                                           = 4,
 180         ST_S5                                           = 5,
 181         ST_S6                                           = 6,
 182 };
 183
 184 struct st_sgitem {
 185         u8 ctrl;        /* SG_CF_xxx */
 186         u8 reserved[3];
 187         __le32 count;
 188         __le64 addr;
 189 };
 190
 191 struct st_ss_sgitem {
 192         __le32 addr;
 193         __le32 addr_hi;
 194         __le32 count;
 195 };
 196
 197 struct st_sgtable {
 198         __le16 sg_count;
 199         __le16 max_sg_count;
 200         __le32 sz_in_byte;
 201 };
 202
 203 struct st_msg_header {
 204         __le64 handle;
 205         u8 flag;
 206         u8 channel;
 207         __le16 timeout;
 208         u32 reserved;
 209 };
 210
 211 struct handshake_frame {
 212         __le64 rb_phy;          /* request payload queue physical address */
 213         __le16 req_sz;          /* size of each request payload */
 214         __le16 req_cnt;         /* count of reqs the buffer can hold */
 215         __le16 status_sz;       /* size of each status payload */
 216         __le16 status_cnt;      /* count of status the buffer can hold */
 217         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 218         u8 partner_type;        /* who sends this frame */
 219         u8 reserved0[7];
 220         __le32 partner_ver_major;
 221         __le32 partner_ver_minor;
 222         __le32 partner_ver_oem;
 223         __le32 partner_ver_build;
 224         __le32 extra_offset;    /* NEW */
 225         __le32 extra_size;      /* NEW */
 226         __le32 scratch_size;
 227         u32 reserved1;
 228 };
 229
 230 struct req_msg {
 231         __le16 tag;
 232         u8 lun;
 233         u8 target;
 234         u8 task_attr;
 235         u8 task_manage;
 236         u8 data_dir;
 237         u8 payload_sz;          /* payload size in 4-byte, not used */
 238         u8 cdb[STEX_CDB_LENGTH];
 239         u32 variable[];
 240 };
 241
 242 struct status_msg {
 243         __le16 tag;
 244         u8 lun;
 245         u8 target;
 246         u8 srb_status;
 247         u8 scsi_status;
 248         u8 reserved;
 249         u8 payload_sz;          /* payload size in 4-byte */
 250         u8 variable[STATUS_VAR_LEN];
 251 };
 252
 253 struct ver_info {
 254         u32 major;
 255         u32 minor;
 256         u32 oem;
 257         u32 build;
 258         u32 reserved[2];
 259 };
 260
 261 struct st_frame {
 262         u32 base[6];
 263         u32 rom_addr;
 264
 265         struct ver_info drv_ver;
 266         struct ver_info bios_ver;
 267
 268         u32 bus;
 269         u32 slot;
 270         u32 irq_level;
 271         u32 irq_vec;
 272         u32 id;
 273         u32 subid;
 274
 275         u32 dimm_size;
 276         u8 dimm_type;
 277         u8 reserved[3];
 278
 279         u32 channel;
 280         u32 reserved1;
 281 };
 282
 283 struct st_drvver {
 284         u32 major;
 285         u32 minor;
 286         u32 oem;
 287         u32 build;
 288         u32 signature[2];
 289         u8 console_id;
 290         u8 host_no;
 291         u8 reserved0[2];
 292         u32 reserved[3];
 293 };
 294
 295 struct st_ccb {
 296         struct req_msg *req;
 297         struct scsi_cmnd *cmd;
 298
 299         void *sense_buffer;
 300         unsigned int sense_bufflen;
 301         int sg_count;
 302
 303         u32 req_type;
 304         u8 srb_status;
 305         u8 scsi_status;
 306         u8 reserved[2];
 307 };
 308
 309 struct st_hba {
 310         void __iomem *mmio_base;        /* iomapped PCI memory space */
 311         void *dma_mem;
 312         dma_addr_t dma_handle;
 313         size_t dma_size;
 314
 315         struct Scsi_Host *host;
 316         struct pci_dev *pdev;
 317
 318         struct req_msg * (*alloc_rq) (struct st_hba *);
 319         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 320         void (*send) (struct st_hba *, struct req_msg *, u16);
 321
 322         u32 req_head;
 323         u32 req_tail;
 324         u32 status_head;
 325         u32 status_tail;
 326
 327         struct status_msg *status_buffer;
 328         void *copy_buffer; /* temp buffer for driver-handled commands */
 329         struct st_ccb *ccb;
 330         struct st_ccb *wait_ccb;
 331         __le32 *scratch;
 332
 333         char work_q_name[20];
 334         struct workqueue_struct *work_q;
 335         struct work_struct reset_work;
 336         wait_queue_head_t reset_waitq;
 337         unsigned int mu_status;
 338         unsigned int cardtype;
 339         int msi_enabled;
 340         int out_req_cnt;
 341         u32 extra_offset;
 342         u16 rq_count;
 343         u16 rq_size;
 344         u16 sts_count;
 345         u8  supports_pm;
 346         int msi_lock;
 347 };
 348
 349 struct st_card_info {
 350         struct req_msg * (*alloc_rq) (struct st_hba *);
 351         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 352         void (*send) (struct st_hba *, struct req_msg *, u16);
 353         unsigned int max_id;
 354         unsigned int max_lun;
 355         unsigned int max_channel;
 356         u16 rq_count;
 357         u16 rq_size;
 358         u16 sts_count;
 359 };
 360
 361 static int S6flag;
 362 static int stex_halt(struct notifier_block *nb, ulong event, void *buf);
 363 static struct notifier_block stex_notifier = {
 364         stex_halt, NULL, 0
 365 };
 366
 367 static int msi;
 368 module_param(msi, int, 0);
 369 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 370
 371 static const char console_inq_page[] =
 372 {
 373         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 374         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 375         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 376         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 377         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 378         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 379         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 380         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 381 };
 382
 383 MODULE_AUTHOR("Ed Lin");
 384 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 385 MODULE_LICENSE("GPL");
 386 MODULE_VERSION(ST_DRIVER_VERSION);
 387
 388 static struct status_msg *stex_get_status(struct st_hba *hba)
 389 {
 390         struct status_msg *status = hba->status_buffer + hba->status_tail;
 391
 392         ++hba->status_tail;
 393         hba->status_tail %= hba->sts_count+1;
 394
 395         return status;
 396 }
 397
 398 static void stex_invalid_field(struct scsi_cmnd *cmd,
 399                                void (*done)(struct scsi_cmnd *))
 400 {
 401         /* "Invalid field in cdb" */
 402         scsi_build_sense(cmd, 0, ILLEGAL_REQUEST, 0x24, 0x0);
 403         done(cmd);
 404 }
 405
 406 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 407 {
 408         struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
 409
 410         ++hba->req_head;
 411         hba->req_head %= hba->rq_count+1;
 412
 413         return req;
 414 }
 415
 416 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
 417 {
 418         return (struct req_msg *)(hba->dma_mem +
 419                 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
 420 }
 421
 422 static int stex_map_sg(struct st_hba *hba,
 423         struct req_msg *req, struct st_ccb *ccb)
 424 {
 425         struct scsi_cmnd *cmd;
 426         struct scatterlist *sg;
 427         struct st_sgtable *dst;
 428         struct st_sgitem *table;
 429         int i, nseg;
 430
 431         cmd = ccb->cmd;
 432         nseg = scsi_dma_map(cmd);
 433         BUG_ON(nseg < 0);
 434         if (nseg) {
 435                 dst = (struct st_sgtable *)req->variable;
 436
 437                 ccb->sg_count = nseg;
 438                 dst->sg_count = cpu_to_le16((u16)nseg);
 439                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 440                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 441
 442                 table = (struct st_sgitem *)(dst + 1);
 443                 scsi_for_each_sg(cmd, sg, nseg, i) {
 444                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 445                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 446                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 447                 }
 448                 table[--i].ctrl |= SG_CF_EOT;
 449         }
 450
 451         return nseg;
 452 }
 453
 454 static int stex_ss_map_sg(struct st_hba *hba,
 455         struct req_msg *req, struct st_ccb *ccb)
 456 {
 457         struct scsi_cmnd *cmd;
 458         struct scatterlist *sg;
 459         struct st_sgtable *dst;
 460         struct st_ss_sgitem *table;
 461         int i, nseg;
 462
 463         cmd = ccb->cmd;
 464         nseg = scsi_dma_map(cmd);
 465         BUG_ON(nseg < 0);
 466         if (nseg) {
 467                 dst = (struct st_sgtable *)req->variable;
 468
 469                 ccb->sg_count = nseg;
 470                 dst->sg_count = cpu_to_le16((u16)nseg);
 471                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 472                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 473
 474                 table = (struct st_ss_sgitem *)(dst + 1);
 475                 scsi_for_each_sg(cmd, sg, nseg, i) {
 476                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 477                         table[i].addr =
 478                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 479                         table[i].addr_hi =
 480                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 481                 }
 482         }
 483
 484         return nseg;
 485 }
 486
 487 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 488 {
 489         struct st_frame *p;
 490         size_t count = sizeof(struct st_frame);
 491
 492         p = hba->copy_buffer;
 493         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 494         memset(p->base, 0, sizeof(u32)*6);
 495         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 496         p->rom_addr = 0;
 497
 498         p->drv_ver.major = ST_VER_MAJOR;
 499         p->drv_ver.minor = ST_VER_MINOR;
 500         p->drv_ver.oem = ST_OEM;
 501         p->drv_ver.build = ST_BUILD_VER;
 502
 503         p->bus = hba->pdev->bus->number;
 504         p->slot = hba->pdev->devfn;
 505         p->irq_level = 0;
 506         p->irq_vec = hba->pdev->irq;
 507         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 508         p->subid =
 509                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 510
 511         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 512 }
 513
 514 static void
 515 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 516 {
 517         req->tag = cpu_to_le16(tag);
 518
 519         hba->ccb[tag].req = req;
 520         hba->out_req_cnt++;
 521
 522         writel(hba->req_head, hba->mmio_base + IMR0);
 523         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 524         readl(hba->mmio_base + IDBL); /* flush */
 525 }
 526
 527 static void
 528 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 529 {
 530         struct scsi_cmnd *cmd;
 531         struct st_msg_header *msg_h;
 532         dma_addr_t addr;
 533
 534         req->tag = cpu_to_le16(tag);
 535
 536         hba->ccb[tag].req = req;
 537         hba->out_req_cnt++;
 538
 539         cmd = hba->ccb[tag].cmd;
 540         msg_h = (struct st_msg_header *)req - 1;
 541         if (likely(cmd)) {
 542                 msg_h->channel = (u8)cmd->device->channel;
 543                 msg_h->timeout = cpu_to_le16(scsi_cmd_to_rq(cmd)->timeout / HZ);
 544         }
 545         addr = hba->dma_handle + hba->req_head * hba->rq_size;
 546         addr += (hba->ccb[tag].sg_count+4)/11;
 547         msg_h->handle = cpu_to_le64(addr);
 548
 549         ++hba->req_head;
 550         hba->req_head %= hba->rq_count+1;
 551         if (hba->cardtype == st_P3) {
 552                 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 553                 writel(addr, hba->mmio_base + YH2I_REQ);
 554         } else {
 555                 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 556                 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
 557                 writel(addr, hba->mmio_base + YH2I_REQ);
 558                 readl(hba->mmio_base + YH2I_REQ); /* flush */
 559         }
 560 }
 561
 562 static void return_abnormal_state(struct st_hba *hba, int status)
 563 {
 564         struct st_ccb *ccb;
 565         unsigned long flags;
 566         u16 tag;
 567
 568         spin_lock_irqsave(hba->host->host_lock, flags);
 569         for (tag = 0; tag < hba->host->can_queue; tag++) {
 570                 ccb = &hba->ccb[tag];
 571                 if (ccb->req == NULL)
 572                         continue;
 573                 ccb->req = NULL;
 574                 if (ccb->cmd) {
 575                         scsi_dma_unmap(ccb->cmd);
 576                         ccb->cmd->result = status << 16;
 577                         scsi_done(ccb->cmd);
 578                         ccb->cmd = NULL;
 579                 }
 580         }
 581         spin_unlock_irqrestore(hba->host->host_lock, flags);
 582 }
 583 static int
 584 stex_slave_config(struct scsi_device *sdev)
 585 {
 586         sdev->use_10_for_rw = 1;
 587         sdev->use_10_for_ms = 1;
 588         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 589
 590         return 0;
 591 }
 592
 593 static int stex_queuecommand_lck(struct scsi_cmnd *cmd)
 594 {
 595         void (*done)(struct scsi_cmnd *) = scsi_done;
 596         struct st_hba *hba;
 597         struct Scsi_Host *host;
 598         unsigned int id, lun;
 599         struct req_msg *req;
 600         u16 tag;
 601
 602         host = cmd->device->host;
 603         id = cmd->device->id;
 604         lun = cmd->device->lun;
 605         hba = (struct st_hba *) &host->hostdata[0];
 606         if (hba->mu_status == MU_STATE_NOCONNECT) {
 607                 cmd->result = DID_NO_CONNECT;
 608                 done(cmd);
 609                 return 0;
 610         }
 611         if (unlikely(hba->mu_status != MU_STATE_STARTED))
 612                 return SCSI_MLQUEUE_HOST_BUSY;
 613
 614         switch (cmd->cmnd[0]) {
 615         case MODE_SENSE_10:
 616         {
 617                 static char ms10_caching_page[12] =
 618                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 619                 unsigned char page;
 620
 621                 page = cmd->cmnd[2] & 0x3f;
 622                 if (page == 0x8 || page == 0x3f) {
 623                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 624                                                  sizeof(ms10_caching_page));
 625                         cmd->result = DID_OK << 16;
 626                         done(cmd);
 627                 } else
 628                         stex_invalid_field(cmd, done);
 629                 return 0;
 630         }
 631         case REPORT_LUNS:
 632                 /*
 633                  * The shasta firmware does not report actual luns in the
 634                  * target, so fail the command to force sequential lun scan.
 635                  * Also, the console device does not support this command.
 636                  */
 637                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 638                         stex_invalid_field(cmd, done);
 639                         return 0;
 640                 }
 641                 break;
 642         case TEST_UNIT_READY:
 643                 if (id == host->max_id - 1) {
 644                         cmd->result = DID_OK << 16;
 645                         done(cmd);
 646                         return 0;
 647                 }
 648                 break;
 649         case INQUIRY:
 650                 if (lun >= host->max_lun) {
 651                         cmd->result = DID_NO_CONNECT << 16;
 652                         done(cmd);
 653                         return 0;
 654                 }
 655                 if (id != host->max_id - 1)
 656                         break;
 657                 if (!lun && !cmd->device->channel &&
 658                         (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 659                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 660                                                  sizeof(console_inq_page));
 661                         cmd->result = DID_OK << 16;
 662                         done(cmd);
 663                 } else
 664                         stex_invalid_field(cmd, done);
 665                 return 0;
 666         case PASSTHRU_CMD:
 667                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 668                         const struct st_drvver ver = {
 669                                 .major = ST_VER_MAJOR,
 670                                 .minor = ST_VER_MINOR,
 671                                 .oem = ST_OEM,
 672                                 .build = ST_BUILD_VER,
 673                                 .signature[0] = PASSTHRU_SIGNATURE,
 674                                 .console_id = host->max_id - 1,
 675                                 .host_no = hba->host->host_no,
 676                         };
 677                         size_t cp_len = sizeof(ver);
 678
 679                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 680                         if (sizeof(ver) == cp_len)
 681                                 cmd->result = DID_OK << 16;
 682                         else
 683                                 cmd->result = DID_ERROR << 16;
 684                         done(cmd);
 685                         return 0;
 686                 }
 687                 break;
 688         default:
 689                 break;
 690         }
 691
 692         tag = scsi_cmd_to_rq(cmd)->tag;
 693
 694         if (unlikely(tag >= host->can_queue))
 695                 return SCSI_MLQUEUE_HOST_BUSY;
 696
 697         req = hba->alloc_rq(hba);
 698
 699         req->lun = lun;
 700         req->target = id;
 701
 702         /* cdb */
 703         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 704
 705         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 706                 req->data_dir = MSG_DATA_DIR_IN;
 707         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 708                 req->data_dir = MSG_DATA_DIR_OUT;
 709         else
 710                 req->data_dir = MSG_DATA_DIR_ND;
 711
 712         hba->ccb[tag].cmd = cmd;
 713         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 714         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 715
 716         if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
 717                 hba->ccb[tag].sg_count = 0;
 718                 memset(&req->variable[0], 0, 8);
 719         }
 720
 721         hba->send(hba, req, tag);
 722         return 0;
 723 }
 724
 725 static DEF_SCSI_QCMD(stex_queuecommand)
 726
 727 static void stex_scsi_done(struct st_ccb *ccb)
 728 {
 729         struct scsi_cmnd *cmd = ccb->cmd;
 730         int result;
 731
 732         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 733                 result = ccb->scsi_status;
 734                 switch (ccb->scsi_status) {
 735                 case SAM_STAT_GOOD:
 736                         result |= DID_OK << 16;
 737                         break;
 738                 case SAM_STAT_CHECK_CONDITION:
 739                         result |= DID_OK << 16;
 740                         break;
 741                 case SAM_STAT_BUSY:
 742                         result |= DID_BUS_BUSY << 16;
 743                         break;
 744                 default:
 745                         result |= DID_ERROR << 16;
 746                         break;
 747                 }
 748         }
 749         else if (ccb->srb_status & SRB_SEE_SENSE)
 750                 result = SAM_STAT_CHECK_CONDITION;
 751         else switch (ccb->srb_status) {
 752                 case SRB_STATUS_SELECTION_TIMEOUT:
 753                         result = DID_NO_CONNECT << 16;
 754                         break;
 755                 case SRB_STATUS_BUSY:
 756                         result = DID_BUS_BUSY << 16;
 757                         break;
 758                 case SRB_STATUS_INVALID_REQUEST:
 759                 case SRB_STATUS_ERROR:
 760                 default:
 761                         result = DID_ERROR << 16;
 762                         break;
 763         }
 764
 765         cmd->result = result;
 766         scsi_done(cmd);
 767 }
 768
 769 static void stex_copy_data(struct st_ccb *ccb,
 770         struct status_msg *resp, unsigned int variable)
 771 {
 772         if (resp->scsi_status != SAM_STAT_GOOD) {
 773                 if (ccb->sense_buffer != NULL)
 774                         memcpy(ccb->sense_buffer, resp->variable,
 775                                 min(variable, ccb->sense_bufflen));
 776                 return;
 777         }
 778
 779         if (ccb->cmd == NULL)
 780                 return;
 781         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 782 }
 783
 784 static void stex_check_cmd(struct st_hba *hba,
 785         struct st_ccb *ccb, struct status_msg *resp)
 786 {
 787         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 788                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 789                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 790                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 791 }
 792
 793 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 794 {
 795         void __iomem *base = hba->mmio_base;
 796         struct status_msg *resp;
 797         struct st_ccb *ccb;
 798         unsigned int size;
 799         u16 tag;
 800
 801         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 802                 return;
 803
 804         /* status payloads */
 805         hba->status_head = readl(base + OMR1);
 806         if (unlikely(hba->status_head > hba->sts_count)) {
 807                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 808                         pci_name(hba->pdev));
 809                 return;
 810         }
 811
 812         /*
 813          * it's not a valid status payload if:
 814          * 1. there are no pending requests(e.g. during init stage)
 815          * 2. there are some pending requests, but the controller is in
 816          *     reset status, and its type is not st_yosemite
 817          * firmware of st_yosemite in reset status will return pending requests
 818          * to driver, so we allow it to pass
 819          */
 820         if (unlikely(hba->out_req_cnt <= 0 ||
 821                         (hba->mu_status == MU_STATE_RESETTING &&
 822                          hba->cardtype != st_yosemite))) {
 823                 hba->status_tail = hba->status_head;
 824                 goto update_status;
 825         }
 826
 827         while (hba->status_tail != hba->status_head) {
 828                 resp = stex_get_status(hba);
 829                 tag = le16_to_cpu(resp->tag);
 830                 if (unlikely(tag >= hba->host->can_queue)) {
 831                         printk(KERN_WARNING DRV_NAME
 832                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 833                         continue;
 834                 }
 835
 836                 hba->out_req_cnt--;
 837                 ccb = &hba->ccb[tag];
 838                 if (unlikely(hba->wait_ccb == ccb))
 839                         hba->wait_ccb = NULL;
 840                 if (unlikely(ccb->req == NULL)) {
 841                         printk(KERN_WARNING DRV_NAME
 842                                 "(%s): lagging req\n", pci_name(hba->pdev));
 843                         continue;
 844                 }
 845
 846                 size = resp->payload_sz * sizeof(u32); /* payload size */
 847                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 848                         size > sizeof(*resp))) {
 849                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 850                                 pci_name(hba->pdev));
 851                 } else {
 852                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 853                         if (size)
 854                                 stex_copy_data(ccb, resp, size);
 855                 }
 856
 857                 ccb->req = NULL;
 858                 ccb->srb_status = resp->srb_status;
 859                 ccb->scsi_status = resp->scsi_status;
 860
 861                 if (likely(ccb->cmd != NULL)) {
 862                         if (hba->cardtype == st_yosemite)
 863                                 stex_check_cmd(hba, ccb, resp);
 864
 865                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 866                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 867                                 stex_controller_info(hba, ccb);
 868
 869                         scsi_dma_unmap(ccb->cmd);
 870                         stex_scsi_done(ccb);
 871                 } else
 872                         ccb->req_type = 0;
 873         }
 874
 875 update_status:
 876         writel(hba->status_head, base + IMR1);
 877         readl(base + IMR1); /* flush */
 878 }
 879
 880 static irqreturn_t stex_intr(int irq, void *__hba)
 881 {
 882         struct st_hba *hba = __hba;
 883         void __iomem *base = hba->mmio_base;
 884         u32 data;
 885         unsigned long flags;
 886
 887         spin_lock_irqsave(hba->host->host_lock, flags);
 888
 889         data = readl(base + ODBL);
 890
 891         if (data && data != 0xffffffff) {
 892                 /* clear the interrupt */
 893                 writel(data, base + ODBL);
 894                 readl(base + ODBL); /* flush */
 895                 stex_mu_intr(hba, data);
 896                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 897                 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
 898                         hba->cardtype == st_shasta))
 899                         queue_work(hba->work_q, &hba->reset_work);
 900                 return IRQ_HANDLED;
 901         }
 902
 903         spin_unlock_irqrestore(hba->host->host_lock, flags);
 904
 905         return IRQ_NONE;
 906 }
 907
 908 static void stex_ss_mu_intr(struct st_hba *hba)
 909 {
 910         struct status_msg *resp;
 911         struct st_ccb *ccb;
 912         __le32 *scratch;
 913         unsigned int size;
 914         int count = 0;
 915         u32 value;
 916         u16 tag;
 917
 918         if (unlikely(hba->out_req_cnt <= 0 ||
 919                         hba->mu_status == MU_STATE_RESETTING))
 920                 return;
 921
 922         while (count < hba->sts_count) {
 923                 scratch = hba->scratch + hba->status_tail;
 924                 value = le32_to_cpu(*scratch);
 925                 if (unlikely(!(value & SS_STS_NORMAL)))
 926                         return;
 927
 928                 resp = hba->status_buffer + hba->status_tail;
 929                 *scratch = 0;
 930                 ++count;
 931                 ++hba->status_tail;
 932                 hba->status_tail %= hba->sts_count+1;
 933
 934                 tag = (u16)value;
 935                 if (unlikely(tag >= hba->host->can_queue)) {
 936                         printk(KERN_WARNING DRV_NAME
 937                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 938                         continue;
 939                 }
 940
 941                 hba->out_req_cnt--;
 942                 ccb = &hba->ccb[tag];
 943                 if (unlikely(hba->wait_ccb == ccb))
 944                         hba->wait_ccb = NULL;
 945                 if (unlikely(ccb->req == NULL)) {
 946                         printk(KERN_WARNING DRV_NAME
 947                                 "(%s): lagging req\n", pci_name(hba->pdev));
 948                         continue;
 949                 }
 950
 951                 ccb->req = NULL;
 952                 if (likely(value & SS_STS_DONE)) { /* normal case */
 953                         ccb->srb_status = SRB_STATUS_SUCCESS;
 954                         ccb->scsi_status = SAM_STAT_GOOD;
 955                 } else {
 956                         ccb->srb_status = resp->srb_status;
 957                         ccb->scsi_status = resp->scsi_status;
 958                         size = resp->payload_sz * sizeof(u32);
 959                         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 960                                 size > sizeof(*resp))) {
 961                                 printk(KERN_WARNING DRV_NAME
 962                                         "(%s): bad status size\n",
 963                                         pci_name(hba->pdev));
 964                         } else {
 965                                 size -= sizeof(*resp) - STATUS_VAR_LEN;
 966                                 if (size)
 967                                         stex_copy_data(ccb, resp, size);
 968                         }
 969                         if (likely(ccb->cmd != NULL))
 970                                 stex_check_cmd(hba, ccb, resp);
 971                 }
 972
 973                 if (likely(ccb->cmd != NULL)) {
 974                         scsi_dma_unmap(ccb->cmd);
 975                         stex_scsi_done(ccb);
 976                 } else
 977                         ccb->req_type = 0;
 978         }
 979 }
 980
 981 static irqreturn_t stex_ss_intr(int irq, void *__hba)
 982 {
 983         struct st_hba *hba = __hba;
 984         void __iomem *base = hba->mmio_base;
 985         u32 data;
 986         unsigned long flags;
 987
 988         spin_lock_irqsave(hba->host->host_lock, flags);
 989
 990         if (hba->cardtype == st_yel) {
 991                 data = readl(base + YI2H_INT);
 992                 if (data && data != 0xffffffff) {
 993                         /* clear the interrupt */
 994                         writel(data, base + YI2H_INT_C);
 995                         stex_ss_mu_intr(hba);
 996                         spin_unlock_irqrestore(hba->host->host_lock, flags);
 997                         if (unlikely(data & SS_I2H_REQUEST_RESET))
 998                                 queue_work(hba->work_q, &hba->reset_work);
 999                         return IRQ_HANDLED;
1000                 }
1001         } else {
1002                 data = readl(base + PSCRATCH4);
1003                 if (data != 0xffffffff) {
1004                         if (data != 0) {
1005                                 /* clear the interrupt */
1006                                 writel(data, base + PSCRATCH1);
1007                                 writel((1 << 22), base + YH2I_INT);
1008                         }
1009                         stex_ss_mu_intr(hba);
1010                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1011                         if (unlikely(data & SS_I2H_REQUEST_RESET))
1012                                 queue_work(hba->work_q, &hba->reset_work);
1013                         return IRQ_HANDLED;
1014                 }
1015         }
1016
1017         spin_unlock_irqrestore(hba->host->host_lock, flags);
1018
1019         return IRQ_NONE;
1020 }
1021
1022 static int stex_common_handshake(struct st_hba *hba)
1023 {
1024         void __iomem *base = hba->mmio_base;
1025         struct handshake_frame *h;
1026         dma_addr_t status_phys;
1027         u32 data;
1028         unsigned long before;
1029
1030         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1031                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1032                 readl(base + IDBL);
1033                 before = jiffies;
1034                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1035                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1036                                 printk(KERN_ERR DRV_NAME
1037                                         "(%s): no handshake signature\n",
1038                                         pci_name(hba->pdev));
1039                                 return -1;
1040                         }
1041                         rmb();
1042                         msleep(1);
1043                 }
1044         }
1045
1046         udelay(10);
1047
1048         data = readl(base + OMR1);
1049         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1050                 data &= 0x0000ffff;
1051                 if (hba->host->can_queue > data) {
1052                         hba->host->can_queue = data;
1053                         hba->host->cmd_per_lun = data;
1054                 }
1055         }
1056
1057         h = (struct handshake_frame *)hba->status_buffer;
1058         h->rb_phy = cpu_to_le64(hba->dma_handle);
1059         h->req_sz = cpu_to_le16(hba->rq_size);
1060         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1061         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1062         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1063         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1064         h->partner_type = HMU_PARTNER_TYPE;
1065         if (hba->extra_offset) {
1066                 h->extra_offset = cpu_to_le32(hba->extra_offset);
1067                 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1068         } else
1069                 h->extra_offset = h->extra_size = 0;
1070
1071         status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1072         writel(status_phys, base + IMR0);
1073         readl(base + IMR0);
1074         writel((status_phys >> 16) >> 16, base + IMR1);
1075         readl(base + IMR1);
1076
1077         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1078         readl(base + OMR0);
1079         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1080         readl(base + IDBL); /* flush */
1081
1082         udelay(10);
1083         before = jiffies;
1084         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1085                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1086                         printk(KERN_ERR DRV_NAME
1087                                 "(%s): no signature after handshake frame\n",
1088                                 pci_name(hba->pdev));
1089                         return -1;
1090                 }
1091                 rmb();
1092                 msleep(1);
1093         }
1094
1095         writel(0, base + IMR0);
1096         readl(base + IMR0);
1097         writel(0, base + OMR0);
1098         readl(base + OMR0);
1099         writel(0, base + IMR1);
1100         readl(base + IMR1);
1101         writel(0, base + OMR1);
1102         readl(base + OMR1); /* flush */
1103         return 0;
1104 }
1105
1106 static int stex_ss_handshake(struct st_hba *hba)
1107 {
1108         void __iomem *base = hba->mmio_base;
1109         struct st_msg_header *msg_h;
1110         struct handshake_frame *h;
1111         __le32 *scratch;
1112         u32 data, scratch_size, mailboxdata, operationaldata;
1113         unsigned long before;
1114         int ret = 0;
1115
1116         before = jiffies;
1117
1118         if (hba->cardtype == st_yel) {
1119                 operationaldata = readl(base + YIOA_STATUS);
1120                 while (operationaldata != SS_MU_OPERATIONAL) {
1121                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1122                                 printk(KERN_ERR DRV_NAME
1123                                         "(%s): firmware not operational\n",
1124                                         pci_name(hba->pdev));
1125                                 return -1;
1126                         }
1127                         msleep(1);
1128                         operationaldata = readl(base + YIOA_STATUS);
1129                 }
1130         } else {
1131                 operationaldata = readl(base + PSCRATCH3);
1132                 while (operationaldata != SS_MU_OPERATIONAL) {
1133                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1134                                 printk(KERN_ERR DRV_NAME
1135                                         "(%s): firmware not operational\n",
1136                                         pci_name(hba->pdev));
1137                                 return -1;
1138                         }
1139                         msleep(1);
1140                         operationaldata = readl(base + PSCRATCH3);
1141                 }
1142         }
1143
1144         msg_h = (struct st_msg_header *)hba->dma_mem;
1145         msg_h->handle = cpu_to_le64(hba->dma_handle);
1146         msg_h->flag = SS_HEAD_HANDSHAKE;
1147
1148         h = (struct handshake_frame *)(msg_h + 1);
1149         h->rb_phy = cpu_to_le64(hba->dma_handle);
1150         h->req_sz = cpu_to_le16(hba->rq_size);
1151         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1152         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1153         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1154         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1155         h->partner_type = HMU_PARTNER_TYPE;
1156         h->extra_offset = h->extra_size = 0;
1157         scratch_size = (hba->sts_count+1)*sizeof(u32);
1158         h->scratch_size = cpu_to_le32(scratch_size);
1159
1160         if (hba->cardtype == st_yel) {
1161                 data = readl(base + YINT_EN);
1162                 data &= ~4;
1163                 writel(data, base + YINT_EN);
1164                 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1165                 readl(base + YH2I_REQ_HI);
1166                 writel(hba->dma_handle, base + YH2I_REQ);
1167                 readl(base + YH2I_REQ); /* flush */
1168         } else {
1169                 data = readl(base + YINT_EN);
1170                 data &= ~(1 << 0);
1171                 data &= ~(1 << 2);
1172                 writel(data, base + YINT_EN);
1173                 if (hba->msi_lock == 0) {
1174                         /* P3 MSI Register cannot access twice */
1175                         writel((1 << 6), base + YH2I_INT);
1176                         hba->msi_lock  = 1;
1177                 }
1178                 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1179                 writel(hba->dma_handle, base + YH2I_REQ);
1180         }
1181
1182         before = jiffies;
1183         scratch = hba->scratch;
1184         if (hba->cardtype == st_yel) {
1185                 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1186                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1187                                 printk(KERN_ERR DRV_NAME
1188                                         "(%s): no signature after handshake frame\n",
1189                                         pci_name(hba->pdev));
1190                                 ret = -1;
1191                                 break;
1192                         }
1193                         rmb();
1194                         msleep(1);
1195                 }
1196         } else {
1197                 mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1198                 while (mailboxdata != SS_STS_HANDSHAKE) {
1199                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1200                                 printk(KERN_ERR DRV_NAME
1201                                         "(%s): no signature after handshake frame\n",
1202                                         pci_name(hba->pdev));
1203                                 ret = -1;
1204                                 break;
1205                         }
1206                         rmb();
1207                         msleep(1);
1208                         mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1209                 }
1210         }
1211         memset(scratch, 0, scratch_size);
1212         msg_h->flag = 0;
1213
1214         return ret;
1215 }
1216
1217 static int stex_handshake(struct st_hba *hba)
1218 {
1219         int err;
1220         unsigned long flags;
1221         unsigned int mu_status;
1222
1223         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1224                 err = stex_ss_handshake(hba);
1225         else
1226                 err = stex_common_handshake(hba);
1227         spin_lock_irqsave(hba->host->host_lock, flags);
1228         mu_status = hba->mu_status;
1229         if (err == 0) {
1230                 hba->req_head = 0;
1231                 hba->req_tail = 0;
1232                 hba->status_head = 0;
1233                 hba->status_tail = 0;
1234                 hba->out_req_cnt = 0;
1235                 hba->mu_status = MU_STATE_STARTED;
1236         } else
1237                 hba->mu_status = MU_STATE_FAILED;
1238         if (mu_status == MU_STATE_RESETTING)
1239                 wake_up_all(&hba->reset_waitq);
1240         spin_unlock_irqrestore(hba->host->host_lock, flags);
1241         return err;
1242 }
1243
1244 static int stex_abort(struct scsi_cmnd *cmd)
1245 {
1246         struct Scsi_Host *host = cmd->device->host;
1247         struct st_hba *hba = (struct st_hba *)host->hostdata;
1248         u16 tag = scsi_cmd_to_rq(cmd)->tag;
1249         void __iomem *base;
1250         u32 data;
1251         int result = SUCCESS;
1252         unsigned long flags;
1253
1254         scmd_printk(KERN_INFO, cmd, "aborting command\n");
1255
1256         base = hba->mmio_base;
1257         spin_lock_irqsave(host->host_lock, flags);
1258         if (tag < host->can_queue &&
1259                 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1260                 hba->wait_ccb = &hba->ccb[tag];
1261         else
1262                 goto out;
1263
1264         if (hba->cardtype == st_yel) {
1265                 data = readl(base + YI2H_INT);
1266                 if (data == 0 || data == 0xffffffff)
1267                         goto fail_out;
1268
1269                 writel(data, base + YI2H_INT_C);
1270                 stex_ss_mu_intr(hba);
1271         } else if (hba->cardtype == st_P3) {
1272                 data = readl(base + PSCRATCH4);
1273                 if (data == 0xffffffff)
1274                         goto fail_out;
1275                 if (data != 0) {
1276                         writel(data, base + PSCRATCH1);
1277                         writel((1 << 22), base + YH2I_INT);
1278                 }
1279                 stex_ss_mu_intr(hba);
1280         } else {
1281                 data = readl(base + ODBL);
1282                 if (data == 0 || data == 0xffffffff)
1283                         goto fail_out;
1284
1285                 writel(data, base + ODBL);
1286                 readl(base + ODBL); /* flush */
1287                 stex_mu_intr(hba, data);
1288         }
1289         if (hba->wait_ccb == NULL) {
1290                 printk(KERN_WARNING DRV_NAME
1291                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1292                 goto out;
1293         }
1294
1295 fail_out:
1296         scsi_dma_unmap(cmd);
1297         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1298         hba->wait_ccb = NULL;
1299         result = FAILED;
1300 out:
1301         spin_unlock_irqrestore(host->host_lock, flags);
1302         return result;
1303 }
1304
1305 static void stex_hard_reset(struct st_hba *hba)
1306 {
1307         struct pci_bus *bus;
1308         int i;
1309         u16 pci_cmd;
1310         u8 pci_bctl;
1311
1312         for (i = 0; i < 16; i++)
1313                 pci_read_config_dword(hba->pdev, i * 4,
1314                         &hba->pdev->saved_config_space[i]);
1315
1316         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1317            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1318         bus = hba->pdev->bus;
1319         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1320         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1321         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1322
1323         /*
1324          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1325          * require more time to finish bus reset. Use 100 ms here for safety
1326          */
1327         msleep(100);
1328         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1329         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1330
1331         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1332                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1333                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1334                         break;
1335                 msleep(1);
1336         }
1337
1338         ssleep(5);
1339         for (i = 0; i < 16; i++)
1340                 pci_write_config_dword(hba->pdev, i * 4,
1341                         hba->pdev->saved_config_space[i]);
1342 }
1343
1344 static int stex_yos_reset(struct st_hba *hba)
1345 {
1346         void __iomem *base;
1347         unsigned long flags, before;
1348         int ret = 0;
1349
1350         base = hba->mmio_base;
1351         writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1352         readl(base + IDBL); /* flush */
1353         before = jiffies;
1354         while (hba->out_req_cnt > 0) {
1355                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1356                         printk(KERN_WARNING DRV_NAME
1357                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1358                         ret = -1;
1359                         break;
1360                 }
1361                 msleep(1);
1362         }
1363
1364         spin_lock_irqsave(hba->host->host_lock, flags);
1365         if (ret == -1)
1366                 hba->mu_status = MU_STATE_FAILED;
1367         else
1368                 hba->mu_status = MU_STATE_STARTED;
1369         wake_up_all(&hba->reset_waitq);
1370         spin_unlock_irqrestore(hba->host->host_lock, flags);
1371
1372         return ret;
1373 }
1374
1375 static void stex_ss_reset(struct st_hba *hba)
1376 {
1377         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1378         readl(hba->mmio_base + YH2I_INT);
1379         ssleep(5);
1380 }
1381
1382 static void stex_p3_reset(struct st_hba *hba)
1383 {
1384         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1385         ssleep(5);
1386 }
1387
1388 static int stex_do_reset(struct st_hba *hba)
1389 {
1390         unsigned long flags;
1391         unsigned int mu_status = MU_STATE_RESETTING;
1392
1393         spin_lock_irqsave(hba->host->host_lock, flags);
1394         if (hba->mu_status == MU_STATE_STARTING) {
1395                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1396                 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1397                         pci_name(hba->pdev));
1398                 return 0;
1399         }
1400         while (hba->mu_status == MU_STATE_RESETTING) {
1401                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1402                 wait_event_timeout(hba->reset_waitq,
1403                                    hba->mu_status != MU_STATE_RESETTING,
1404                                    MU_MAX_DELAY * HZ);
1405                 spin_lock_irqsave(hba->host->host_lock, flags);
1406                 mu_status = hba->mu_status;
1407         }
1408
1409         if (mu_status != MU_STATE_RESETTING) {
1410                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1411                 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1412         }
1413
1414         hba->mu_status = MU_STATE_RESETTING;
1415         spin_unlock_irqrestore(hba->host->host_lock, flags);
1416
1417         if (hba->cardtype == st_yosemite)
1418                 return stex_yos_reset(hba);
1419
1420         if (hba->cardtype == st_shasta)
1421                 stex_hard_reset(hba);
1422         else if (hba->cardtype == st_yel)
1423                 stex_ss_reset(hba);
1424         else if (hba->cardtype == st_P3)
1425                 stex_p3_reset(hba);
1426
1427         return_abnormal_state(hba, DID_RESET);
1428
1429         if (stex_handshake(hba) == 0)
1430                 return 0;
1431
1432         printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1433                 pci_name(hba->pdev));
1434         return -1;
1435 }
1436
1437 static int stex_reset(struct scsi_cmnd *cmd)
1438 {
1439         struct st_hba *hba;
1440
1441         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1442
1443         shost_printk(KERN_INFO, cmd->device->host,
1444                      "resetting host\n");
1445
1446         return stex_do_reset(hba) ? FAILED : SUCCESS;
1447 }
1448
1449 static void stex_reset_work(struct work_struct *work)
1450 {
1451         struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1452
1453         stex_do_reset(hba);
1454 }
1455
1456 static int stex_biosparam(struct scsi_device *sdev,
1457         struct block_device *bdev, sector_t capacity, int geom[])
1458 {
1459         int heads = 255, sectors = 63;
1460
1461         if (capacity < 0x200000) {
1462                 heads = 64;
1463                 sectors = 32;
1464         }
1465
1466         sector_div(capacity, heads * sectors);
1467
1468         geom[0] = heads;
1469         geom[1] = sectors;
1470         geom[2] = capacity;
1471
1472         return 0;
1473 }
1474
1475 static struct scsi_host_template driver_template = {
1476         .module                         = THIS_MODULE,
1477         .name                           = DRV_NAME,
1478         .proc_name                      = DRV_NAME,
1479         .bios_param                     = stex_biosparam,
1480         .queuecommand                   = stex_queuecommand,
1481         .slave_configure                = stex_slave_config,
1482         .eh_abort_handler               = stex_abort,
1483         .eh_host_reset_handler          = stex_reset,
1484         .this_id                        = -1,
1485         .dma_boundary                   = PAGE_SIZE - 1,
1486 };
1487
1488 static struct pci_device_id stex_pci_tbl[] = {
1489         /* st_shasta */
1490         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1491                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1492         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1493                 st_shasta }, /* SuperTrak EX12350 */
1494         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1495                 st_shasta }, /* SuperTrak EX4350 */
1496         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1497                 st_shasta }, /* SuperTrak EX24350 */
1498
1499         /* st_vsc */
1500         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1501
1502         /* st_yosemite */
1503         { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1504
1505         /* st_seq */
1506         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1507
1508         /* st_yel */
1509         { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1510         { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1511
1512         /* st_P3, pluto */
1513         { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1514                 0x8870, 0, 0, st_P3 },
1515         /* st_P3, p3 */
1516         { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1517                 0x4300, 0, 0, st_P3 },
1518
1519         /* st_P3, SymplyStor4E */
1520         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1521                 0x4311, 0, 0, st_P3 },
1522         /* st_P3, SymplyStor8E */
1523         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1524                 0x4312, 0, 0, st_P3 },
1525         /* st_P3, SymplyStor4 */
1526         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1527                 0x4321, 0, 0, st_P3 },
1528         /* st_P3, SymplyStor8 */
1529         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1530                 0x4322, 0, 0, st_P3 },
1531         { }     /* terminate list */
1532 };
1533
1534 static struct st_card_info stex_card_info[] = {
1535         /* st_shasta */
1536         {
1537                 .max_id         = 17,
1538                 .max_lun        = 8,
1539                 .max_channel    = 0,
1540                 .rq_count       = 32,
1541                 .rq_size        = 1048,
1542                 .sts_count      = 32,
1543                 .alloc_rq       = stex_alloc_req,
1544                 .map_sg         = stex_map_sg,
1545                 .send           = stex_send_cmd,
1546         },
1547
1548         /* st_vsc */
1549         {
1550                 .max_id         = 129,
1551                 .max_lun        = 1,
1552                 .max_channel    = 0,
1553                 .rq_count       = 32,
1554                 .rq_size        = 1048,
1555                 .sts_count      = 32,
1556                 .alloc_rq       = stex_alloc_req,
1557                 .map_sg         = stex_map_sg,
1558                 .send           = stex_send_cmd,
1559         },
1560
1561         /* st_yosemite */
1562         {
1563                 .max_id         = 2,
1564                 .max_lun        = 256,
1565                 .max_channel    = 0,
1566                 .rq_count       = 256,
1567                 .rq_size        = 1048,
1568                 .sts_count      = 256,
1569                 .alloc_rq       = stex_alloc_req,
1570                 .map_sg         = stex_map_sg,
1571                 .send           = stex_send_cmd,
1572         },
1573
1574         /* st_seq */
1575         {
1576                 .max_id         = 129,
1577                 .max_lun        = 1,
1578                 .max_channel    = 0,
1579                 .rq_count       = 32,
1580                 .rq_size        = 1048,
1581                 .sts_count      = 32,
1582                 .alloc_rq       = stex_alloc_req,
1583                 .map_sg         = stex_map_sg,
1584                 .send           = stex_send_cmd,
1585         },
1586
1587         /* st_yel */
1588         {
1589                 .max_id         = 129,
1590                 .max_lun        = 256,
1591                 .max_channel    = 3,
1592                 .rq_count       = 801,
1593                 .rq_size        = 512,
1594                 .sts_count      = 801,
1595                 .alloc_rq       = stex_ss_alloc_req,
1596                 .map_sg         = stex_ss_map_sg,
1597                 .send           = stex_ss_send_cmd,
1598         },
1599
1600         /* st_P3 */
1601         {
1602                 .max_id         = 129,
1603                 .max_lun        = 256,
1604                 .max_channel    = 0,
1605                 .rq_count       = 801,
1606                 .rq_size        = 512,
1607                 .sts_count      = 801,
1608                 .alloc_rq       = stex_ss_alloc_req,
1609                 .map_sg         = stex_ss_map_sg,
1610                 .send           = stex_ss_send_cmd,
1611         },
1612 };
1613
1614 static int stex_request_irq(struct st_hba *hba)
1615 {
1616         struct pci_dev *pdev = hba->pdev;
1617         int status;
1618
1619         if (msi || hba->cardtype == st_P3) {
1620                 status = pci_enable_msi(pdev);
1621                 if (status != 0)
1622                         printk(KERN_ERR DRV_NAME
1623                                 "(%s): error %d setting up MSI\n",
1624                                 pci_name(pdev), status);
1625                 else
1626                         hba->msi_enabled = 1;
1627         } else
1628                 hba->msi_enabled = 0;
1629
1630         status = request_irq(pdev->irq,
1631                 (hba->cardtype == st_yel || hba->cardtype == st_P3) ?
1632                 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1633
1634         if (status != 0) {
1635                 if (hba->msi_enabled)
1636                         pci_disable_msi(pdev);
1637         }
1638         return status;
1639 }
1640
1641 static void stex_free_irq(struct st_hba *hba)
1642 {
1643         struct pci_dev *pdev = hba->pdev;
1644
1645         free_irq(pdev->irq, hba);
1646         if (hba->msi_enabled)
1647                 pci_disable_msi(pdev);
1648 }
1649
1650 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1651 {
1652         struct st_hba *hba;
1653         struct Scsi_Host *host;
1654         const struct st_card_info *ci = NULL;
1655         u32 sts_offset, cp_offset, scratch_offset;
1656         int err;
1657
1658         err = pci_enable_device(pdev);
1659         if (err)
1660                 return err;
1661
1662         pci_set_master(pdev);
1663
1664         S6flag = 0;
1665         register_reboot_notifier(&stex_notifier);
1666
1667         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1668
1669         if (!host) {
1670                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1671                         pci_name(pdev));
1672                 err = -ENOMEM;
1673                 goto out_disable;
1674         }
1675
1676         hba = (struct st_hba *)host->hostdata;
1677         memset(hba, 0, sizeof(struct st_hba));
1678
1679         err = pci_request_regions(pdev, DRV_NAME);
1680         if (err < 0) {
1681                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1682                         pci_name(pdev));
1683                 goto out_scsi_host_put;
1684         }
1685
1686         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1687         if ( !hba->mmio_base) {
1688                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1689                         pci_name(pdev));
1690                 err = -ENOMEM;
1691                 goto out_release_regions;
1692         }
1693
1694         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1695         if (err)
1696                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1697         if (err) {
1698                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1699                         pci_name(pdev));
1700                 goto out_iounmap;
1701         }
1702
1703         hba->cardtype = (unsigned int) id->driver_data;
1704         ci = &stex_card_info[hba->cardtype];
1705         switch (id->subdevice) {
1706         case 0x4221:
1707         case 0x4222:
1708         case 0x4223:
1709         case 0x4224:
1710         case 0x4225:
1711         case 0x4226:
1712         case 0x4227:
1713         case 0x4261:
1714         case 0x4262:
1715         case 0x4263:
1716         case 0x4264:
1717         case 0x4265:
1718                 break;
1719         default:
1720                 if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1721                         hba->supports_pm = 1;
1722         }
1723
1724         sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1725         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1726                 sts_offset += (ci->sts_count+1) * sizeof(u32);
1727         cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1728         hba->dma_size = cp_offset + sizeof(struct st_frame);
1729         if (hba->cardtype == st_seq ||
1730                 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1731                 hba->extra_offset = hba->dma_size;
1732                 hba->dma_size += ST_ADDITIONAL_MEM;
1733         }
1734         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1735                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1736         if (!hba->dma_mem) {
1737                 /* Retry minimum coherent mapping for st_seq and st_vsc */
1738                 if (hba->cardtype == st_seq ||
1739                     (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1740                         printk(KERN_WARNING DRV_NAME
1741                                 "(%s): allocating min buffer for controller\n",
1742                                 pci_name(pdev));
1743                         hba->dma_size = hba->extra_offset
1744                                 + ST_ADDITIONAL_MEM_MIN;
1745                         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1746                                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1747                 }
1748
1749                 if (!hba->dma_mem) {
1750                         err = -ENOMEM;
1751                         printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1752                                 pci_name(pdev));
1753                         goto out_iounmap;
1754                 }
1755         }
1756
1757         hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1758         if (!hba->ccb) {
1759                 err = -ENOMEM;
1760                 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1761                         pci_name(pdev));
1762                 goto out_pci_free;
1763         }
1764
1765         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1766                 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1767         hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1768         hba->copy_buffer = hba->dma_mem + cp_offset;
1769         hba->rq_count = ci->rq_count;
1770         hba->rq_size = ci->rq_size;
1771         hba->sts_count = ci->sts_count;
1772         hba->alloc_rq = ci->alloc_rq;
1773         hba->map_sg = ci->map_sg;
1774         hba->send = ci->send;
1775         hba->mu_status = MU_STATE_STARTING;
1776         hba->msi_lock = 0;
1777
1778         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1779                 host->sg_tablesize = 38;
1780         else
1781                 host->sg_tablesize = 32;
1782         host->can_queue = ci->rq_count;
1783         host->cmd_per_lun = ci->rq_count;
1784         host->max_id = ci->max_id;
1785         host->max_lun = ci->max_lun;
1786         host->max_channel = ci->max_channel;
1787         host->unique_id = host->host_no;
1788         host->max_cmd_len = STEX_CDB_LENGTH;
1789
1790         hba->host = host;
1791         hba->pdev = pdev;
1792         init_waitqueue_head(&hba->reset_waitq);
1793
1794         snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1795                  "stex_wq_%d", host->host_no);
1796         hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1797         if (!hba->work_q) {
1798                 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1799                         pci_name(pdev));
1800                 err = -ENOMEM;
1801                 goto out_ccb_free;
1802         }
1803         INIT_WORK(&hba->reset_work, stex_reset_work);
1804
1805         err = stex_request_irq(hba);
1806         if (err) {
1807                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1808                         pci_name(pdev));
1809                 goto out_free_wq;
1810         }
1811
1812         err = stex_handshake(hba);
1813         if (err)
1814                 goto out_free_irq;
1815
1816         pci_set_drvdata(pdev, hba);
1817
1818         err = scsi_add_host(host, &pdev->dev);
1819         if (err) {
1820                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1821                         pci_name(pdev));
1822                 goto out_free_irq;
1823         }
1824
1825         scsi_scan_host(host);
1826
1827         return 0;
1828
1829 out_free_irq:
1830         stex_free_irq(hba);
1831 out_free_wq:
1832         destroy_workqueue(hba->work_q);
1833 out_ccb_free:
1834         kfree(hba->ccb);
1835 out_pci_free:
1836         dma_free_coherent(&pdev->dev, hba->dma_size,
1837                           hba->dma_mem, hba->dma_handle);
1838 out_iounmap:
1839         iounmap(hba->mmio_base);
1840 out_release_regions:
1841         pci_release_regions(pdev);
1842 out_scsi_host_put:
1843         scsi_host_put(host);
1844 out_disable:
1845         pci_disable_device(pdev);
1846
1847         return err;
1848 }
1849
1850 static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic)
1851 {
1852         struct req_msg *req;
1853         struct st_msg_header *msg_h;
1854         unsigned long flags;
1855         unsigned long before;
1856         u16 tag = 0;
1857
1858         spin_lock_irqsave(hba->host->host_lock, flags);
1859
1860         if ((hba->cardtype == st_yel || hba->cardtype == st_P3) &&
1861                 hba->supports_pm == 1) {
1862                 if (st_sleep_mic == ST_NOTHANDLED) {
1863                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1864                         return;
1865                 }
1866         }
1867         req = hba->alloc_rq(hba);
1868         if (hba->cardtype == st_yel || hba->cardtype == st_P3) {
1869                 msg_h = (struct st_msg_header *)req - 1;
1870                 memset(msg_h, 0, hba->rq_size);
1871         } else
1872                 memset(req, 0, hba->rq_size);
1873
1874         if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel
1875                 || hba->cardtype == st_P3)
1876                 && st_sleep_mic == ST_IGNORED) {
1877                 req->cdb[0] = MGT_CMD;
1878                 req->cdb[1] = MGT_CMD_SIGNATURE;
1879                 req->cdb[2] = CTLR_CONFIG_CMD;
1880                 req->cdb[3] = CTLR_SHUTDOWN;
1881         } else if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1882                 && st_sleep_mic != ST_IGNORED) {
1883                 req->cdb[0] = MGT_CMD;
1884                 req->cdb[1] = MGT_CMD_SIGNATURE;
1885                 req->cdb[2] = CTLR_CONFIG_CMD;
1886                 req->cdb[3] = PMIC_SHUTDOWN;
1887                 req->cdb[4] = st_sleep_mic;
1888         } else {
1889                 req->cdb[0] = CONTROLLER_CMD;
1890                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1891                 req->cdb[2] = CTLR_POWER_SAVING;
1892         }
1893         hba->ccb[tag].cmd = NULL;
1894         hba->ccb[tag].sg_count = 0;
1895         hba->ccb[tag].sense_bufflen = 0;
1896         hba->ccb[tag].sense_buffer = NULL;
1897         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1898         hba->send(hba, req, tag);
1899         spin_unlock_irqrestore(hba->host->host_lock, flags);
1900         before = jiffies;
1901         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1902                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1903                         hba->ccb[tag].req_type = 0;
1904                         hba->mu_status = MU_STATE_STOP;
1905                         return;
1906                 }
1907                 msleep(1);
1908         }
1909         hba->mu_status = MU_STATE_STOP;
1910 }
1911
1912 static void stex_hba_free(struct st_hba *hba)
1913 {
1914         stex_free_irq(hba);
1915
1916         destroy_workqueue(hba->work_q);
1917
1918         iounmap(hba->mmio_base);
1919
1920         pci_release_regions(hba->pdev);
1921
1922         kfree(hba->ccb);
1923
1924         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1925                           hba->dma_mem, hba->dma_handle);
1926 }
1927
1928 static void stex_remove(struct pci_dev *pdev)
1929 {
1930         struct st_hba *hba = pci_get_drvdata(pdev);
1931
1932         hba->mu_status = MU_STATE_NOCONNECT;
1933         return_abnormal_state(hba, DID_NO_CONNECT);
1934         scsi_remove_host(hba->host);
1935
1936         scsi_block_requests(hba->host);
1937
1938         stex_hba_free(hba);
1939
1940         scsi_host_put(hba->host);
1941
1942         pci_disable_device(pdev);
1943
1944         unregister_reboot_notifier(&stex_notifier);
1945 }
1946
1947 static void stex_shutdown(struct pci_dev *pdev)
1948 {
1949         struct st_hba *hba = pci_get_drvdata(pdev);
1950
1951         if (hba->supports_pm == 0) {
1952                 stex_hba_stop(hba, ST_IGNORED);
1953         } else if (hba->supports_pm == 1 && S6flag) {
1954                 unregister_reboot_notifier(&stex_notifier);
1955                 stex_hba_stop(hba, ST_S6);
1956         } else
1957                 stex_hba_stop(hba, ST_S5);
1958 }
1959
1960 static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state)
1961 {
1962         switch (state.event) {
1963         case PM_EVENT_SUSPEND:
1964                 return ST_S3;
1965         case PM_EVENT_HIBERNATE:
1966                 hba->msi_lock = 0;
1967                 return ST_S4;
1968         default:
1969                 return ST_NOTHANDLED;
1970         }
1971 }
1972
1973 static int stex_suspend(struct pci_dev *pdev, pm_message_t state)
1974 {
1975         struct st_hba *hba = pci_get_drvdata(pdev);
1976
1977         if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1978                 && hba->supports_pm == 1)
1979                 stex_hba_stop(hba, stex_choice_sleep_mic(hba, state));
1980         else
1981                 stex_hba_stop(hba, ST_IGNORED);
1982         return 0;
1983 }
1984
1985 static int stex_resume(struct pci_dev *pdev)
1986 {
1987         struct st_hba *hba = pci_get_drvdata(pdev);
1988
1989         hba->mu_status = MU_STATE_STARTING;
1990         stex_handshake(hba);
1991         return 0;
1992 }
1993
1994 static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf)
1995 {
1996         S6flag = 1;
1997         return NOTIFY_OK;
1998 }
1999 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
2000
2001 static struct pci_driver stex_pci_driver = {
2002         .name           = DRV_NAME,
2003         .id_table       = stex_pci_tbl,
2004         .probe          = stex_probe,
2005         .remove         = stex_remove,
2006         .shutdown       = stex_shutdown,
2007         .suspend        = stex_suspend,
2008         .resume         = stex_resume,
2009 };
2010
2011 static int __init stex_init(void)
2012 {
2013         printk(KERN_INFO DRV_NAME
2014                 ": Promise SuperTrak EX Driver version: %s\n",
2015                  ST_DRIVER_VERSION);
2016
2017         return pci_register_driver(&stex_pci_driver);
2018 }
2019
2020 static void __exit stex_exit(void)
2021 {
2022         pci_unregister_driver(&stex_pci_driver);
2023 }
2024
2025 module_init(stex_init);
2026 module_exit(stex_exit);