2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
21 #include "qla_target.h"
26 char qla2x00_version_str[40];
28 static int apidev_major;
31 * SRB allocation cache
33 static struct kmem_cache *srb_cachep;
36 * CT6 CTX allocation cache
38 static struct kmem_cache *ctx_cachep;
40 * error level for logging
42 int ql_errlev = ql_log_all;
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 "Maximum number of command retries to a port that returns "
60 "a PORT-DOWN status.");
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
66 "a Fabric scan. This is needed for several broken switches. "
67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 MODULE_PARM_DESC(ql2xextended_error_logging,
84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
99 "\t\tDo LOGICAL OR of the value to enable more than one level");
101 int ql2xshiftctondsd = 6;
102 module_param(ql2xshiftctondsd, int, S_IRUGO);
103 MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
107 int ql2xfdmienable=1;
108 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
109 MODULE_PARM_DESC(ql2xfdmienable,
110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
113 #define MAX_Q_DEPTH 32
114 static int ql2xmaxqdepth = MAX_Q_DEPTH;
115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116 MODULE_PARM_DESC(ql2xmaxqdepth,
117 "Maximum queue depth to set for each LUN. "
120 int ql2xenabledif = 2;
121 module_param(ql2xenabledif, int, S_IRUGO);
122 MODULE_PARM_DESC(ql2xenabledif,
123 " Enable T10-CRC-DIF:\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
129 int ql2xenablehba_err_chk = 2;
130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131 MODULE_PARM_DESC(ql2xenablehba_err_chk,
132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
138 int ql2xiidmaenable=1;
139 module_param(ql2xiidmaenable, int, S_IRUGO);
140 MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
144 int ql2xmaxqueues = 1;
145 module_param(ql2xmaxqueues, int, S_IRUGO);
146 MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
151 int ql2xmultique_tag;
152 module_param(ql2xmultique_tag, int, S_IRUGO);
153 MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
160 MODULE_PARM_DESC(ql2xfwloadbin,
161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
168 module_param(ql2xetsenable, int, S_IRUGO);
169 MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
175 MODULE_PARM_DESC(ql2xdbwr,
176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
180 int ql2xtargetreset = 1;
181 module_param(ql2xtargetreset, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
187 module_param(ql2xgffidenable, int, S_IRUGO);
188 MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
192 int ql2xasynctmfenable;
193 module_param(ql2xasynctmfenable, int, S_IRUGO);
194 MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
198 int ql2xdontresethba;
199 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
200 MODULE_PARM_DESC(ql2xdontresethba,
201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
205 uint64_t ql2xmaxlun = MAX_LUNS;
206 module_param(ql2xmaxlun, ullong, S_IRUGO);
207 MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
211 int ql2xmdcapmask = 0x1F;
212 module_param(ql2xmdcapmask, int, S_IRUGO);
213 MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
217 int ql2xmdenable = 1;
218 module_param(ql2xmdenable, int, S_IRUGO);
219 MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
225 * SCSI host template entry points
227 static int qla2xxx_slave_configure(struct scsi_device * device);
228 static int qla2xxx_slave_alloc(struct scsi_device *);
229 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230 static void qla2xxx_scan_start(struct Scsi_Host *);
231 static void qla2xxx_slave_destroy(struct scsi_device *);
232 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
233 static int qla2xxx_eh_abort(struct scsi_cmnd *);
234 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
235 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
236 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
239 static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
240 static int qla2x00_change_queue_type(struct scsi_device *, int);
241 static void qla2x00_clear_drv_active(struct qla_hw_data *);
242 static void qla2x00_free_device(scsi_qla_host_t *);
243 static void qla83xx_disable_laser(scsi_qla_host_t *vha);
245 struct scsi_host_template qla2xxx_driver_template = {
246 .module = THIS_MODULE,
247 .name = QLA2XXX_DRIVER_NAME,
248 .queuecommand = qla2xxx_queuecommand,
250 .eh_abort_handler = qla2xxx_eh_abort,
251 .eh_device_reset_handler = qla2xxx_eh_device_reset,
252 .eh_target_reset_handler = qla2xxx_eh_target_reset,
253 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
254 .eh_host_reset_handler = qla2xxx_eh_host_reset,
256 .slave_configure = qla2xxx_slave_configure,
258 .slave_alloc = qla2xxx_slave_alloc,
259 .slave_destroy = qla2xxx_slave_destroy,
260 .scan_finished = qla2xxx_scan_finished,
261 .scan_start = qla2xxx_scan_start,
262 .change_queue_depth = qla2x00_change_queue_depth,
263 .change_queue_type = qla2x00_change_queue_type,
266 .use_clustering = ENABLE_CLUSTERING,
267 .sg_tablesize = SG_ALL,
269 .max_sectors = 0xFFFF,
270 .shost_attrs = qla2x00_host_attrs,
272 .supported_mode = MODE_INITIATOR,
275 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
276 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
278 /* TODO Convert to inlines
284 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
286 init_timer(&vha->timer);
287 vha->timer.expires = jiffies + interval * HZ;
288 vha->timer.data = (unsigned long)vha;
289 vha->timer.function = (void (*)(unsigned long))func;
290 add_timer(&vha->timer);
291 vha->timer_active = 1;
295 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
297 /* Currently used for 82XX only. */
298 if (vha->device_flags & DFLG_DEV_FAILED) {
299 ql_dbg(ql_dbg_timer, vha, 0x600d,
300 "Device in a failed state, returning.\n");
304 mod_timer(&vha->timer, jiffies + interval * HZ);
307 static __inline__ void
308 qla2x00_stop_timer(scsi_qla_host_t *vha)
310 del_timer_sync(&vha->timer);
311 vha->timer_active = 0;
314 static int qla2x00_do_dpc(void *data);
316 static void qla2x00_rst_aen(scsi_qla_host_t *);
318 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
319 struct req_que **, struct rsp_que **);
320 static void qla2x00_free_fw_dump(struct qla_hw_data *);
321 static void qla2x00_mem_free(struct qla_hw_data *);
323 /* -------------------------------------------------------------------------- */
324 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
327 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
328 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
330 if (!ha->req_q_map) {
331 ql_log(ql_log_fatal, vha, 0x003b,
332 "Unable to allocate memory for request queue ptrs.\n");
336 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
338 if (!ha->rsp_q_map) {
339 ql_log(ql_log_fatal, vha, 0x003c,
340 "Unable to allocate memory for response queue ptrs.\n");
344 * Make sure we record at least the request and response queue zero in
345 * case we need to free them if part of the probe fails.
347 ha->rsp_q_map[0] = rsp;
348 ha->req_q_map[0] = req;
349 set_bit(0, ha->rsp_qid_map);
350 set_bit(0, ha->req_qid_map);
354 kfree(ha->req_q_map);
355 ha->req_q_map = NULL;
360 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
362 if (IS_QLAFX00(ha)) {
363 if (req && req->ring_fx00)
364 dma_free_coherent(&ha->pdev->dev,
365 (req->length_fx00 + 1) * sizeof(request_t),
366 req->ring_fx00, req->dma_fx00);
367 } else if (req && req->ring)
368 dma_free_coherent(&ha->pdev->dev,
369 (req->length + 1) * sizeof(request_t),
370 req->ring, req->dma);
373 kfree(req->outstanding_cmds);
379 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
381 if (IS_QLAFX00(ha)) {
382 if (rsp && rsp->ring)
383 dma_free_coherent(&ha->pdev->dev,
384 (rsp->length_fx00 + 1) * sizeof(request_t),
385 rsp->ring_fx00, rsp->dma_fx00);
386 } else if (rsp && rsp->ring) {
387 dma_free_coherent(&ha->pdev->dev,
388 (rsp->length + 1) * sizeof(response_t),
389 rsp->ring, rsp->dma);
395 static void qla2x00_free_queues(struct qla_hw_data *ha)
401 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
402 req = ha->req_q_map[cnt];
403 qla2x00_free_req_que(ha, req);
405 kfree(ha->req_q_map);
406 ha->req_q_map = NULL;
408 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
409 rsp = ha->rsp_q_map[cnt];
410 qla2x00_free_rsp_que(ha, rsp);
412 kfree(ha->rsp_q_map);
413 ha->rsp_q_map = NULL;
416 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
418 uint16_t options = 0;
420 struct qla_hw_data *ha = vha->hw;
422 if (!(ha->fw_attributes & BIT_6)) {
423 ql_log(ql_log_warn, vha, 0x00d8,
424 "Firmware is not multi-queue capable.\n");
427 if (ql2xmultique_tag) {
428 /* create a request queue for IO */
430 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
431 QLA_DEFAULT_QUE_QOS);
433 ql_log(ql_log_warn, vha, 0x00e0,
434 "Failed to create request queue.\n");
437 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
438 vha->req = ha->req_q_map[req];
440 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
441 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
443 ql_log(ql_log_warn, vha, 0x00e8,
444 "Failed to create response queue.\n");
448 ha->flags.cpu_affinity_enabled = 1;
449 ql_dbg(ql_dbg_multiq, vha, 0xc007,
450 "CPU affinity mode enalbed, "
451 "no. of response queues:%d no. of request queues:%d.\n",
452 ha->max_rsp_queues, ha->max_req_queues);
453 ql_dbg(ql_dbg_init, vha, 0x00e9,
454 "CPU affinity mode enalbed, "
455 "no. of response queues:%d no. of request queues:%d.\n",
456 ha->max_rsp_queues, ha->max_req_queues);
460 qla25xx_delete_queues(vha);
461 destroy_workqueue(ha->wq);
463 vha->req = ha->req_q_map[0];
466 kfree(ha->req_q_map);
467 kfree(ha->rsp_q_map);
468 ha->max_req_queues = ha->max_rsp_queues = 1;
473 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
475 struct qla_hw_data *ha = vha->hw;
476 static char *pci_bus_modes[] = {
477 "33", "66", "100", "133",
482 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
485 strcat(str, pci_bus_modes[pci_bus]);
487 pci_bus = (ha->pci_attr & BIT_8) >> 8;
489 strcat(str, pci_bus_modes[pci_bus]);
491 strcat(str, " MHz)");
497 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
499 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
500 struct qla_hw_data *ha = vha->hw;
503 if (pci_is_pcie(ha->pdev)) {
505 uint32_t lstat, lspeed, lwidth;
507 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
508 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
509 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
511 strcpy(str, "PCIe (");
514 strcat(str, "2.5GT/s ");
517 strcat(str, "5.0GT/s ");
520 strcat(str, "8.0GT/s ");
523 strcat(str, "<unknown> ");
526 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
533 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
534 if (pci_bus == 0 || pci_bus == 8) {
536 strcat(str, pci_bus_modes[pci_bus >> 3]);
540 strcat(str, "Mode 2");
542 strcat(str, "Mode 1");
544 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
546 strcat(str, " MHz)");
552 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
555 struct qla_hw_data *ha = vha->hw;
557 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
558 ha->fw_minor_version, ha->fw_subminor_version);
560 if (ha->fw_attributes & BIT_9) {
565 switch (ha->fw_attributes & 0xFF) {
579 sprintf(un_str, "(%x)", ha->fw_attributes);
583 if (ha->fw_attributes & 0x100)
590 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
592 struct qla_hw_data *ha = vha->hw;
594 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
595 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
600 qla2x00_sp_free_dma(void *vha, void *ptr)
602 srb_t *sp = (srb_t *)ptr;
603 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
604 struct qla_hw_data *ha = sp->fcport->vha->hw;
605 void *ctx = GET_CMD_CTX_SP(sp);
607 if (sp->flags & SRB_DMA_VALID) {
609 sp->flags &= ~SRB_DMA_VALID;
612 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
613 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
614 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
615 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
618 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
619 /* List assured to be having elements */
620 qla2x00_clean_dsd_pool(ha, sp, NULL);
621 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
624 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
625 dma_pool_free(ha->dl_dma_pool, ctx,
626 ((struct crc_context *)ctx)->crc_ctx_dma);
627 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
630 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
631 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
633 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
635 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
636 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
637 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
638 mempool_free(ctx1, ha->ctx_mempool);
643 qla2x00_rel_sp(sp->fcport->vha, sp);
647 qla2x00_sp_compl(void *data, void *ptr, int res)
649 struct qla_hw_data *ha = (struct qla_hw_data *)data;
650 srb_t *sp = (srb_t *)ptr;
651 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
655 if (atomic_read(&sp->ref_count) == 0) {
656 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
657 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
659 if (ql2xextended_error_logging & ql_dbg_io)
663 if (!atomic_dec_and_test(&sp->ref_count))
666 qla2x00_sp_free_dma(ha, sp);
670 /* If we are SP1 here, we need to still take and release the host_lock as SP1
671 * does not have the changes necessary to avoid taking host->host_lock.
674 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
676 scsi_qla_host_t *vha = shost_priv(host);
677 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
678 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
679 struct qla_hw_data *ha = vha->hw;
680 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
684 if (ha->flags.eeh_busy) {
685 if (ha->flags.pci_channel_io_perm_failure) {
686 ql_dbg(ql_dbg_aer, vha, 0x9010,
687 "PCI Channel IO permanent failure, exiting "
689 cmd->result = DID_NO_CONNECT << 16;
691 ql_dbg(ql_dbg_aer, vha, 0x9011,
692 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
693 cmd->result = DID_REQUEUE << 16;
695 goto qc24_fail_command;
698 rval = fc_remote_port_chkready(rport);
701 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
702 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
704 goto qc24_fail_command;
707 if (!vha->flags.difdix_supported &&
708 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
709 ql_dbg(ql_dbg_io, vha, 0x3004,
710 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
712 cmd->result = DID_NO_CONNECT << 16;
713 goto qc24_fail_command;
717 cmd->result = DID_NO_CONNECT << 16;
718 goto qc24_fail_command;
721 if (atomic_read(&fcport->state) != FCS_ONLINE) {
722 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
723 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
724 ql_dbg(ql_dbg_io, vha, 0x3005,
725 "Returning DNC, fcport_state=%d loop_state=%d.\n",
726 atomic_read(&fcport->state),
727 atomic_read(&base_vha->loop_state));
728 cmd->result = DID_NO_CONNECT << 16;
729 goto qc24_fail_command;
731 goto qc24_target_busy;
735 * Return target busy if we've received a non-zero retry_delay_timer
738 if (time_after(jiffies, fcport->retry_delay_timestamp))
739 fcport->retry_delay_timestamp = 0;
741 goto qc24_target_busy;
743 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
747 sp->u.scmd.cmd = cmd;
748 sp->type = SRB_SCSI_CMD;
749 atomic_set(&sp->ref_count, 1);
750 CMD_SP(cmd) = (void *)sp;
751 sp->free = qla2x00_sp_free_dma;
752 sp->done = qla2x00_sp_compl;
754 rval = ha->isp_ops->start_scsi(sp);
755 if (rval != QLA_SUCCESS) {
756 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
757 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
758 goto qc24_host_busy_free_sp;
763 qc24_host_busy_free_sp:
764 qla2x00_sp_free_dma(ha, sp);
767 return SCSI_MLQUEUE_HOST_BUSY;
770 return SCSI_MLQUEUE_TARGET_BUSY;
779 * qla2x00_eh_wait_on_command
780 * Waits for the command to be returned by the Firmware for some
784 * cmd = Scsi Command to wait on.
791 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
793 #define ABORT_POLLING_PERIOD 1000
794 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
795 unsigned long wait_iter = ABORT_WAIT_ITER;
796 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
797 struct qla_hw_data *ha = vha->hw;
798 int ret = QLA_SUCCESS;
800 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
801 ql_dbg(ql_dbg_taskm, vha, 0x8005,
802 "Return:eh_wait.\n");
806 while (CMD_SP(cmd) && wait_iter--) {
807 msleep(ABORT_POLLING_PERIOD);
810 ret = QLA_FUNCTION_FAILED;
816 * qla2x00_wait_for_hba_online
817 * Wait till the HBA is online after going through
818 * <= MAX_RETRIES_OF_ISP_ABORT or
819 * finally HBA is disabled ie marked offline
822 * ha - pointer to host adapter structure
825 * Does context switching-Release SPIN_LOCK
826 * (if any) before calling this routine.
829 * Success (Adapter is online) : 0
830 * Failed (Adapter is offline/disabled) : 1
833 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
836 unsigned long wait_online;
837 struct qla_hw_data *ha = vha->hw;
838 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
840 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
841 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
842 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
843 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
844 ha->dpc_active) && time_before(jiffies, wait_online)) {
848 if (base_vha->flags.online)
849 return_status = QLA_SUCCESS;
851 return_status = QLA_FUNCTION_FAILED;
853 return (return_status);
857 * qla2x00_wait_for_hba_ready
858 * Wait till the HBA is ready before doing driver unload
861 * ha - pointer to host adapter structure
864 * Does context switching-Release SPIN_LOCK
865 * (if any) before calling this routine.
869 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
871 struct qla_hw_data *ha = vha->hw;
873 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
874 ha->flags.mbox_busy) ||
875 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
876 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
881 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
884 unsigned long wait_reset;
885 struct qla_hw_data *ha = vha->hw;
886 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
888 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
889 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
890 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
891 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
892 ha->dpc_active) && time_before(jiffies, wait_reset)) {
896 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
897 ha->flags.chip_reset_done)
900 if (ha->flags.chip_reset_done)
901 return_status = QLA_SUCCESS;
903 return_status = QLA_FUNCTION_FAILED;
905 return return_status;
909 sp_get(struct srb *sp)
911 atomic_inc(&sp->ref_count);
914 /**************************************************************************
918 * The abort function will abort the specified command.
921 * cmd = Linux SCSI command packet to be aborted.
924 * Either SUCCESS or FAILED.
927 * Only return FAILED if command not returned by firmware.
928 **************************************************************************/
930 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
932 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
939 struct qla_hw_data *ha = vha->hw;
944 ret = fc_block_scsi_eh(cmd);
949 id = cmd->device->id;
950 lun = cmd->device->lun;
952 spin_lock_irqsave(&ha->hardware_lock, flags);
953 sp = (srb_t *) CMD_SP(cmd);
955 spin_unlock_irqrestore(&ha->hardware_lock, flags);
959 ql_dbg(ql_dbg_taskm, vha, 0x8002,
960 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n",
961 vha->host_no, id, lun, sp, cmd);
963 /* Get a reference to the sp and drop the lock.*/
966 spin_unlock_irqrestore(&ha->hardware_lock, flags);
967 rval = ha->isp_ops->abort_command(sp);
969 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
971 * Decrement the ref_count since we can't find the
974 atomic_dec(&sp->ref_count);
979 ql_dbg(ql_dbg_taskm, vha, 0x8003,
980 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
982 ql_dbg(ql_dbg_taskm, vha, 0x8004,
983 "Abort command mbx success cmd=%p.\n", cmd);
987 spin_lock_irqsave(&ha->hardware_lock, flags);
989 * Clear the slot in the oustanding_cmds array if we can't find the
990 * command to reclaim the resources.
992 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
993 vha->req->outstanding_cmds[sp->handle] = NULL;
995 spin_unlock_irqrestore(&ha->hardware_lock, flags);
997 /* Did the command return during mailbox execution? */
998 if (ret == FAILED && !CMD_SP(cmd))
1001 /* Wait for the command to be returned. */
1003 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
1004 ql_log(ql_log_warn, vha, 0x8006,
1005 "Abort handler timed out cmd=%p.\n", cmd);
1010 ql_log(ql_log_info, vha, 0x801c,
1011 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
1012 vha->host_no, id, lun, wait, ret);
1018 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1019 uint64_t l, enum nexus_wait_type type)
1021 int cnt, match, status;
1022 unsigned long flags;
1023 struct qla_hw_data *ha = vha->hw;
1024 struct req_que *req;
1026 struct scsi_cmnd *cmd;
1028 status = QLA_SUCCESS;
1030 spin_lock_irqsave(&ha->hardware_lock, flags);
1032 for (cnt = 1; status == QLA_SUCCESS &&
1033 cnt < req->num_outstanding_cmds; cnt++) {
1034 sp = req->outstanding_cmds[cnt];
1037 if (sp->type != SRB_SCSI_CMD)
1039 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1042 cmd = GET_CMD_SP(sp);
1048 match = cmd->device->id == t;
1051 match = (cmd->device->id == t &&
1052 cmd->device->lun == l);
1058 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1059 status = qla2x00_eh_wait_on_command(cmd);
1060 spin_lock_irqsave(&ha->hardware_lock, flags);
1062 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1067 static char *reset_errors[] = {
1070 "Task management failed",
1071 "Waiting for command completions",
1075 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1076 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1078 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1079 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1086 err = fc_block_scsi_eh(cmd);
1090 ql_log(ql_log_info, vha, 0x8009,
1091 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1092 cmd->device->id, cmd->device->lun, cmd);
1095 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1096 ql_log(ql_log_warn, vha, 0x800a,
1097 "Wait for hba online failed for cmd=%p.\n", cmd);
1098 goto eh_reset_failed;
1101 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1103 ql_log(ql_log_warn, vha, 0x800c,
1104 "do_reset failed for cmd=%p.\n", cmd);
1105 goto eh_reset_failed;
1108 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1109 cmd->device->lun, type) != QLA_SUCCESS) {
1110 ql_log(ql_log_warn, vha, 0x800d,
1111 "wait for pending cmds failed for cmd=%p.\n", cmd);
1112 goto eh_reset_failed;
1115 ql_log(ql_log_info, vha, 0x800e,
1116 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1117 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1122 ql_log(ql_log_info, vha, 0x800f,
1123 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1124 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1130 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1132 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1133 struct qla_hw_data *ha = vha->hw;
1135 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1136 ha->isp_ops->lun_reset);
1140 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1142 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1143 struct qla_hw_data *ha = vha->hw;
1145 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1146 ha->isp_ops->target_reset);
1149 /**************************************************************************
1150 * qla2xxx_eh_bus_reset
1153 * The bus reset function will reset the bus and abort any executing
1157 * cmd = Linux SCSI command packet of the command that cause the
1161 * SUCCESS/FAILURE (defined as macro in scsi.h).
1163 **************************************************************************/
1165 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1167 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1168 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1173 id = cmd->device->id;
1174 lun = cmd->device->lun;
1180 ret = fc_block_scsi_eh(cmd);
1185 ql_log(ql_log_info, vha, 0x8012,
1186 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1188 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1189 ql_log(ql_log_fatal, vha, 0x8013,
1190 "Wait for hba online failed board disabled.\n");
1191 goto eh_bus_reset_done;
1194 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1198 goto eh_bus_reset_done;
1200 /* Flush outstanding commands. */
1201 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1203 ql_log(ql_log_warn, vha, 0x8014,
1204 "Wait for pending commands failed.\n");
1209 ql_log(ql_log_warn, vha, 0x802b,
1210 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1211 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1216 /**************************************************************************
1217 * qla2xxx_eh_host_reset
1220 * The reset function will reset the Adapter.
1223 * cmd = Linux SCSI command packet of the command that cause the
1227 * Either SUCCESS or FAILED.
1230 **************************************************************************/
1232 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1234 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1235 struct qla_hw_data *ha = vha->hw;
1239 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1241 id = cmd->device->id;
1242 lun = cmd->device->lun;
1244 ql_log(ql_log_info, vha, 0x8018,
1245 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1248 * No point in issuing another reset if one is active. Also do not
1249 * attempt a reset if we are updating flash.
1251 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1252 goto eh_host_reset_lock;
1254 if (vha != base_vha) {
1255 if (qla2x00_vp_abort_isp(vha))
1256 goto eh_host_reset_lock;
1258 if (IS_P3P_TYPE(vha->hw)) {
1259 if (!qla82xx_fcoe_ctx_reset(vha)) {
1260 /* Ctx reset success */
1262 goto eh_host_reset_lock;
1264 /* fall thru if ctx reset failed */
1267 flush_workqueue(ha->wq);
1269 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1270 if (ha->isp_ops->abort_isp(base_vha)) {
1271 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1272 /* failed. schedule dpc to try */
1273 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1275 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1276 ql_log(ql_log_warn, vha, 0x802a,
1277 "wait for hba online failed.\n");
1278 goto eh_host_reset_lock;
1281 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1284 /* Waiting for command to be returned to OS.*/
1285 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1290 ql_log(ql_log_info, vha, 0x8017,
1291 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1292 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1298 * qla2x00_loop_reset
1302 * ha = adapter block pointer.
1308 qla2x00_loop_reset(scsi_qla_host_t *vha)
1311 struct fc_port *fcport;
1312 struct qla_hw_data *ha = vha->hw;
1314 if (IS_QLAFX00(ha)) {
1315 return qlafx00_loop_reset(vha);
1318 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1319 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1320 if (fcport->port_type != FCT_TARGET)
1323 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1324 if (ret != QLA_SUCCESS) {
1325 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1326 "Bus Reset failed: Reset=%d "
1327 "d_id=%x.\n", ret, fcport->d_id.b24);
1333 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1334 atomic_set(&vha->loop_state, LOOP_DOWN);
1335 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1336 qla2x00_mark_all_devices_lost(vha, 0);
1337 ret = qla2x00_full_login_lip(vha);
1338 if (ret != QLA_SUCCESS) {
1339 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1340 "full_login_lip=%d.\n", ret);
1344 if (ha->flags.enable_lip_reset) {
1345 ret = qla2x00_lip_reset(vha);
1346 if (ret != QLA_SUCCESS)
1347 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1348 "lip_reset failed (%d).\n", ret);
1351 /* Issue marker command only when we are going to start the I/O */
1352 vha->marker_needed = 1;
1358 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1361 unsigned long flags;
1363 struct qla_hw_data *ha = vha->hw;
1364 struct req_que *req;
1366 spin_lock_irqsave(&ha->hardware_lock, flags);
1367 for (que = 0; que < ha->max_req_queues; que++) {
1368 req = ha->req_q_map[que];
1371 if (!req->outstanding_cmds)
1373 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1374 sp = req->outstanding_cmds[cnt];
1376 req->outstanding_cmds[cnt] = NULL;
1377 sp->done(vha, sp, res);
1381 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1385 qla2xxx_slave_alloc(struct scsi_device *sdev)
1387 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1389 if (!rport || fc_remote_port_chkready(rport))
1392 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1398 qla2xxx_slave_configure(struct scsi_device *sdev)
1400 scsi_qla_host_t *vha = shost_priv(sdev->host);
1401 struct req_que *req = vha->req;
1403 if (IS_T10_PI_CAPABLE(vha->hw))
1404 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1406 if (sdev->tagged_supported)
1407 scsi_activate_tcq(sdev, req->max_q_depth);
1409 scsi_deactivate_tcq(sdev, req->max_q_depth);
1414 qla2xxx_slave_destroy(struct scsi_device *sdev)
1416 sdev->hostdata = NULL;
1419 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1421 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1423 if (!scsi_track_queue_full(sdev, qdepth))
1426 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1427 "Queue depth adjusted-down to %d for nexus=%ld:%d:%llu.\n",
1428 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1431 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1433 fc_port_t *fcport = sdev->hostdata;
1434 struct scsi_qla_host *vha = fcport->vha;
1435 struct req_que *req = NULL;
1441 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1444 if (sdev->ordered_tags)
1445 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1447 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1449 ql_dbg(ql_dbg_io, vha, 0x302a,
1450 "Queue depth adjusted-up to %d for nexus=%ld:%d:%llu.\n",
1451 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1455 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
1458 case SCSI_QDEPTH_DEFAULT:
1459 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1461 case SCSI_QDEPTH_QFULL:
1462 qla2x00_handle_queue_full(sdev, qdepth);
1464 case SCSI_QDEPTH_RAMP_UP:
1465 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1471 return sdev->queue_depth;
1475 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1477 if (sdev->tagged_supported) {
1478 scsi_set_tag_type(sdev, tag_type);
1480 scsi_activate_tcq(sdev, sdev->queue_depth);
1482 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1490 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1493 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1494 * supported addressing method.
1497 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1499 /* Assume a 32bit DMA mask. */
1500 ha->flags.enable_64bit_addressing = 0;
1502 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1503 /* Any upper-dword bits set? */
1504 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1505 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1506 /* Ok, a 64bit DMA mask is applicable. */
1507 ha->flags.enable_64bit_addressing = 1;
1508 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1509 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1514 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1515 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1519 qla2x00_enable_intrs(struct qla_hw_data *ha)
1521 unsigned long flags = 0;
1522 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1524 spin_lock_irqsave(&ha->hardware_lock, flags);
1525 ha->interrupts_on = 1;
1526 /* enable risc and host interrupts */
1527 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
1528 RD_REG_WORD(®->ictrl);
1529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1534 qla2x00_disable_intrs(struct qla_hw_data *ha)
1536 unsigned long flags = 0;
1537 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1539 spin_lock_irqsave(&ha->hardware_lock, flags);
1540 ha->interrupts_on = 0;
1541 /* disable risc and host interrupts */
1542 WRT_REG_WORD(®->ictrl, 0);
1543 RD_REG_WORD(®->ictrl);
1544 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1548 qla24xx_enable_intrs(struct qla_hw_data *ha)
1550 unsigned long flags = 0;
1551 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1553 spin_lock_irqsave(&ha->hardware_lock, flags);
1554 ha->interrupts_on = 1;
1555 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT);
1556 RD_REG_DWORD(®->ictrl);
1557 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1561 qla24xx_disable_intrs(struct qla_hw_data *ha)
1563 unsigned long flags = 0;
1564 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1566 if (IS_NOPOLLING_TYPE(ha))
1568 spin_lock_irqsave(&ha->hardware_lock, flags);
1569 ha->interrupts_on = 0;
1570 WRT_REG_DWORD(®->ictrl, 0);
1571 RD_REG_DWORD(®->ictrl);
1572 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1576 qla2x00_iospace_config(struct qla_hw_data *ha)
1578 resource_size_t pio;
1582 if (pci_request_selected_regions(ha->pdev, ha->bars,
1583 QLA2XXX_DRIVER_NAME)) {
1584 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1585 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1586 pci_name(ha->pdev));
1587 goto iospace_error_exit;
1589 if (!(ha->bars & 1))
1592 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1593 pio = pci_resource_start(ha->pdev, 0);
1594 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1595 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1596 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1597 "Invalid pci I/O region size (%s).\n",
1598 pci_name(ha->pdev));
1602 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1603 "Region #0 no a PIO resource (%s).\n",
1604 pci_name(ha->pdev));
1607 ha->pio_address = pio;
1608 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1609 "PIO address=%llu.\n",
1610 (unsigned long long)ha->pio_address);
1613 /* Use MMIO operations for all accesses. */
1614 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1615 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1616 "Region #1 not an MMIO resource (%s), aborting.\n",
1617 pci_name(ha->pdev));
1618 goto iospace_error_exit;
1620 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1621 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1622 "Invalid PCI mem region size (%s), aborting.\n",
1623 pci_name(ha->pdev));
1624 goto iospace_error_exit;
1627 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1629 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1630 "Cannot remap MMIO (%s), aborting.\n",
1631 pci_name(ha->pdev));
1632 goto iospace_error_exit;
1635 /* Determine queue resources */
1636 ha->max_req_queues = ha->max_rsp_queues = 1;
1637 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1638 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1639 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1642 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1643 pci_resource_len(ha->pdev, 3));
1645 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1646 "MQIO Base=%p.\n", ha->mqiobase);
1647 /* Read MSIX vector size of the board */
1648 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1649 ha->msix_count = msix;
1650 /* Max queues are bounded by available msix vectors */
1651 /* queue 0 uses two msix vectors */
1652 if (ql2xmultique_tag) {
1653 cpus = num_online_cpus();
1654 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1655 (cpus + 1) : (ha->msix_count - 1);
1656 ha->max_req_queues = 2;
1657 } else if (ql2xmaxqueues > 1) {
1658 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1659 QLA_MQ_SIZE : ql2xmaxqueues;
1660 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1661 "QoS mode set, max no of request queues:%d.\n",
1662 ha->max_req_queues);
1663 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1664 "QoS mode set, max no of request queues:%d.\n",
1665 ha->max_req_queues);
1667 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1668 "MSI-X vector count: %d.\n", msix);
1670 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1671 "BAR 3 not enabled.\n");
1674 ha->msix_count = ha->max_rsp_queues + 1;
1675 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1676 "MSIX Count:%d.\n", ha->msix_count);
1685 qla83xx_iospace_config(struct qla_hw_data *ha)
1690 if (pci_request_selected_regions(ha->pdev, ha->bars,
1691 QLA2XXX_DRIVER_NAME)) {
1692 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1693 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1694 pci_name(ha->pdev));
1696 goto iospace_error_exit;
1699 /* Use MMIO operations for all accesses. */
1700 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1701 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1702 "Invalid pci I/O region size (%s).\n",
1703 pci_name(ha->pdev));
1704 goto iospace_error_exit;
1706 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1707 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1708 "Invalid PCI mem region size (%s), aborting\n",
1709 pci_name(ha->pdev));
1710 goto iospace_error_exit;
1713 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1715 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1716 "Cannot remap MMIO (%s), aborting.\n",
1717 pci_name(ha->pdev));
1718 goto iospace_error_exit;
1721 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1722 /* 83XX 26XX always use MQ type access for queues
1723 * - mbar 2, a.k.a region 4 */
1724 ha->max_req_queues = ha->max_rsp_queues = 1;
1725 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1726 pci_resource_len(ha->pdev, 4));
1728 if (!ha->mqiobase) {
1729 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1730 "BAR2/region4 not enabled\n");
1734 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1735 pci_resource_len(ha->pdev, 2));
1737 /* Read MSIX vector size of the board */
1738 pci_read_config_word(ha->pdev,
1739 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1740 ha->msix_count = msix;
1741 /* Max queues are bounded by available msix vectors */
1742 /* queue 0 uses two msix vectors */
1743 if (ql2xmultique_tag) {
1744 cpus = num_online_cpus();
1745 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1746 (cpus + 1) : (ha->msix_count - 1);
1747 ha->max_req_queues = 2;
1748 } else if (ql2xmaxqueues > 1) {
1749 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1750 QLA_MQ_SIZE : ql2xmaxqueues;
1751 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1752 "QoS mode set, max no of request queues:%d.\n",
1753 ha->max_req_queues);
1754 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1755 "QoS mode set, max no of request queues:%d.\n",
1756 ha->max_req_queues);
1758 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1759 "MSI-X vector count: %d.\n", msix);
1761 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1762 "BAR 1 not enabled.\n");
1765 ha->msix_count = ha->max_rsp_queues + 1;
1767 qlt_83xx_iospace_config(ha);
1769 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1770 "MSIX Count:%d.\n", ha->msix_count);
1777 static struct isp_operations qla2100_isp_ops = {
1778 .pci_config = qla2100_pci_config,
1779 .reset_chip = qla2x00_reset_chip,
1780 .chip_diag = qla2x00_chip_diag,
1781 .config_rings = qla2x00_config_rings,
1782 .reset_adapter = qla2x00_reset_adapter,
1783 .nvram_config = qla2x00_nvram_config,
1784 .update_fw_options = qla2x00_update_fw_options,
1785 .load_risc = qla2x00_load_risc,
1786 .pci_info_str = qla2x00_pci_info_str,
1787 .fw_version_str = qla2x00_fw_version_str,
1788 .intr_handler = qla2100_intr_handler,
1789 .enable_intrs = qla2x00_enable_intrs,
1790 .disable_intrs = qla2x00_disable_intrs,
1791 .abort_command = qla2x00_abort_command,
1792 .target_reset = qla2x00_abort_target,
1793 .lun_reset = qla2x00_lun_reset,
1794 .fabric_login = qla2x00_login_fabric,
1795 .fabric_logout = qla2x00_fabric_logout,
1796 .calc_req_entries = qla2x00_calc_iocbs_32,
1797 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1798 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1799 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1800 .read_nvram = qla2x00_read_nvram_data,
1801 .write_nvram = qla2x00_write_nvram_data,
1802 .fw_dump = qla2100_fw_dump,
1805 .beacon_blink = NULL,
1806 .read_optrom = qla2x00_read_optrom_data,
1807 .write_optrom = qla2x00_write_optrom_data,
1808 .get_flash_version = qla2x00_get_flash_version,
1809 .start_scsi = qla2x00_start_scsi,
1810 .abort_isp = qla2x00_abort_isp,
1811 .iospace_config = qla2x00_iospace_config,
1812 .initialize_adapter = qla2x00_initialize_adapter,
1815 static struct isp_operations qla2300_isp_ops = {
1816 .pci_config = qla2300_pci_config,
1817 .reset_chip = qla2x00_reset_chip,
1818 .chip_diag = qla2x00_chip_diag,
1819 .config_rings = qla2x00_config_rings,
1820 .reset_adapter = qla2x00_reset_adapter,
1821 .nvram_config = qla2x00_nvram_config,
1822 .update_fw_options = qla2x00_update_fw_options,
1823 .load_risc = qla2x00_load_risc,
1824 .pci_info_str = qla2x00_pci_info_str,
1825 .fw_version_str = qla2x00_fw_version_str,
1826 .intr_handler = qla2300_intr_handler,
1827 .enable_intrs = qla2x00_enable_intrs,
1828 .disable_intrs = qla2x00_disable_intrs,
1829 .abort_command = qla2x00_abort_command,
1830 .target_reset = qla2x00_abort_target,
1831 .lun_reset = qla2x00_lun_reset,
1832 .fabric_login = qla2x00_login_fabric,
1833 .fabric_logout = qla2x00_fabric_logout,
1834 .calc_req_entries = qla2x00_calc_iocbs_32,
1835 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1836 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1837 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1838 .read_nvram = qla2x00_read_nvram_data,
1839 .write_nvram = qla2x00_write_nvram_data,
1840 .fw_dump = qla2300_fw_dump,
1841 .beacon_on = qla2x00_beacon_on,
1842 .beacon_off = qla2x00_beacon_off,
1843 .beacon_blink = qla2x00_beacon_blink,
1844 .read_optrom = qla2x00_read_optrom_data,
1845 .write_optrom = qla2x00_write_optrom_data,
1846 .get_flash_version = qla2x00_get_flash_version,
1847 .start_scsi = qla2x00_start_scsi,
1848 .abort_isp = qla2x00_abort_isp,
1849 .iospace_config = qla2x00_iospace_config,
1850 .initialize_adapter = qla2x00_initialize_adapter,
1853 static struct isp_operations qla24xx_isp_ops = {
1854 .pci_config = qla24xx_pci_config,
1855 .reset_chip = qla24xx_reset_chip,
1856 .chip_diag = qla24xx_chip_diag,
1857 .config_rings = qla24xx_config_rings,
1858 .reset_adapter = qla24xx_reset_adapter,
1859 .nvram_config = qla24xx_nvram_config,
1860 .update_fw_options = qla24xx_update_fw_options,
1861 .load_risc = qla24xx_load_risc,
1862 .pci_info_str = qla24xx_pci_info_str,
1863 .fw_version_str = qla24xx_fw_version_str,
1864 .intr_handler = qla24xx_intr_handler,
1865 .enable_intrs = qla24xx_enable_intrs,
1866 .disable_intrs = qla24xx_disable_intrs,
1867 .abort_command = qla24xx_abort_command,
1868 .target_reset = qla24xx_abort_target,
1869 .lun_reset = qla24xx_lun_reset,
1870 .fabric_login = qla24xx_login_fabric,
1871 .fabric_logout = qla24xx_fabric_logout,
1872 .calc_req_entries = NULL,
1873 .build_iocbs = NULL,
1874 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1875 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1876 .read_nvram = qla24xx_read_nvram_data,
1877 .write_nvram = qla24xx_write_nvram_data,
1878 .fw_dump = qla24xx_fw_dump,
1879 .beacon_on = qla24xx_beacon_on,
1880 .beacon_off = qla24xx_beacon_off,
1881 .beacon_blink = qla24xx_beacon_blink,
1882 .read_optrom = qla24xx_read_optrom_data,
1883 .write_optrom = qla24xx_write_optrom_data,
1884 .get_flash_version = qla24xx_get_flash_version,
1885 .start_scsi = qla24xx_start_scsi,
1886 .abort_isp = qla2x00_abort_isp,
1887 .iospace_config = qla2x00_iospace_config,
1888 .initialize_adapter = qla2x00_initialize_adapter,
1891 static struct isp_operations qla25xx_isp_ops = {
1892 .pci_config = qla25xx_pci_config,
1893 .reset_chip = qla24xx_reset_chip,
1894 .chip_diag = qla24xx_chip_diag,
1895 .config_rings = qla24xx_config_rings,
1896 .reset_adapter = qla24xx_reset_adapter,
1897 .nvram_config = qla24xx_nvram_config,
1898 .update_fw_options = qla24xx_update_fw_options,
1899 .load_risc = qla24xx_load_risc,
1900 .pci_info_str = qla24xx_pci_info_str,
1901 .fw_version_str = qla24xx_fw_version_str,
1902 .intr_handler = qla24xx_intr_handler,
1903 .enable_intrs = qla24xx_enable_intrs,
1904 .disable_intrs = qla24xx_disable_intrs,
1905 .abort_command = qla24xx_abort_command,
1906 .target_reset = qla24xx_abort_target,
1907 .lun_reset = qla24xx_lun_reset,
1908 .fabric_login = qla24xx_login_fabric,
1909 .fabric_logout = qla24xx_fabric_logout,
1910 .calc_req_entries = NULL,
1911 .build_iocbs = NULL,
1912 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1913 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1914 .read_nvram = qla25xx_read_nvram_data,
1915 .write_nvram = qla25xx_write_nvram_data,
1916 .fw_dump = qla25xx_fw_dump,
1917 .beacon_on = qla24xx_beacon_on,
1918 .beacon_off = qla24xx_beacon_off,
1919 .beacon_blink = qla24xx_beacon_blink,
1920 .read_optrom = qla25xx_read_optrom_data,
1921 .write_optrom = qla24xx_write_optrom_data,
1922 .get_flash_version = qla24xx_get_flash_version,
1923 .start_scsi = qla24xx_dif_start_scsi,
1924 .abort_isp = qla2x00_abort_isp,
1925 .iospace_config = qla2x00_iospace_config,
1926 .initialize_adapter = qla2x00_initialize_adapter,
1929 static struct isp_operations qla81xx_isp_ops = {
1930 .pci_config = qla25xx_pci_config,
1931 .reset_chip = qla24xx_reset_chip,
1932 .chip_diag = qla24xx_chip_diag,
1933 .config_rings = qla24xx_config_rings,
1934 .reset_adapter = qla24xx_reset_adapter,
1935 .nvram_config = qla81xx_nvram_config,
1936 .update_fw_options = qla81xx_update_fw_options,
1937 .load_risc = qla81xx_load_risc,
1938 .pci_info_str = qla24xx_pci_info_str,
1939 .fw_version_str = qla24xx_fw_version_str,
1940 .intr_handler = qla24xx_intr_handler,
1941 .enable_intrs = qla24xx_enable_intrs,
1942 .disable_intrs = qla24xx_disable_intrs,
1943 .abort_command = qla24xx_abort_command,
1944 .target_reset = qla24xx_abort_target,
1945 .lun_reset = qla24xx_lun_reset,
1946 .fabric_login = qla24xx_login_fabric,
1947 .fabric_logout = qla24xx_fabric_logout,
1948 .calc_req_entries = NULL,
1949 .build_iocbs = NULL,
1950 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1951 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1953 .write_nvram = NULL,
1954 .fw_dump = qla81xx_fw_dump,
1955 .beacon_on = qla24xx_beacon_on,
1956 .beacon_off = qla24xx_beacon_off,
1957 .beacon_blink = qla83xx_beacon_blink,
1958 .read_optrom = qla25xx_read_optrom_data,
1959 .write_optrom = qla24xx_write_optrom_data,
1960 .get_flash_version = qla24xx_get_flash_version,
1961 .start_scsi = qla24xx_dif_start_scsi,
1962 .abort_isp = qla2x00_abort_isp,
1963 .iospace_config = qla2x00_iospace_config,
1964 .initialize_adapter = qla2x00_initialize_adapter,
1967 static struct isp_operations qla82xx_isp_ops = {
1968 .pci_config = qla82xx_pci_config,
1969 .reset_chip = qla82xx_reset_chip,
1970 .chip_diag = qla24xx_chip_diag,
1971 .config_rings = qla82xx_config_rings,
1972 .reset_adapter = qla24xx_reset_adapter,
1973 .nvram_config = qla81xx_nvram_config,
1974 .update_fw_options = qla24xx_update_fw_options,
1975 .load_risc = qla82xx_load_risc,
1976 .pci_info_str = qla24xx_pci_info_str,
1977 .fw_version_str = qla24xx_fw_version_str,
1978 .intr_handler = qla82xx_intr_handler,
1979 .enable_intrs = qla82xx_enable_intrs,
1980 .disable_intrs = qla82xx_disable_intrs,
1981 .abort_command = qla24xx_abort_command,
1982 .target_reset = qla24xx_abort_target,
1983 .lun_reset = qla24xx_lun_reset,
1984 .fabric_login = qla24xx_login_fabric,
1985 .fabric_logout = qla24xx_fabric_logout,
1986 .calc_req_entries = NULL,
1987 .build_iocbs = NULL,
1988 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1989 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1990 .read_nvram = qla24xx_read_nvram_data,
1991 .write_nvram = qla24xx_write_nvram_data,
1992 .fw_dump = qla82xx_fw_dump,
1993 .beacon_on = qla82xx_beacon_on,
1994 .beacon_off = qla82xx_beacon_off,
1995 .beacon_blink = NULL,
1996 .read_optrom = qla82xx_read_optrom_data,
1997 .write_optrom = qla82xx_write_optrom_data,
1998 .get_flash_version = qla82xx_get_flash_version,
1999 .start_scsi = qla82xx_start_scsi,
2000 .abort_isp = qla82xx_abort_isp,
2001 .iospace_config = qla82xx_iospace_config,
2002 .initialize_adapter = qla2x00_initialize_adapter,
2005 static struct isp_operations qla8044_isp_ops = {
2006 .pci_config = qla82xx_pci_config,
2007 .reset_chip = qla82xx_reset_chip,
2008 .chip_diag = qla24xx_chip_diag,
2009 .config_rings = qla82xx_config_rings,
2010 .reset_adapter = qla24xx_reset_adapter,
2011 .nvram_config = qla81xx_nvram_config,
2012 .update_fw_options = qla24xx_update_fw_options,
2013 .load_risc = qla82xx_load_risc,
2014 .pci_info_str = qla24xx_pci_info_str,
2015 .fw_version_str = qla24xx_fw_version_str,
2016 .intr_handler = qla8044_intr_handler,
2017 .enable_intrs = qla82xx_enable_intrs,
2018 .disable_intrs = qla82xx_disable_intrs,
2019 .abort_command = qla24xx_abort_command,
2020 .target_reset = qla24xx_abort_target,
2021 .lun_reset = qla24xx_lun_reset,
2022 .fabric_login = qla24xx_login_fabric,
2023 .fabric_logout = qla24xx_fabric_logout,
2024 .calc_req_entries = NULL,
2025 .build_iocbs = NULL,
2026 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2027 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2029 .write_nvram = NULL,
2030 .fw_dump = qla8044_fw_dump,
2031 .beacon_on = qla82xx_beacon_on,
2032 .beacon_off = qla82xx_beacon_off,
2033 .beacon_blink = NULL,
2034 .read_optrom = qla8044_read_optrom_data,
2035 .write_optrom = qla8044_write_optrom_data,
2036 .get_flash_version = qla82xx_get_flash_version,
2037 .start_scsi = qla82xx_start_scsi,
2038 .abort_isp = qla8044_abort_isp,
2039 .iospace_config = qla82xx_iospace_config,
2040 .initialize_adapter = qla2x00_initialize_adapter,
2043 static struct isp_operations qla83xx_isp_ops = {
2044 .pci_config = qla25xx_pci_config,
2045 .reset_chip = qla24xx_reset_chip,
2046 .chip_diag = qla24xx_chip_diag,
2047 .config_rings = qla24xx_config_rings,
2048 .reset_adapter = qla24xx_reset_adapter,
2049 .nvram_config = qla81xx_nvram_config,
2050 .update_fw_options = qla81xx_update_fw_options,
2051 .load_risc = qla81xx_load_risc,
2052 .pci_info_str = qla24xx_pci_info_str,
2053 .fw_version_str = qla24xx_fw_version_str,
2054 .intr_handler = qla24xx_intr_handler,
2055 .enable_intrs = qla24xx_enable_intrs,
2056 .disable_intrs = qla24xx_disable_intrs,
2057 .abort_command = qla24xx_abort_command,
2058 .target_reset = qla24xx_abort_target,
2059 .lun_reset = qla24xx_lun_reset,
2060 .fabric_login = qla24xx_login_fabric,
2061 .fabric_logout = qla24xx_fabric_logout,
2062 .calc_req_entries = NULL,
2063 .build_iocbs = NULL,
2064 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2065 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2067 .write_nvram = NULL,
2068 .fw_dump = qla83xx_fw_dump,
2069 .beacon_on = qla24xx_beacon_on,
2070 .beacon_off = qla24xx_beacon_off,
2071 .beacon_blink = qla83xx_beacon_blink,
2072 .read_optrom = qla25xx_read_optrom_data,
2073 .write_optrom = qla24xx_write_optrom_data,
2074 .get_flash_version = qla24xx_get_flash_version,
2075 .start_scsi = qla24xx_dif_start_scsi,
2076 .abort_isp = qla2x00_abort_isp,
2077 .iospace_config = qla83xx_iospace_config,
2078 .initialize_adapter = qla2x00_initialize_adapter,
2081 static struct isp_operations qlafx00_isp_ops = {
2082 .pci_config = qlafx00_pci_config,
2083 .reset_chip = qlafx00_soft_reset,
2084 .chip_diag = qlafx00_chip_diag,
2085 .config_rings = qlafx00_config_rings,
2086 .reset_adapter = qlafx00_soft_reset,
2087 .nvram_config = NULL,
2088 .update_fw_options = NULL,
2090 .pci_info_str = qlafx00_pci_info_str,
2091 .fw_version_str = qlafx00_fw_version_str,
2092 .intr_handler = qlafx00_intr_handler,
2093 .enable_intrs = qlafx00_enable_intrs,
2094 .disable_intrs = qlafx00_disable_intrs,
2095 .abort_command = qla24xx_async_abort_command,
2096 .target_reset = qlafx00_abort_target,
2097 .lun_reset = qlafx00_lun_reset,
2098 .fabric_login = NULL,
2099 .fabric_logout = NULL,
2100 .calc_req_entries = NULL,
2101 .build_iocbs = NULL,
2102 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2103 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2104 .read_nvram = qla24xx_read_nvram_data,
2105 .write_nvram = qla24xx_write_nvram_data,
2107 .beacon_on = qla24xx_beacon_on,
2108 .beacon_off = qla24xx_beacon_off,
2109 .beacon_blink = NULL,
2110 .read_optrom = qla24xx_read_optrom_data,
2111 .write_optrom = qla24xx_write_optrom_data,
2112 .get_flash_version = qla24xx_get_flash_version,
2113 .start_scsi = qlafx00_start_scsi,
2114 .abort_isp = qlafx00_abort_isp,
2115 .iospace_config = qlafx00_iospace_config,
2116 .initialize_adapter = qlafx00_initialize_adapter,
2119 static struct isp_operations qla27xx_isp_ops = {
2120 .pci_config = qla25xx_pci_config,
2121 .reset_chip = qla24xx_reset_chip,
2122 .chip_diag = qla24xx_chip_diag,
2123 .config_rings = qla24xx_config_rings,
2124 .reset_adapter = qla24xx_reset_adapter,
2125 .nvram_config = qla81xx_nvram_config,
2126 .update_fw_options = qla81xx_update_fw_options,
2127 .load_risc = qla81xx_load_risc,
2128 .pci_info_str = qla24xx_pci_info_str,
2129 .fw_version_str = qla24xx_fw_version_str,
2130 .intr_handler = qla24xx_intr_handler,
2131 .enable_intrs = qla24xx_enable_intrs,
2132 .disable_intrs = qla24xx_disable_intrs,
2133 .abort_command = qla24xx_abort_command,
2134 .target_reset = qla24xx_abort_target,
2135 .lun_reset = qla24xx_lun_reset,
2136 .fabric_login = qla24xx_login_fabric,
2137 .fabric_logout = qla24xx_fabric_logout,
2138 .calc_req_entries = NULL,
2139 .build_iocbs = NULL,
2140 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2141 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2143 .write_nvram = NULL,
2144 .fw_dump = qla27xx_fwdump,
2145 .beacon_on = qla24xx_beacon_on,
2146 .beacon_off = qla24xx_beacon_off,
2147 .beacon_blink = qla83xx_beacon_blink,
2148 .read_optrom = qla25xx_read_optrom_data,
2149 .write_optrom = qla24xx_write_optrom_data,
2150 .get_flash_version = qla24xx_get_flash_version,
2151 .start_scsi = qla24xx_dif_start_scsi,
2152 .abort_isp = qla2x00_abort_isp,
2153 .iospace_config = qla83xx_iospace_config,
2154 .initialize_adapter = qla2x00_initialize_adapter,
2158 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2160 ha->device_type = DT_EXTENDED_IDS;
2161 switch (ha->pdev->device) {
2162 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2163 ha->device_type |= DT_ISP2100;
2164 ha->device_type &= ~DT_EXTENDED_IDS;
2165 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2167 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2168 ha->device_type |= DT_ISP2200;
2169 ha->device_type &= ~DT_EXTENDED_IDS;
2170 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2172 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2173 ha->device_type |= DT_ISP2300;
2174 ha->device_type |= DT_ZIO_SUPPORTED;
2175 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2177 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2178 ha->device_type |= DT_ISP2312;
2179 ha->device_type |= DT_ZIO_SUPPORTED;
2180 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2182 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2183 ha->device_type |= DT_ISP2322;
2184 ha->device_type |= DT_ZIO_SUPPORTED;
2185 if (ha->pdev->subsystem_vendor == 0x1028 &&
2186 ha->pdev->subsystem_device == 0x0170)
2187 ha->device_type |= DT_OEM_001;
2188 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2190 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2191 ha->device_type |= DT_ISP6312;
2192 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2194 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2195 ha->device_type |= DT_ISP6322;
2196 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2198 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2199 ha->device_type |= DT_ISP2422;
2200 ha->device_type |= DT_ZIO_SUPPORTED;
2201 ha->device_type |= DT_FWI2;
2202 ha->device_type |= DT_IIDMA;
2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2205 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2206 ha->device_type |= DT_ISP2432;
2207 ha->device_type |= DT_ZIO_SUPPORTED;
2208 ha->device_type |= DT_FWI2;
2209 ha->device_type |= DT_IIDMA;
2210 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2212 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2213 ha->device_type |= DT_ISP8432;
2214 ha->device_type |= DT_ZIO_SUPPORTED;
2215 ha->device_type |= DT_FWI2;
2216 ha->device_type |= DT_IIDMA;
2217 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2219 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2220 ha->device_type |= DT_ISP5422;
2221 ha->device_type |= DT_FWI2;
2222 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2224 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2225 ha->device_type |= DT_ISP5432;
2226 ha->device_type |= DT_FWI2;
2227 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2229 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2230 ha->device_type |= DT_ISP2532;
2231 ha->device_type |= DT_ZIO_SUPPORTED;
2232 ha->device_type |= DT_FWI2;
2233 ha->device_type |= DT_IIDMA;
2234 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2236 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2237 ha->device_type |= DT_ISP8001;
2238 ha->device_type |= DT_ZIO_SUPPORTED;
2239 ha->device_type |= DT_FWI2;
2240 ha->device_type |= DT_IIDMA;
2241 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2243 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2244 ha->device_type |= DT_ISP8021;
2245 ha->device_type |= DT_ZIO_SUPPORTED;
2246 ha->device_type |= DT_FWI2;
2247 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2248 /* Initialize 82XX ISP flags */
2249 qla82xx_init_flags(ha);
2251 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2252 ha->device_type |= DT_ISP8044;
2253 ha->device_type |= DT_ZIO_SUPPORTED;
2254 ha->device_type |= DT_FWI2;
2255 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2256 /* Initialize 82XX ISP flags */
2257 qla82xx_init_flags(ha);
2259 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2260 ha->device_type |= DT_ISP2031;
2261 ha->device_type |= DT_ZIO_SUPPORTED;
2262 ha->device_type |= DT_FWI2;
2263 ha->device_type |= DT_IIDMA;
2264 ha->device_type |= DT_T10_PI;
2265 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2267 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2268 ha->device_type |= DT_ISP8031;
2269 ha->device_type |= DT_ZIO_SUPPORTED;
2270 ha->device_type |= DT_FWI2;
2271 ha->device_type |= DT_IIDMA;
2272 ha->device_type |= DT_T10_PI;
2273 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2275 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2276 ha->device_type |= DT_ISPFX00;
2278 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2279 ha->device_type |= DT_ISP2071;
2280 ha->device_type |= DT_ZIO_SUPPORTED;
2281 ha->device_type |= DT_FWI2;
2282 ha->device_type |= DT_IIDMA;
2283 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2285 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2286 ha->device_type |= DT_ISP2271;
2287 ha->device_type |= DT_ZIO_SUPPORTED;
2288 ha->device_type |= DT_FWI2;
2289 ha->device_type |= DT_IIDMA;
2290 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2295 ha->port_no = ha->portnum & 1;
2297 /* Get adapter physical port no from interrupt pin register. */
2298 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2302 ha->port_no = !(ha->port_no & 1);
2305 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2306 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2307 ha->device_type, ha->port_no, ha->fw_srisc_address);
2311 qla2xxx_scan_start(struct Scsi_Host *shost)
2313 scsi_qla_host_t *vha = shost_priv(shost);
2315 if (vha->hw->flags.running_gold_fw)
2318 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2319 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2320 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2321 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2325 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2327 scsi_qla_host_t *vha = shost_priv(shost);
2331 if (time > vha->hw->loop_reset_delay * HZ)
2334 return atomic_read(&vha->loop_state) == LOOP_READY;
2338 * PCI driver interface
2341 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2344 struct Scsi_Host *host;
2345 scsi_qla_host_t *base_vha = NULL;
2346 struct qla_hw_data *ha;
2348 char fw_str[30], wq_name[30];
2349 struct scsi_host_template *sht;
2350 int bars, mem_only = 0;
2351 uint16_t req_length = 0, rsp_length = 0;
2352 struct req_que *req = NULL;
2353 struct rsp_que *rsp = NULL;
2354 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2355 sht = &qla2xxx_driver_template;
2356 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2357 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2358 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2359 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2360 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2361 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2362 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2363 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2364 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2365 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2366 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2367 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2368 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2369 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
2370 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2372 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2373 "Mem only adapter.\n");
2375 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2376 "Bars=%d.\n", bars);
2379 if (pci_enable_device_mem(pdev))
2382 if (pci_enable_device(pdev))
2386 /* This may fail but that's ok */
2387 pci_enable_pcie_error_reporting(pdev);
2389 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2391 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2392 "Unable to allocate memory for ha.\n");
2395 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2396 "Memory allocated for ha=%p.\n", ha);
2398 ha->tgt.enable_class_2 = ql2xenableclass2;
2400 /* Clear our data area */
2402 ha->mem_only = mem_only;
2403 spin_lock_init(&ha->hardware_lock);
2404 spin_lock_init(&ha->vport_slock);
2405 mutex_init(&ha->selflogin_lock);
2406 mutex_init(&ha->optrom_mutex);
2408 /* Set ISP-type information. */
2409 qla2x00_set_isp_flags(ha);
2411 /* Set EEH reset type to fundamental if required by hba */
2412 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2413 IS_QLA83XX(ha) || IS_QLA27XX(ha))
2414 pdev->needs_freset = 1;
2416 ha->prev_topology = 0;
2417 ha->init_cb_size = sizeof(init_cb_t);
2418 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2419 ha->optrom_size = OPTROM_SIZE_2300;
2421 /* Assign ISP specific operations. */
2422 if (IS_QLA2100(ha)) {
2423 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2424 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2425 req_length = REQUEST_ENTRY_CNT_2100;
2426 rsp_length = RESPONSE_ENTRY_CNT_2100;
2427 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2428 ha->gid_list_info_size = 4;
2429 ha->flash_conf_off = ~0;
2430 ha->flash_data_off = ~0;
2431 ha->nvram_conf_off = ~0;
2432 ha->nvram_data_off = ~0;
2433 ha->isp_ops = &qla2100_isp_ops;
2434 } else if (IS_QLA2200(ha)) {
2435 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2436 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2437 req_length = REQUEST_ENTRY_CNT_2200;
2438 rsp_length = RESPONSE_ENTRY_CNT_2100;
2439 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2440 ha->gid_list_info_size = 4;
2441 ha->flash_conf_off = ~0;
2442 ha->flash_data_off = ~0;
2443 ha->nvram_conf_off = ~0;
2444 ha->nvram_data_off = ~0;
2445 ha->isp_ops = &qla2100_isp_ops;
2446 } else if (IS_QLA23XX(ha)) {
2447 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2448 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2449 req_length = REQUEST_ENTRY_CNT_2200;
2450 rsp_length = RESPONSE_ENTRY_CNT_2300;
2451 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2452 ha->gid_list_info_size = 6;
2453 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2454 ha->optrom_size = OPTROM_SIZE_2322;
2455 ha->flash_conf_off = ~0;
2456 ha->flash_data_off = ~0;
2457 ha->nvram_conf_off = ~0;
2458 ha->nvram_data_off = ~0;
2459 ha->isp_ops = &qla2300_isp_ops;
2460 } else if (IS_QLA24XX_TYPE(ha)) {
2461 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2462 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2463 req_length = REQUEST_ENTRY_CNT_24XX;
2464 rsp_length = RESPONSE_ENTRY_CNT_2300;
2465 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2466 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2467 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2468 ha->gid_list_info_size = 8;
2469 ha->optrom_size = OPTROM_SIZE_24XX;
2470 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2471 ha->isp_ops = &qla24xx_isp_ops;
2472 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2473 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2474 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2475 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2476 } else if (IS_QLA25XX(ha)) {
2477 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2478 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2479 req_length = REQUEST_ENTRY_CNT_24XX;
2480 rsp_length = RESPONSE_ENTRY_CNT_2300;
2481 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2482 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2483 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2484 ha->gid_list_info_size = 8;
2485 ha->optrom_size = OPTROM_SIZE_25XX;
2486 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2487 ha->isp_ops = &qla25xx_isp_ops;
2488 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2489 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2490 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2491 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2492 } else if (IS_QLA81XX(ha)) {
2493 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2494 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2495 req_length = REQUEST_ENTRY_CNT_24XX;
2496 rsp_length = RESPONSE_ENTRY_CNT_2300;
2497 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2498 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2499 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2500 ha->gid_list_info_size = 8;
2501 ha->optrom_size = OPTROM_SIZE_81XX;
2502 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2503 ha->isp_ops = &qla81xx_isp_ops;
2504 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2505 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2506 ha->nvram_conf_off = ~0;
2507 ha->nvram_data_off = ~0;
2508 } else if (IS_QLA82XX(ha)) {
2509 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2510 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2511 req_length = REQUEST_ENTRY_CNT_82XX;
2512 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2513 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2514 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2515 ha->gid_list_info_size = 8;
2516 ha->optrom_size = OPTROM_SIZE_82XX;
2517 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2518 ha->isp_ops = &qla82xx_isp_ops;
2519 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2520 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2521 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2522 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2523 } else if (IS_QLA8044(ha)) {
2524 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2525 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2526 req_length = REQUEST_ENTRY_CNT_82XX;
2527 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2528 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2529 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2530 ha->gid_list_info_size = 8;
2531 ha->optrom_size = OPTROM_SIZE_83XX;
2532 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2533 ha->isp_ops = &qla8044_isp_ops;
2534 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2535 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2536 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2537 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2538 } else if (IS_QLA83XX(ha)) {
2539 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2540 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2541 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2542 req_length = REQUEST_ENTRY_CNT_24XX;
2543 rsp_length = RESPONSE_ENTRY_CNT_2300;
2544 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2545 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2546 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2547 ha->gid_list_info_size = 8;
2548 ha->optrom_size = OPTROM_SIZE_83XX;
2549 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2550 ha->isp_ops = &qla83xx_isp_ops;
2551 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2552 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2553 ha->nvram_conf_off = ~0;
2554 ha->nvram_data_off = ~0;
2555 } else if (IS_QLAFX00(ha)) {
2556 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2557 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2558 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2559 req_length = REQUEST_ENTRY_CNT_FX00;
2560 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2561 ha->isp_ops = &qlafx00_isp_ops;
2562 ha->port_down_retry_count = 30; /* default value */
2563 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2564 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2565 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2566 ha->mr.fw_hbt_en = 1;
2567 ha->mr.host_info_resend = false;
2568 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2569 } else if (IS_QLA27XX(ha)) {
2570 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2571 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2572 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2573 req_length = REQUEST_ENTRY_CNT_24XX;
2574 rsp_length = RESPONSE_ENTRY_CNT_2300;
2575 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2576 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2577 ha->gid_list_info_size = 8;
2578 ha->optrom_size = OPTROM_SIZE_83XX;
2579 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2580 ha->isp_ops = &qla27xx_isp_ops;
2581 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2582 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2583 ha->nvram_conf_off = ~0;
2584 ha->nvram_data_off = ~0;
2587 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2588 "mbx_count=%d, req_length=%d, "
2589 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2590 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2591 "max_fibre_devices=%d.\n",
2592 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2593 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2594 ha->nvram_npiv_size, ha->max_fibre_devices);
2595 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2596 "isp_ops=%p, flash_conf_off=%d, "
2597 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2598 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2599 ha->nvram_conf_off, ha->nvram_data_off);
2601 /* Configure PCI I/O space */
2602 ret = ha->isp_ops->iospace_config(ha);
2604 goto iospace_config_failed;
2606 ql_log_pci(ql_log_info, pdev, 0x001d,
2607 "Found an ISP%04X irq %d iobase 0x%p.\n",
2608 pdev->device, pdev->irq, ha->iobase);
2609 mutex_init(&ha->vport_lock);
2610 init_completion(&ha->mbx_cmd_comp);
2611 complete(&ha->mbx_cmd_comp);
2612 init_completion(&ha->mbx_intr_comp);
2613 init_completion(&ha->dcbx_comp);
2614 init_completion(&ha->lb_portup_comp);
2616 set_bit(0, (unsigned long *) ha->vp_idx_map);
2618 qla2x00_config_dma_addressing(ha);
2619 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2620 "64 Bit addressing is %s.\n",
2621 ha->flags.enable_64bit_addressing ? "enable" :
2623 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2625 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2626 "Failed to allocate memory for adapter, aborting.\n");
2628 goto probe_hw_failed;
2631 req->max_q_depth = MAX_Q_DEPTH;
2632 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2633 req->max_q_depth = ql2xmaxqdepth;
2636 base_vha = qla2x00_create_host(sht, ha);
2639 qla2x00_mem_free(ha);
2640 qla2x00_free_req_que(ha, req);
2641 qla2x00_free_rsp_que(ha, rsp);
2642 goto probe_hw_failed;
2645 pci_set_drvdata(pdev, base_vha);
2646 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2648 host = base_vha->host;
2649 base_vha->req = req;
2650 if (IS_QLA2XXX_MIDTYPE(ha))
2651 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2653 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2656 /* Setup fcport template structure. */
2657 ha->mr.fcport.vha = base_vha;
2658 ha->mr.fcport.port_type = FCT_UNKNOWN;
2659 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2660 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2661 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2662 ha->mr.fcport.scan_state = 1;
2664 /* Set the SG table size based on ISP type */
2665 if (!IS_FWI2_CAPABLE(ha)) {
2667 host->sg_tablesize = 32;
2669 if (!IS_QLA82XX(ha))
2670 host->sg_tablesize = QLA_SG_ALL;
2672 host->max_id = ha->max_fibre_devices;
2673 host->cmd_per_lun = 3;
2674 host->unique_id = host->host_no;
2675 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2676 host->max_cmd_len = 32;
2678 host->max_cmd_len = MAX_CMDSZ;
2679 host->max_channel = MAX_BUSES - 1;
2680 /* Older HBAs support only 16-bit LUNs */
2681 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2682 ql2xmaxlun > 0xffff)
2683 host->max_lun = 0xffff;
2685 host->max_lun = ql2xmaxlun;
2686 host->transportt = qla2xxx_transport_template;
2687 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2689 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2690 "max_id=%d this_id=%d "
2691 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2692 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
2693 host->this_id, host->cmd_per_lun, host->unique_id,
2694 host->max_cmd_len, host->max_channel, host->max_lun,
2695 host->transportt, sht->vendor_id);
2698 /* Alloc arrays of request and response ring ptrs */
2699 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2700 ql_log(ql_log_fatal, base_vha, 0x003d,
2701 "Failed to allocate memory for queue pointers..."
2703 goto probe_init_failed;
2706 qlt_probe_one_stage1(base_vha, ha);
2708 /* Set up the irqs */
2709 ret = qla2x00_request_irqs(ha, rsp);
2711 goto probe_init_failed;
2713 pci_save_state(pdev);
2715 /* Assign back pointers */
2719 if (IS_QLAFX00(ha)) {
2720 ha->rsp_q_map[0] = rsp;
2721 ha->req_q_map[0] = req;
2722 set_bit(0, ha->req_qid_map);
2723 set_bit(0, ha->rsp_qid_map);
2726 /* FWI2-capable only. */
2727 req->req_q_in = &ha->iobase->isp24.req_q_in;
2728 req->req_q_out = &ha->iobase->isp24.req_q_out;
2729 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2730 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2731 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2732 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2733 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2734 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2735 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2738 if (IS_QLAFX00(ha)) {
2739 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2740 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2741 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2742 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2745 if (IS_P3P_TYPE(ha)) {
2746 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2747 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2748 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2751 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2752 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2753 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2754 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2755 "req->req_q_in=%p req->req_q_out=%p "
2756 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2757 req->req_q_in, req->req_q_out,
2758 rsp->rsp_q_in, rsp->rsp_q_out);
2759 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2760 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2761 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2762 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2763 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2764 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2766 if (ha->isp_ops->initialize_adapter(base_vha)) {
2767 ql_log(ql_log_fatal, base_vha, 0x00d6,
2768 "Failed to initialize adapter - Adapter flags %x.\n",
2769 base_vha->device_flags);
2771 if (IS_QLA82XX(ha)) {
2772 qla82xx_idc_lock(ha);
2773 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2774 QLA8XXX_DEV_FAILED);
2775 qla82xx_idc_unlock(ha);
2776 ql_log(ql_log_fatal, base_vha, 0x00d7,
2777 "HW State: FAILED.\n");
2778 } else if (IS_QLA8044(ha)) {
2779 qla8044_idc_lock(ha);
2780 qla8044_wr_direct(base_vha,
2781 QLA8044_CRB_DEV_STATE_INDEX,
2782 QLA8XXX_DEV_FAILED);
2783 qla8044_idc_unlock(ha);
2784 ql_log(ql_log_fatal, base_vha, 0x0150,
2785 "HW State: FAILED.\n");
2793 host->can_queue = QLAFX00_MAX_CANQUEUE;
2795 host->can_queue = req->num_outstanding_cmds - 10;
2797 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2798 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2799 host->can_queue, base_vha->req,
2800 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2803 if (qla25xx_setup_mode(base_vha)) {
2804 ql_log(ql_log_warn, base_vha, 0x00ec,
2805 "Failed to create queues, falling back to single queue mode.\n");
2810 if (ha->flags.running_gold_fw)
2814 * Startup the kernel thread for this host adapter
2816 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2817 "%s_dpc", base_vha->host_str);
2818 if (IS_ERR(ha->dpc_thread)) {
2819 ql_log(ql_log_fatal, base_vha, 0x00ed,
2820 "Failed to start DPC thread.\n");
2821 ret = PTR_ERR(ha->dpc_thread);
2824 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2825 "DPC thread started successfully.\n");
2828 * If we're not coming up in initiator mode, we might sit for
2829 * a while without waking up the dpc thread, which leads to a
2830 * stuck process warning. So just kick the dpc once here and
2831 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2833 qla2xxx_wake_dpc(base_vha);
2835 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2837 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2838 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2839 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2840 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2842 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2843 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2844 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2845 INIT_WORK(&ha->idc_state_handler,
2846 qla83xx_idc_state_handler_work);
2847 INIT_WORK(&ha->nic_core_unrecoverable,
2848 qla83xx_nic_core_unrecoverable_work);
2852 list_add_tail(&base_vha->list, &ha->vp_list);
2853 base_vha->host->irq = ha->pdev->irq;
2855 /* Initialized the timer */
2856 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2857 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2858 "Started qla2x00_timer with "
2859 "interval=%d.\n", WATCH_INTERVAL);
2860 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2861 "Detected hba at address=%p.\n",
2864 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2865 if (ha->fw_attributes & BIT_4) {
2866 int prot = 0, guard;
2867 base_vha->flags.difdix_supported = 1;
2868 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2869 "Registering for DIF/DIX type 1 and 3 protection.\n");
2870 if (ql2xenabledif == 1)
2871 prot = SHOST_DIX_TYPE0_PROTECTION;
2872 scsi_host_set_prot(host,
2873 prot | SHOST_DIF_TYPE1_PROTECTION
2874 | SHOST_DIF_TYPE2_PROTECTION
2875 | SHOST_DIF_TYPE3_PROTECTION
2876 | SHOST_DIX_TYPE1_PROTECTION
2877 | SHOST_DIX_TYPE2_PROTECTION
2878 | SHOST_DIX_TYPE3_PROTECTION);
2880 guard = SHOST_DIX_GUARD_CRC;
2882 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2883 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2884 guard |= SHOST_DIX_GUARD_IP;
2886 scsi_host_set_guard(host, guard);
2888 base_vha->flags.difdix_supported = 0;
2891 ha->isp_ops->enable_intrs(ha);
2893 if (IS_QLAFX00(ha)) {
2894 ret = qlafx00_fx_disc(base_vha,
2895 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2896 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2900 ret = scsi_add_host(host, &pdev->dev);
2904 base_vha->flags.init_done = 1;
2905 base_vha->flags.online = 1;
2906 ha->prev_minidump_failed = 0;
2908 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2909 "Init done and hba is online.\n");
2911 if (qla_ini_mode_enabled(base_vha))
2912 scsi_scan_host(host);
2914 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2915 "skipping scsi_scan_host() for non-initiator port\n");
2917 qla2x00_alloc_sysfs_attr(base_vha);
2919 if (IS_QLAFX00(ha)) {
2920 ret = qlafx00_fx_disc(base_vha,
2921 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2923 /* Register system information */
2924 ret = qlafx00_fx_disc(base_vha,
2925 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2928 qla2x00_init_host_attr(base_vha);
2930 qla2x00_dfs_setup(base_vha);
2932 ql_log(ql_log_info, base_vha, 0x00fb,
2933 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2934 ql_log(ql_log_info, base_vha, 0x00fc,
2935 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2936 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2937 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2939 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
2941 qlt_add_target(ha, base_vha);
2943 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2947 qla2x00_free_req_que(ha, req);
2948 ha->req_q_map[0] = NULL;
2949 clear_bit(0, ha->req_qid_map);
2950 qla2x00_free_rsp_que(ha, rsp);
2951 ha->rsp_q_map[0] = NULL;
2952 clear_bit(0, ha->rsp_qid_map);
2953 ha->max_req_queues = ha->max_rsp_queues = 0;
2956 if (base_vha->timer_active)
2957 qla2x00_stop_timer(base_vha);
2958 base_vha->flags.online = 0;
2959 if (ha->dpc_thread) {
2960 struct task_struct *t = ha->dpc_thread;
2962 ha->dpc_thread = NULL;
2966 qla2x00_free_device(base_vha);
2968 scsi_host_put(base_vha->host);
2971 qla2x00_clear_drv_active(ha);
2973 iospace_config_failed:
2974 if (IS_P3P_TYPE(ha)) {
2975 if (!ha->nx_pcibase)
2976 iounmap((device_reg_t *)ha->nx_pcibase);
2978 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
2981 iounmap(ha->iobase);
2983 iounmap(ha->cregbase);
2985 pci_release_selected_regions(ha->pdev, ha->bars);
2990 pci_disable_device(pdev);
2995 qla2x00_shutdown(struct pci_dev *pdev)
2997 scsi_qla_host_t *vha;
2998 struct qla_hw_data *ha;
3000 if (!atomic_read(&pdev->enable_cnt))
3003 vha = pci_get_drvdata(pdev);
3006 /* Notify ISPFX00 firmware */
3008 qlafx00_driver_shutdown(vha, 20);
3010 /* Turn-off FCE trace */
3011 if (ha->flags.fce_enabled) {
3012 qla2x00_disable_fce_trace(vha, NULL, NULL);
3013 ha->flags.fce_enabled = 0;
3016 /* Turn-off EFT trace */
3018 qla2x00_disable_eft_trace(vha);
3020 /* Stop currently executing firmware. */
3021 qla2x00_try_to_stop_firmware(vha);
3023 /* Turn adapter off line */
3024 vha->flags.online = 0;
3026 /* turn-off interrupts on the card */
3027 if (ha->interrupts_on) {
3028 vha->flags.init_done = 0;
3029 ha->isp_ops->disable_intrs(ha);
3032 qla2x00_free_irqs(vha);
3034 qla2x00_free_fw_dump(ha);
3036 pci_disable_pcie_error_reporting(pdev);
3037 pci_disable_device(pdev);
3040 /* Deletes all the virtual ports for a given ha */
3042 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3044 struct Scsi_Host *scsi_host;
3045 scsi_qla_host_t *vha;
3046 unsigned long flags;
3048 mutex_lock(&ha->vport_lock);
3049 while (ha->cur_vport_count) {
3050 spin_lock_irqsave(&ha->vport_slock, flags);
3052 BUG_ON(base_vha->list.next == &ha->vp_list);
3053 /* This assumes first entry in ha->vp_list is always base vha */
3054 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3055 scsi_host = scsi_host_get(vha->host);
3057 spin_unlock_irqrestore(&ha->vport_slock, flags);
3058 mutex_unlock(&ha->vport_lock);
3060 fc_vport_terminate(vha->fc_vport);
3061 scsi_host_put(vha->host);
3063 mutex_lock(&ha->vport_lock);
3065 mutex_unlock(&ha->vport_lock);
3068 /* Stops all deferred work threads */
3070 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3072 /* Flush the work queue and remove it */
3074 flush_workqueue(ha->wq);
3075 destroy_workqueue(ha->wq);
3079 /* Cancel all work and destroy DPC workqueues */
3080 if (ha->dpc_lp_wq) {
3081 cancel_work_sync(&ha->idc_aen);
3082 destroy_workqueue(ha->dpc_lp_wq);
3083 ha->dpc_lp_wq = NULL;
3086 if (ha->dpc_hp_wq) {
3087 cancel_work_sync(&ha->nic_core_reset);
3088 cancel_work_sync(&ha->idc_state_handler);
3089 cancel_work_sync(&ha->nic_core_unrecoverable);
3090 destroy_workqueue(ha->dpc_hp_wq);
3091 ha->dpc_hp_wq = NULL;
3094 /* Kill the kernel thread for this host */
3095 if (ha->dpc_thread) {
3096 struct task_struct *t = ha->dpc_thread;
3099 * qla2xxx_wake_dpc checks for ->dpc_thread
3100 * so we need to zero it out.
3102 ha->dpc_thread = NULL;
3108 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3110 if (IS_QLA82XX(ha)) {
3112 iounmap((device_reg_t *)ha->nx_pcibase);
3114 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3117 iounmap(ha->iobase);
3120 iounmap(ha->cregbase);
3123 iounmap(ha->mqiobase);
3125 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3126 iounmap(ha->msixbase);
3131 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3133 if (IS_QLA8044(ha)) {
3134 qla8044_idc_lock(ha);
3135 qla8044_clear_drv_active(ha);
3136 qla8044_idc_unlock(ha);
3137 } else if (IS_QLA82XX(ha)) {
3138 qla82xx_idc_lock(ha);
3139 qla82xx_clear_drv_active(ha);
3140 qla82xx_idc_unlock(ha);
3145 qla2x00_remove_one(struct pci_dev *pdev)
3147 scsi_qla_host_t *base_vha;
3148 struct qla_hw_data *ha;
3150 base_vha = pci_get_drvdata(pdev);
3153 /* Indicate device removal to prevent future board_disable and wait
3154 * until any pending board_disable has completed. */
3155 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3156 cancel_work_sync(&ha->board_disable);
3159 * If the PCI device is disabled then there was a PCI-disconnect and
3160 * qla2x00_disable_board_on_pci_error has taken care of most of the
3163 if (!atomic_read(&pdev->enable_cnt)) {
3164 scsi_host_put(base_vha->host);
3166 pci_set_drvdata(pdev, NULL);
3170 qla2x00_wait_for_hba_ready(base_vha);
3172 set_bit(UNLOADING, &base_vha->dpc_flags);
3175 qlafx00_driver_shutdown(base_vha, 20);
3177 qla2x00_delete_all_vps(ha, base_vha);
3179 if (IS_QLA8031(ha)) {
3180 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3181 "Clearing fcoe driver presence.\n");
3182 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3183 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3184 "Error while clearing DRV-Presence.\n");
3187 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3189 qla2x00_dfs_remove(base_vha);
3191 qla84xx_put_chip(base_vha);
3193 /* Laser should be disabled only for ISP2031 */
3195 qla83xx_disable_laser(base_vha);
3198 if (base_vha->timer_active)
3199 qla2x00_stop_timer(base_vha);
3201 base_vha->flags.online = 0;
3203 qla2x00_destroy_deferred_work(ha);
3205 qlt_remove_target(ha, base_vha);
3207 qla2x00_free_sysfs_attr(base_vha, true);
3209 fc_remove_host(base_vha->host);
3211 scsi_remove_host(base_vha->host);
3213 qla2x00_free_device(base_vha);
3215 qla2x00_clear_drv_active(ha);
3217 scsi_host_put(base_vha->host);
3219 qla2x00_unmap_iobases(ha);
3221 pci_release_selected_regions(ha->pdev, ha->bars);
3225 pci_disable_pcie_error_reporting(pdev);
3227 pci_disable_device(pdev);
3231 qla2x00_free_device(scsi_qla_host_t *vha)
3233 struct qla_hw_data *ha = vha->hw;
3235 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3238 if (vha->timer_active)
3239 qla2x00_stop_timer(vha);
3241 qla25xx_delete_queues(vha);
3243 if (ha->flags.fce_enabled)
3244 qla2x00_disable_fce_trace(vha, NULL, NULL);
3247 qla2x00_disable_eft_trace(vha);
3249 /* Stop currently executing firmware. */
3250 qla2x00_try_to_stop_firmware(vha);
3252 vha->flags.online = 0;
3254 /* turn-off interrupts on the card */
3255 if (ha->interrupts_on) {
3256 vha->flags.init_done = 0;
3257 ha->isp_ops->disable_intrs(ha);
3260 qla2x00_free_irqs(vha);
3262 qla2x00_free_fcports(vha);
3264 qla2x00_mem_free(ha);
3266 qla82xx_md_free(vha);
3268 qla2x00_free_queues(ha);
3271 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3273 fc_port_t *fcport, *tfcport;
3275 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3276 list_del(&fcport->list);
3277 qla2x00_clear_loop_id(fcport);
3284 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3287 struct fc_rport *rport;
3288 scsi_qla_host_t *base_vha;
3289 unsigned long flags;
3294 rport = fcport->rport;
3296 base_vha = pci_get_drvdata(vha->hw->pdev);
3297 spin_lock_irqsave(vha->host->host_lock, flags);
3298 fcport->drport = rport;
3299 spin_unlock_irqrestore(vha->host->host_lock, flags);
3300 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3301 qla2xxx_wake_dpc(base_vha);
3303 fc_remote_port_delete(rport);
3304 qlt_fc_port_deleted(vha, fcport);
3309 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3311 * Input: ha = adapter block pointer. fcport = port structure pointer.
3317 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3318 int do_login, int defer)
3320 if (IS_QLAFX00(vha->hw)) {
3321 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3322 qla2x00_schedule_rport_del(vha, fcport, defer);
3326 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3327 vha->vp_idx == fcport->vha->vp_idx) {
3328 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3329 qla2x00_schedule_rport_del(vha, fcport, defer);
3332 * We may need to retry the login, so don't change the state of the
3333 * port but do the retries.
3335 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3336 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3341 if (fcport->login_retry == 0) {
3342 fcport->login_retry = vha->hw->login_retry_count;
3343 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3345 ql_dbg(ql_dbg_disc, vha, 0x2067,
3346 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3347 fcport->port_name, fcport->loop_id, fcport->login_retry);
3352 * qla2x00_mark_all_devices_lost
3353 * Updates fcport state when device goes offline.
3356 * ha = adapter block pointer.
3357 * fcport = port structure pointer.
3365 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3369 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3370 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3374 * No point in marking the device as lost, if the device is
3377 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3379 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3380 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3382 qla2x00_schedule_rport_del(vha, fcport, defer);
3383 else if (vha->vp_idx == fcport->vha->vp_idx)
3384 qla2x00_schedule_rport_del(vha, fcport, defer);
3391 * Allocates adapter memory.
3398 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3399 struct req_que **req, struct rsp_que **rsp)
3403 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3404 &ha->init_cb_dma, GFP_KERNEL);
3408 if (qlt_mem_alloc(ha) < 0)
3409 goto fail_free_init_cb;
3411 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3412 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3414 goto fail_free_tgt_mem;
3416 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3417 if (!ha->srb_mempool)
3418 goto fail_free_gid_list;
3420 if (IS_P3P_TYPE(ha)) {
3421 /* Allocate cache for CT6 Ctx. */
3423 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3424 sizeof(struct ct6_dsd), 0,
3425 SLAB_HWCACHE_ALIGN, NULL);
3427 goto fail_free_gid_list;
3429 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3431 if (!ha->ctx_mempool)
3432 goto fail_free_srb_mempool;
3433 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3434 "ctx_cachep=%p ctx_mempool=%p.\n",
3435 ctx_cachep, ha->ctx_mempool);
3438 /* Get memory for cached NVRAM */
3439 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3441 goto fail_free_ctx_mempool;
3443 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3445 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3446 DMA_POOL_SIZE, 8, 0);
3447 if (!ha->s_dma_pool)
3448 goto fail_free_nvram;
3450 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3451 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3452 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3454 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3455 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3456 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3457 if (!ha->dl_dma_pool) {
3458 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3459 "Failed to allocate memory for dl_dma_pool.\n");
3460 goto fail_s_dma_pool;
3463 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3464 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3465 if (!ha->fcp_cmnd_dma_pool) {
3466 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3467 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3468 goto fail_dl_dma_pool;
3470 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3471 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3472 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3475 /* Allocate memory for SNS commands */
3476 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3477 /* Get consistent memory allocated for SNS commands */
3478 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3479 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3482 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3483 "sns_cmd: %p.\n", ha->sns_cmd);
3485 /* Get consistent memory allocated for MS IOCB */
3486 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3490 /* Get consistent memory allocated for CT SNS commands */
3491 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3492 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3494 goto fail_free_ms_iocb;
3495 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3496 "ms_iocb=%p ct_sns=%p.\n",
3497 ha->ms_iocb, ha->ct_sns);
3500 /* Allocate memory for request ring */
3501 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3503 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3504 "Failed to allocate memory for req.\n");
3507 (*req)->length = req_len;
3508 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3509 ((*req)->length + 1) * sizeof(request_t),
3510 &(*req)->dma, GFP_KERNEL);
3511 if (!(*req)->ring) {
3512 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3513 "Failed to allocate memory for req_ring.\n");
3516 /* Allocate memory for response ring */
3517 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3519 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3520 "Failed to allocate memory for rsp.\n");
3524 (*rsp)->length = rsp_len;
3525 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3526 ((*rsp)->length + 1) * sizeof(response_t),
3527 &(*rsp)->dma, GFP_KERNEL);
3528 if (!(*rsp)->ring) {
3529 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3530 "Failed to allocate memory for rsp_ring.\n");
3535 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3536 "req=%p req->length=%d req->ring=%p rsp=%p "
3537 "rsp->length=%d rsp->ring=%p.\n",
3538 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3540 /* Allocate memory for NVRAM data for vports */
3541 if (ha->nvram_npiv_size) {
3542 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3543 ha->nvram_npiv_size, GFP_KERNEL);
3544 if (!ha->npiv_info) {
3545 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3546 "Failed to allocate memory for npiv_info.\n");
3547 goto fail_npiv_info;
3550 ha->npiv_info = NULL;
3552 /* Get consistent memory allocated for EX-INIT-CB. */
3553 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3554 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3555 &ha->ex_init_cb_dma);
3556 if (!ha->ex_init_cb)
3557 goto fail_ex_init_cb;
3558 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3559 "ex_init_cb=%p.\n", ha->ex_init_cb);
3562 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3564 /* Get consistent memory allocated for Async Port-Database. */
3565 if (!IS_FWI2_CAPABLE(ha)) {
3566 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3570 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3571 "async_pd=%p.\n", ha->async_pd);
3574 INIT_LIST_HEAD(&ha->vp_list);
3576 /* Allocate memory for our loop_id bitmap */
3577 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3579 if (!ha->loop_id_map)
3582 qla2x00_set_reserved_loop_ids(ha);
3583 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3584 "loop_id_map=%p.\n", ha->loop_id_map);
3590 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3592 kfree(ha->npiv_info);
3594 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3595 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3596 (*rsp)->ring = NULL;
3601 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3602 sizeof(request_t), (*req)->ring, (*req)->dma);
3603 (*req)->ring = NULL;
3608 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3609 ha->ct_sns, ha->ct_sns_dma);
3613 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3615 ha->ms_iocb_dma = 0;
3617 if (IS_QLA82XX(ha) || ql2xenabledif) {
3618 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3619 ha->fcp_cmnd_dma_pool = NULL;
3622 if (IS_QLA82XX(ha) || ql2xenabledif) {
3623 dma_pool_destroy(ha->dl_dma_pool);
3624 ha->dl_dma_pool = NULL;
3627 dma_pool_destroy(ha->s_dma_pool);
3628 ha->s_dma_pool = NULL;
3632 fail_free_ctx_mempool:
3633 mempool_destroy(ha->ctx_mempool);
3634 ha->ctx_mempool = NULL;
3635 fail_free_srb_mempool:
3636 mempool_destroy(ha->srb_mempool);
3637 ha->srb_mempool = NULL;
3639 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3642 ha->gid_list = NULL;
3643 ha->gid_list_dma = 0;
3647 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3650 ha->init_cb_dma = 0;
3652 ql_log(ql_log_fatal, NULL, 0x0030,
3653 "Memory allocation failure.\n");
3658 * qla2x00_free_fw_dump
3659 * Frees fw dump stuff.
3662 * ha = adapter block pointer
3665 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3668 dma_free_coherent(&ha->pdev->dev,
3669 FCE_SIZE, ha->fce, ha->fce_dma);
3672 dma_free_coherent(&ha->pdev->dev,
3673 EFT_SIZE, ha->eft, ha->eft_dma);
3677 if (ha->fw_dump_template)
3678 vfree(ha->fw_dump_template);
3685 ha->fw_dump_cap_flags = 0;
3686 ha->fw_dump_reading = 0;
3688 ha->fw_dump_len = 0;
3689 ha->fw_dump_template = NULL;
3690 ha->fw_dump_template_len = 0;
3695 * Frees all adapter allocated memory.
3698 * ha = adapter block pointer.
3701 qla2x00_mem_free(struct qla_hw_data *ha)
3703 qla2x00_free_fw_dump(ha);
3706 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3709 if (ha->srb_mempool)
3710 mempool_destroy(ha->srb_mempool);
3713 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3714 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3717 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3718 ha->xgmac_data, ha->xgmac_data_dma);
3721 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3722 ha->sns_cmd, ha->sns_cmd_dma);
3725 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3726 ha->ct_sns, ha->ct_sns_dma);
3729 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3732 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3735 dma_pool_free(ha->s_dma_pool,
3736 ha->ex_init_cb, ha->ex_init_cb_dma);
3739 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3742 dma_pool_destroy(ha->s_dma_pool);
3745 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3746 ha->gid_list, ha->gid_list_dma);
3748 if (IS_QLA82XX(ha)) {
3749 if (!list_empty(&ha->gbl_dsd_list)) {
3750 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3752 /* clean up allocated prev pool */
3753 list_for_each_entry_safe(dsd_ptr,
3754 tdsd_ptr, &ha->gbl_dsd_list, list) {
3755 dma_pool_free(ha->dl_dma_pool,
3756 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3757 list_del(&dsd_ptr->list);
3763 if (ha->dl_dma_pool)
3764 dma_pool_destroy(ha->dl_dma_pool);
3766 if (ha->fcp_cmnd_dma_pool)
3767 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3769 if (ha->ctx_mempool)
3770 mempool_destroy(ha->ctx_mempool);
3775 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3776 ha->init_cb, ha->init_cb_dma);
3777 vfree(ha->optrom_buffer);
3779 kfree(ha->npiv_info);
3781 kfree(ha->loop_id_map);
3783 ha->srb_mempool = NULL;
3784 ha->ctx_mempool = NULL;
3786 ha->sns_cmd_dma = 0;
3790 ha->ms_iocb_dma = 0;
3792 ha->init_cb_dma = 0;
3793 ha->ex_init_cb = NULL;
3794 ha->ex_init_cb_dma = 0;
3795 ha->async_pd = NULL;
3796 ha->async_pd_dma = 0;
3798 ha->s_dma_pool = NULL;
3799 ha->dl_dma_pool = NULL;
3800 ha->fcp_cmnd_dma_pool = NULL;
3802 ha->gid_list = NULL;
3803 ha->gid_list_dma = 0;
3805 ha->tgt.atio_ring = NULL;
3806 ha->tgt.atio_dma = 0;
3807 ha->tgt.tgt_vp_map = NULL;
3810 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3811 struct qla_hw_data *ha)
3813 struct Scsi_Host *host;
3814 struct scsi_qla_host *vha = NULL;
3816 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3818 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3819 "Failed to allocate host from the scsi layer, aborting.\n");
3823 /* Clear our data area */
3824 vha = shost_priv(host);
3825 memset(vha, 0, sizeof(scsi_qla_host_t));
3828 vha->host_no = host->host_no;
3831 INIT_LIST_HEAD(&vha->vp_fcports);
3832 INIT_LIST_HEAD(&vha->work_list);
3833 INIT_LIST_HEAD(&vha->list);
3835 spin_lock_init(&vha->work_lock);
3837 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3838 ql_dbg(ql_dbg_init, vha, 0x0041,
3839 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3840 vha->host, vha->hw, vha,
3841 dev_name(&(ha->pdev->dev)));
3849 static struct qla_work_evt *
3850 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3852 struct qla_work_evt *e;
3855 QLA_VHA_MARK_BUSY(vha, bail);
3859 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3861 QLA_VHA_MARK_NOT_BUSY(vha);
3865 INIT_LIST_HEAD(&e->list);
3867 e->flags = QLA_EVT_FLAG_FREE;
3872 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3874 unsigned long flags;
3876 spin_lock_irqsave(&vha->work_lock, flags);
3877 list_add_tail(&e->list, &vha->work_list);
3878 spin_unlock_irqrestore(&vha->work_lock, flags);
3879 qla2xxx_wake_dpc(vha);
3885 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3888 struct qla_work_evt *e;
3890 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3892 return QLA_FUNCTION_FAILED;
3894 e->u.aen.code = code;
3895 e->u.aen.data = data;
3896 return qla2x00_post_work(vha, e);
3900 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3902 struct qla_work_evt *e;
3904 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3906 return QLA_FUNCTION_FAILED;
3908 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3909 return qla2x00_post_work(vha, e);
3912 #define qla2x00_post_async_work(name, type) \
3913 int qla2x00_post_async_##name##_work( \
3914 struct scsi_qla_host *vha, \
3915 fc_port_t *fcport, uint16_t *data) \
3917 struct qla_work_evt *e; \
3919 e = qla2x00_alloc_work(vha, type); \
3921 return QLA_FUNCTION_FAILED; \
3923 e->u.logio.fcport = fcport; \
3925 e->u.logio.data[0] = data[0]; \
3926 e->u.logio.data[1] = data[1]; \
3928 return qla2x00_post_work(vha, e); \
3931 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3932 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3933 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3934 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3935 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3936 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3939 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3941 struct qla_work_evt *e;
3943 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3945 return QLA_FUNCTION_FAILED;
3947 e->u.uevent.code = code;
3948 return qla2x00_post_work(vha, e);
3952 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3954 char event_string[40];
3955 char *envp[] = { event_string, NULL };
3958 case QLA_UEVENT_CODE_FW_DUMP:
3959 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3966 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3970 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3971 uint32_t *data, int cnt)
3973 struct qla_work_evt *e;
3975 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3977 return QLA_FUNCTION_FAILED;
3979 e->u.aenfx.evtcode = evtcode;
3980 e->u.aenfx.count = cnt;
3981 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3982 return qla2x00_post_work(vha, e);
3986 qla2x00_do_work(struct scsi_qla_host *vha)
3988 struct qla_work_evt *e, *tmp;
3989 unsigned long flags;
3992 spin_lock_irqsave(&vha->work_lock, flags);
3993 list_splice_init(&vha->work_list, &work);
3994 spin_unlock_irqrestore(&vha->work_lock, flags);
3996 list_for_each_entry_safe(e, tmp, &work, list) {
3997 list_del_init(&e->list);
4001 fc_host_post_event(vha->host, fc_get_event_number(),
4002 e->u.aen.code, e->u.aen.data);
4004 case QLA_EVT_IDC_ACK:
4005 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4007 case QLA_EVT_ASYNC_LOGIN:
4008 qla2x00_async_login(vha, e->u.logio.fcport,
4011 case QLA_EVT_ASYNC_LOGIN_DONE:
4012 qla2x00_async_login_done(vha, e->u.logio.fcport,
4015 case QLA_EVT_ASYNC_LOGOUT:
4016 qla2x00_async_logout(vha, e->u.logio.fcport);
4018 case QLA_EVT_ASYNC_LOGOUT_DONE:
4019 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4022 case QLA_EVT_ASYNC_ADISC:
4023 qla2x00_async_adisc(vha, e->u.logio.fcport,
4026 case QLA_EVT_ASYNC_ADISC_DONE:
4027 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4030 case QLA_EVT_UEVENT:
4031 qla2x00_uevent_emit(vha, e->u.uevent.code);
4034 qlafx00_process_aen(vha, e);
4037 if (e->flags & QLA_EVT_FLAG_FREE)
4040 /* For each work completed decrement vha ref count */
4041 QLA_VHA_MARK_NOT_BUSY(vha);
4045 /* Relogins all the fcports of a vport
4046 * Context: dpc thread
4048 void qla2x00_relogin(struct scsi_qla_host *vha)
4052 uint16_t next_loopid = 0;
4053 struct qla_hw_data *ha = vha->hw;
4056 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4058 * If the port is not ONLINE then try to login
4059 * to it if we haven't run out of retries.
4061 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4062 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4063 fcport->login_retry--;
4064 if (fcport->flags & FCF_FABRIC_DEVICE) {
4065 if (fcport->flags & FCF_FCP2_DEVICE)
4066 ha->isp_ops->fabric_logout(vha,
4068 fcport->d_id.b.domain,
4069 fcport->d_id.b.area,
4070 fcport->d_id.b.al_pa);
4072 if (fcport->loop_id == FC_NO_LOOP_ID) {
4073 fcport->loop_id = next_loopid =
4074 ha->min_external_loopid;
4075 status = qla2x00_find_new_loop_id(
4077 if (status != QLA_SUCCESS) {
4078 /* Ran out of IDs to use */
4083 if (IS_ALOGIO_CAPABLE(ha)) {
4084 fcport->flags |= FCF_ASYNC_SENT;
4086 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4087 status = qla2x00_post_async_login_work(
4089 if (status == QLA_SUCCESS)
4091 /* Attempt a retry. */
4094 status = qla2x00_fabric_login(vha,
4095 fcport, &next_loopid);
4096 if (status == QLA_SUCCESS) {
4105 qla2x00_get_port_database(
4107 if (status2 != QLA_SUCCESS)
4112 status = qla2x00_local_device_login(vha,
4115 if (status == QLA_SUCCESS) {
4116 fcport->old_loop_id = fcport->loop_id;
4118 ql_dbg(ql_dbg_disc, vha, 0x2003,
4119 "Port login OK: logged in ID 0x%x.\n",
4122 qla2x00_update_fcport(vha, fcport);
4124 } else if (status == 1) {
4125 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4126 /* retry the login again */
4127 ql_dbg(ql_dbg_disc, vha, 0x2007,
4128 "Retrying %d login again loop_id 0x%x.\n",
4129 fcport->login_retry, fcport->loop_id);
4131 fcport->login_retry = 0;
4134 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4135 qla2x00_clear_loop_id(fcport);
4137 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4142 /* Schedule work on any of the dpc-workqueues */
4144 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4146 struct qla_hw_data *ha = base_vha->hw;
4148 switch (work_code) {
4149 case MBA_IDC_AEN: /* 0x8200 */
4151 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4154 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4155 if (!ha->flags.nic_core_reset_hdlr_active) {
4157 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4159 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4160 "NIC Core reset is already active. Skip "
4161 "scheduling it again.\n");
4163 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4165 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4167 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4169 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4172 ql_log(ql_log_warn, base_vha, 0xb05f,
4173 "Unknow work-code=0x%x.\n", work_code);
4179 /* Work: Perform NIC Core Unrecoverable state handling */
4181 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4183 struct qla_hw_data *ha =
4184 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4185 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4186 uint32_t dev_state = 0;
4188 qla83xx_idc_lock(base_vha, 0);
4189 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4190 qla83xx_reset_ownership(base_vha);
4191 if (ha->flags.nic_core_reset_owner) {
4192 ha->flags.nic_core_reset_owner = 0;
4193 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4194 QLA8XXX_DEV_FAILED);
4195 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4196 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4198 qla83xx_idc_unlock(base_vha, 0);
4201 /* Work: Execute IDC state handler */
4203 qla83xx_idc_state_handler_work(struct work_struct *work)
4205 struct qla_hw_data *ha =
4206 container_of(work, struct qla_hw_data, idc_state_handler);
4207 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4208 uint32_t dev_state = 0;
4210 qla83xx_idc_lock(base_vha, 0);
4211 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4212 if (dev_state == QLA8XXX_DEV_FAILED ||
4213 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4214 qla83xx_idc_state_handler(base_vha);
4215 qla83xx_idc_unlock(base_vha, 0);
4219 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4221 int rval = QLA_SUCCESS;
4222 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4223 uint32_t heart_beat_counter1, heart_beat_counter2;
4226 if (time_after(jiffies, heart_beat_wait)) {
4227 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4228 "Nic Core f/w is not alive.\n");
4229 rval = QLA_FUNCTION_FAILED;
4233 qla83xx_idc_lock(base_vha, 0);
4234 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4235 &heart_beat_counter1);
4236 qla83xx_idc_unlock(base_vha, 0);
4238 qla83xx_idc_lock(base_vha, 0);
4239 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4240 &heart_beat_counter2);
4241 qla83xx_idc_unlock(base_vha, 0);
4242 } while (heart_beat_counter1 == heart_beat_counter2);
4247 /* Work: Perform NIC Core Reset handling */
4249 qla83xx_nic_core_reset_work(struct work_struct *work)
4251 struct qla_hw_data *ha =
4252 container_of(work, struct qla_hw_data, nic_core_reset);
4253 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4254 uint32_t dev_state = 0;
4256 if (IS_QLA2031(ha)) {
4257 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4258 ql_log(ql_log_warn, base_vha, 0xb081,
4259 "Failed to dump mctp\n");
4263 if (!ha->flags.nic_core_reset_hdlr_active) {
4264 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4265 qla83xx_idc_lock(base_vha, 0);
4266 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4268 qla83xx_idc_unlock(base_vha, 0);
4269 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4270 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4271 "Nic Core f/w is alive.\n");
4276 ha->flags.nic_core_reset_hdlr_active = 1;
4277 if (qla83xx_nic_core_reset(base_vha)) {
4278 /* NIC Core reset failed. */
4279 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4280 "NIC Core reset failed.\n");
4282 ha->flags.nic_core_reset_hdlr_active = 0;
4286 /* Work: Handle 8200 IDC aens */
4288 qla83xx_service_idc_aen(struct work_struct *work)
4290 struct qla_hw_data *ha =
4291 container_of(work, struct qla_hw_data, idc_aen);
4292 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4293 uint32_t dev_state, idc_control;
4295 qla83xx_idc_lock(base_vha, 0);
4296 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4297 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4298 qla83xx_idc_unlock(base_vha, 0);
4299 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4300 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4301 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4302 "Application requested NIC Core Reset.\n");
4303 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4304 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4306 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4307 "Other protocol driver requested NIC Core Reset.\n");
4308 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4310 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4311 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4312 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4317 qla83xx_wait_logic(void)
4322 if (!in_interrupt()) {
4324 * Wait about 200ms before retrying again.
4325 * This controls the number of retries for single
4331 for (i = 0; i < 20; i++)
4332 cpu_relax(); /* This a nop instr on i386 */
4337 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4341 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4342 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4343 struct qla_hw_data *ha = base_vha->hw;
4344 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4345 "Trying force recovery of the IDC lock.\n");
4347 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4351 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4354 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4355 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4362 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4367 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4368 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4369 ~(idc_lck_rcvry_stage_mask));
4370 rval = qla83xx_wr_reg(base_vha,
4371 QLA83XX_IDC_LOCK_RECOVERY, data);
4375 /* Forcefully perform IDC UnLock */
4376 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4380 /* Clear lock-id by setting 0xff */
4381 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4385 /* Clear lock-recovery by setting 0x0 */
4386 rval = qla83xx_wr_reg(base_vha,
4387 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4398 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4400 int rval = QLA_SUCCESS;
4401 uint32_t o_drv_lockid, n_drv_lockid;
4402 unsigned long lock_recovery_timeout;
4404 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4406 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4410 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4411 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4412 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4415 return QLA_FUNCTION_FAILED;
4418 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4422 if (o_drv_lockid == n_drv_lockid) {
4423 qla83xx_wait_logic();
4433 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4435 uint16_t options = (requester_id << 15) | BIT_6;
4437 uint32_t lock_owner;
4438 struct qla_hw_data *ha = base_vha->hw;
4440 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4442 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4445 /* Setting lock-id to our function-number */
4446 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4449 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4451 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4452 "Failed to acquire IDC lock, acquired by %d, "
4453 "retrying...\n", lock_owner);
4455 /* Retry/Perform IDC-Lock recovery */
4456 if (qla83xx_idc_lock_recovery(base_vha)
4458 qla83xx_wait_logic();
4461 ql_log(ql_log_warn, base_vha, 0xb075,
4462 "IDC Lock recovery FAILED.\n");
4469 /* XXX: IDC-lock implementation using access-control mbx */
4471 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4472 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4473 "Failed to acquire IDC lock. retrying...\n");
4474 /* Retry/Perform IDC-Lock recovery */
4475 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4476 qla83xx_wait_logic();
4479 ql_log(ql_log_warn, base_vha, 0xb076,
4480 "IDC Lock recovery FAILED.\n");
4487 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4489 uint16_t options = (requester_id << 15) | BIT_7, retry;
4491 struct qla_hw_data *ha = base_vha->hw;
4493 /* IDC-unlock implementation using driver-unlock/lock-id
4498 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4500 if (data == ha->portnum) {
4501 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4502 /* Clearing lock-id by setting 0xff */
4503 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4504 } else if (retry < 10) {
4505 /* SV: XXX: IDC unlock retrying needed here? */
4507 /* Retry for IDC-unlock */
4508 qla83xx_wait_logic();
4510 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4511 "Failed to release IDC lock, retyring=%d\n", retry);
4514 } else if (retry < 10) {
4515 /* Retry for IDC-unlock */
4516 qla83xx_wait_logic();
4518 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4519 "Failed to read drv-lockid, retyring=%d\n", retry);
4525 /* XXX: IDC-unlock implementation using access-control mbx */
4528 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4530 /* Retry for IDC-unlock */
4531 qla83xx_wait_logic();
4533 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4534 "Failed to release IDC lock, retyring=%d\n", retry);
4543 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4545 int rval = QLA_SUCCESS;
4546 struct qla_hw_data *ha = vha->hw;
4547 uint32_t drv_presence;
4549 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4550 if (rval == QLA_SUCCESS) {
4551 drv_presence |= (1 << ha->portnum);
4552 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4560 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4562 int rval = QLA_SUCCESS;
4564 qla83xx_idc_lock(vha, 0);
4565 rval = __qla83xx_set_drv_presence(vha);
4566 qla83xx_idc_unlock(vha, 0);
4572 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4574 int rval = QLA_SUCCESS;
4575 struct qla_hw_data *ha = vha->hw;
4576 uint32_t drv_presence;
4578 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4579 if (rval == QLA_SUCCESS) {
4580 drv_presence &= ~(1 << ha->portnum);
4581 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4589 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4591 int rval = QLA_SUCCESS;
4593 qla83xx_idc_lock(vha, 0);
4594 rval = __qla83xx_clear_drv_presence(vha);
4595 qla83xx_idc_unlock(vha, 0);
4601 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4603 struct qla_hw_data *ha = vha->hw;
4604 uint32_t drv_ack, drv_presence;
4605 unsigned long ack_timeout;
4607 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4608 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4610 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4611 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4612 if ((drv_ack & drv_presence) == drv_presence)
4615 if (time_after_eq(jiffies, ack_timeout)) {
4616 ql_log(ql_log_warn, vha, 0xb067,
4617 "RESET ACK TIMEOUT! drv_presence=0x%x "
4618 "drv_ack=0x%x\n", drv_presence, drv_ack);
4620 * The function(s) which did not ack in time are forced
4621 * to withdraw any further participation in the IDC
4624 if (drv_ack != drv_presence)
4625 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4630 qla83xx_idc_unlock(vha, 0);
4632 qla83xx_idc_lock(vha, 0);
4635 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4636 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4640 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4642 int rval = QLA_SUCCESS;
4643 uint32_t idc_control;
4645 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4646 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4648 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4649 __qla83xx_get_idc_control(vha, &idc_control);
4650 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4651 __qla83xx_set_idc_control(vha, 0);
4653 qla83xx_idc_unlock(vha, 0);
4654 rval = qla83xx_restart_nic_firmware(vha);
4655 qla83xx_idc_lock(vha, 0);
4657 if (rval != QLA_SUCCESS) {
4658 ql_log(ql_log_fatal, vha, 0xb06a,
4659 "Failed to restart NIC f/w.\n");
4660 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4661 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4663 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4664 "Success in restarting nic f/w.\n");
4665 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4666 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4672 /* Assumes idc_lock always held on entry */
4674 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4676 struct qla_hw_data *ha = base_vha->hw;
4677 int rval = QLA_SUCCESS;
4678 unsigned long dev_init_timeout;
4681 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4682 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4686 if (time_after_eq(jiffies, dev_init_timeout)) {
4687 ql_log(ql_log_warn, base_vha, 0xb06e,
4688 "Initialization TIMEOUT!\n");
4689 /* Init timeout. Disable further NIC Core
4692 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4693 QLA8XXX_DEV_FAILED);
4694 ql_log(ql_log_info, base_vha, 0xb06f,
4695 "HW State: FAILED.\n");
4698 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4699 switch (dev_state) {
4700 case QLA8XXX_DEV_READY:
4701 if (ha->flags.nic_core_reset_owner)
4702 qla83xx_idc_audit(base_vha,
4703 IDC_AUDIT_COMPLETION);
4704 ha->flags.nic_core_reset_owner = 0;
4705 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4706 "Reset_owner reset by 0x%x.\n",
4709 case QLA8XXX_DEV_COLD:
4710 if (ha->flags.nic_core_reset_owner)
4711 rval = qla83xx_device_bootstrap(base_vha);
4713 /* Wait for AEN to change device-state */
4714 qla83xx_idc_unlock(base_vha, 0);
4716 qla83xx_idc_lock(base_vha, 0);
4719 case QLA8XXX_DEV_INITIALIZING:
4720 /* Wait for AEN to change device-state */
4721 qla83xx_idc_unlock(base_vha, 0);
4723 qla83xx_idc_lock(base_vha, 0);
4725 case QLA8XXX_DEV_NEED_RESET:
4726 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4727 qla83xx_need_reset_handler(base_vha);
4729 /* Wait for AEN to change device-state */
4730 qla83xx_idc_unlock(base_vha, 0);
4732 qla83xx_idc_lock(base_vha, 0);
4734 /* reset timeout value after need reset handler */
4735 dev_init_timeout = jiffies +
4736 (ha->fcoe_dev_init_timeout * HZ);
4738 case QLA8XXX_DEV_NEED_QUIESCENT:
4739 /* XXX: DEBUG for now */
4740 qla83xx_idc_unlock(base_vha, 0);
4742 qla83xx_idc_lock(base_vha, 0);
4744 case QLA8XXX_DEV_QUIESCENT:
4745 /* XXX: DEBUG for now */
4746 if (ha->flags.quiesce_owner)
4749 qla83xx_idc_unlock(base_vha, 0);
4751 qla83xx_idc_lock(base_vha, 0);
4752 dev_init_timeout = jiffies +
4753 (ha->fcoe_dev_init_timeout * HZ);
4755 case QLA8XXX_DEV_FAILED:
4756 if (ha->flags.nic_core_reset_owner)
4757 qla83xx_idc_audit(base_vha,
4758 IDC_AUDIT_COMPLETION);
4759 ha->flags.nic_core_reset_owner = 0;
4760 __qla83xx_clear_drv_presence(base_vha);
4761 qla83xx_idc_unlock(base_vha, 0);
4762 qla8xxx_dev_failed_handler(base_vha);
4763 rval = QLA_FUNCTION_FAILED;
4764 qla83xx_idc_lock(base_vha, 0);
4766 case QLA8XXX_BAD_VALUE:
4767 qla83xx_idc_unlock(base_vha, 0);
4769 qla83xx_idc_lock(base_vha, 0);
4772 ql_log(ql_log_warn, base_vha, 0xb071,
4773 "Unknow Device State: %x.\n", dev_state);
4774 qla83xx_idc_unlock(base_vha, 0);
4775 qla8xxx_dev_failed_handler(base_vha);
4776 rval = QLA_FUNCTION_FAILED;
4777 qla83xx_idc_lock(base_vha, 0);
4787 qla2x00_disable_board_on_pci_error(struct work_struct *work)
4789 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4791 struct pci_dev *pdev = ha->pdev;
4792 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4794 ql_log(ql_log_warn, base_vha, 0x015b,
4795 "Disabling adapter.\n");
4797 set_bit(UNLOADING, &base_vha->dpc_flags);
4799 qla2x00_delete_all_vps(ha, base_vha);
4801 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4803 qla2x00_dfs_remove(base_vha);
4805 qla84xx_put_chip(base_vha);
4807 if (base_vha->timer_active)
4808 qla2x00_stop_timer(base_vha);
4810 base_vha->flags.online = 0;
4812 qla2x00_destroy_deferred_work(ha);
4815 * Do not try to stop beacon blink as it will issue a mailbox
4818 qla2x00_free_sysfs_attr(base_vha, false);
4820 fc_remove_host(base_vha->host);
4822 scsi_remove_host(base_vha->host);
4824 base_vha->flags.init_done = 0;
4825 qla25xx_delete_queues(base_vha);
4826 qla2x00_free_irqs(base_vha);
4827 qla2x00_free_fcports(base_vha);
4828 qla2x00_mem_free(ha);
4829 qla82xx_md_free(base_vha);
4830 qla2x00_free_queues(ha);
4832 qla2x00_unmap_iobases(ha);
4834 pci_release_selected_regions(ha->pdev, ha->bars);
4835 pci_disable_pcie_error_reporting(pdev);
4836 pci_disable_device(pdev);
4839 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4843 /**************************************************************************
4845 * This kernel thread is a task that is schedule by the interrupt handler
4846 * to perform the background processing for interrupts.
4849 * This task always run in the context of a kernel thread. It
4850 * is kick-off by the driver's detect code and starts up
4851 * up one per adapter. It immediately goes to sleep and waits for
4852 * some fibre event. When either the interrupt handler or
4853 * the timer routine detects a event it will one of the task
4854 * bits then wake us up.
4855 **************************************************************************/
4857 qla2x00_do_dpc(void *data)
4860 scsi_qla_host_t *base_vha;
4861 struct qla_hw_data *ha;
4863 ha = (struct qla_hw_data *)data;
4864 base_vha = pci_get_drvdata(ha->pdev);
4866 set_user_nice(current, MIN_NICE);
4868 set_current_state(TASK_INTERRUPTIBLE);
4869 while (!kthread_should_stop()) {
4870 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4871 "DPC handler sleeping.\n");
4874 __set_current_state(TASK_RUNNING);
4876 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4879 if (ha->flags.eeh_busy) {
4880 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4881 "eeh_busy=%d.\n", ha->flags.eeh_busy);
4887 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4888 "DPC handler waking up, dpc_flags=0x%lx.\n",
4889 base_vha->dpc_flags);
4891 qla2x00_do_work(base_vha);
4893 if (IS_P3P_TYPE(ha)) {
4894 if (IS_QLA8044(ha)) {
4895 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4896 &base_vha->dpc_flags)) {
4897 qla8044_idc_lock(ha);
4898 qla8044_wr_direct(base_vha,
4899 QLA8044_CRB_DEV_STATE_INDEX,
4900 QLA8XXX_DEV_FAILED);
4901 qla8044_idc_unlock(ha);
4902 ql_log(ql_log_info, base_vha, 0x4004,
4903 "HW State: FAILED.\n");
4904 qla8044_device_state_handler(base_vha);
4909 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4910 &base_vha->dpc_flags)) {
4911 qla82xx_idc_lock(ha);
4912 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4913 QLA8XXX_DEV_FAILED);
4914 qla82xx_idc_unlock(ha);
4915 ql_log(ql_log_info, base_vha, 0x0151,
4916 "HW State: FAILED.\n");
4917 qla82xx_device_state_handler(base_vha);
4922 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4923 &base_vha->dpc_flags)) {
4925 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4926 "FCoE context reset scheduled.\n");
4927 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4928 &base_vha->dpc_flags))) {
4929 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4930 /* FCoE-ctx reset failed.
4931 * Escalate to chip-reset
4933 set_bit(ISP_ABORT_NEEDED,
4934 &base_vha->dpc_flags);
4936 clear_bit(ABORT_ISP_ACTIVE,
4937 &base_vha->dpc_flags);
4940 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4941 "FCoE context reset end.\n");
4943 } else if (IS_QLAFX00(ha)) {
4944 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4945 &base_vha->dpc_flags)) {
4946 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4947 "Firmware Reset Recovery\n");
4948 if (qlafx00_reset_initialize(base_vha)) {
4949 /* Failed. Abort isp later. */
4950 if (!test_bit(UNLOADING,
4951 &base_vha->dpc_flags)) {
4952 set_bit(ISP_UNRECOVERABLE,
4953 &base_vha->dpc_flags);
4954 ql_dbg(ql_dbg_dpc, base_vha,
4956 "Reset Recovery Failed\n");
4961 if (test_and_clear_bit(FX00_TARGET_SCAN,
4962 &base_vha->dpc_flags)) {
4963 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4964 "ISPFx00 Target Scan scheduled\n");
4965 if (qlafx00_rescan_isp(base_vha)) {
4966 if (!test_bit(UNLOADING,
4967 &base_vha->dpc_flags))
4968 set_bit(ISP_UNRECOVERABLE,
4969 &base_vha->dpc_flags);
4970 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4971 "ISPFx00 Target Scan Failed\n");
4973 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4974 "ISPFx00 Target Scan End\n");
4976 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4977 &base_vha->dpc_flags)) {
4978 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4979 "ISPFx00 Host Info resend scheduled\n");
4980 qlafx00_fx_disc(base_vha,
4981 &base_vha->hw->mr.fcport,
4982 FXDISC_REG_HOST_INFO);
4986 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4987 &base_vha->dpc_flags)) {
4989 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4990 "ISP abort scheduled.\n");
4991 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4992 &base_vha->dpc_flags))) {
4994 if (ha->isp_ops->abort_isp(base_vha)) {
4995 /* failed. retry later */
4996 set_bit(ISP_ABORT_NEEDED,
4997 &base_vha->dpc_flags);
4999 clear_bit(ABORT_ISP_ACTIVE,
5000 &base_vha->dpc_flags);
5003 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5004 "ISP abort end.\n");
5007 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5008 &base_vha->dpc_flags)) {
5009 qla2x00_update_fcports(base_vha);
5012 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5014 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5015 if (ret != QLA_SUCCESS)
5016 ql_log(ql_log_warn, base_vha, 0x121,
5017 "Failed to enable receiving of RSCN "
5018 "requests: 0x%x.\n", ret);
5019 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5023 goto loop_resync_check;
5025 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
5026 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5027 "Quiescence mode scheduled.\n");
5028 if (IS_P3P_TYPE(ha)) {
5030 qla82xx_device_state_handler(base_vha);
5032 qla8044_device_state_handler(base_vha);
5033 clear_bit(ISP_QUIESCE_NEEDED,
5034 &base_vha->dpc_flags);
5035 if (!ha->flags.quiesce_owner) {
5036 qla2x00_perform_loop_resync(base_vha);
5037 if (IS_QLA82XX(ha)) {
5038 qla82xx_idc_lock(ha);
5039 qla82xx_clear_qsnt_ready(
5041 qla82xx_idc_unlock(ha);
5042 } else if (IS_QLA8044(ha)) {
5043 qla8044_idc_lock(ha);
5044 qla8044_clear_qsnt_ready(
5046 qla8044_idc_unlock(ha);
5050 clear_bit(ISP_QUIESCE_NEEDED,
5051 &base_vha->dpc_flags);
5052 qla2x00_quiesce_io(base_vha);
5054 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5055 "Quiescence mode end.\n");
5058 if (test_and_clear_bit(RESET_MARKER_NEEDED,
5059 &base_vha->dpc_flags) &&
5060 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
5062 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5063 "Reset marker scheduled.\n");
5064 qla2x00_rst_aen(base_vha);
5065 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
5066 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5067 "Reset marker end.\n");
5070 /* Retry each device up to login retry count */
5071 if ((test_and_clear_bit(RELOGIN_NEEDED,
5072 &base_vha->dpc_flags)) &&
5073 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5074 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
5076 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5077 "Relogin scheduled.\n");
5078 qla2x00_relogin(base_vha);
5079 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5083 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5084 &base_vha->dpc_flags)) {
5086 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5087 "Loop resync scheduled.\n");
5089 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5090 &base_vha->dpc_flags))) {
5092 rval = qla2x00_loop_resync(base_vha);
5094 clear_bit(LOOP_RESYNC_ACTIVE,
5095 &base_vha->dpc_flags);
5098 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5099 "Loop resync end.\n");
5105 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5106 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5107 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5108 qla2xxx_flash_npiv_conf(base_vha);
5112 if (!ha->interrupts_on)
5113 ha->isp_ops->enable_intrs(ha);
5115 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5116 &base_vha->dpc_flags)) {
5117 if (ha->beacon_blink_led == 1)
5118 ha->isp_ops->beacon_blink(base_vha);
5121 if (!IS_QLAFX00(ha))
5122 qla2x00_do_dpc_all_vps(base_vha);
5126 set_current_state(TASK_INTERRUPTIBLE);
5127 } /* End of while(1) */
5128 __set_current_state(TASK_RUNNING);
5130 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5131 "DPC handler exiting.\n");
5134 * Make sure that nobody tries to wake us up again.
5138 /* Cleanup any residual CTX SRBs. */
5139 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5145 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5147 struct qla_hw_data *ha = vha->hw;
5148 struct task_struct *t = ha->dpc_thread;
5150 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5156 * Processes asynchronous reset.
5159 * ha = adapter block pointer.
5162 qla2x00_rst_aen(scsi_qla_host_t *vha)
5164 if (vha->flags.online && !vha->flags.reset_active &&
5165 !atomic_read(&vha->loop_down_timer) &&
5166 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5168 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5171 * Issue marker command only when we are going to start
5174 vha->marker_needed = 1;
5175 } while (!atomic_read(&vha->loop_down_timer) &&
5176 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5180 /**************************************************************************
5186 * Context: Interrupt
5187 ***************************************************************************/
5189 qla2x00_timer(scsi_qla_host_t *vha)
5191 unsigned long cpu_flags = 0;
5196 struct qla_hw_data *ha = vha->hw;
5197 struct req_que *req;
5199 if (ha->flags.eeh_busy) {
5200 ql_dbg(ql_dbg_timer, vha, 0x6000,
5201 "EEH = %d, restarting timer.\n",
5202 ha->flags.eeh_busy);
5203 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5208 * Hardware read to raise pending EEH errors during mailbox waits. If
5209 * the read returns -1 then disable the board.
5211 if (!pci_channel_offline(ha->pdev)) {
5212 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5213 qla2x00_check_reg16_for_disconnect(vha, w);
5216 /* Make sure qla82xx_watchdog is run only for physical port */
5217 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5218 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5221 qla82xx_watchdog(vha);
5222 else if (IS_QLA8044(ha))
5223 qla8044_watchdog(vha);
5226 if (!vha->vp_idx && IS_QLAFX00(ha))
5227 qlafx00_timer_routine(vha);
5229 /* Loop down handler. */
5230 if (atomic_read(&vha->loop_down_timer) > 0 &&
5231 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5232 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5233 && vha->flags.online) {
5235 if (atomic_read(&vha->loop_down_timer) ==
5236 vha->loop_down_abort_time) {
5238 ql_log(ql_log_info, vha, 0x6008,
5239 "Loop down - aborting the queues before time expires.\n");
5241 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5242 atomic_set(&vha->loop_state, LOOP_DEAD);
5245 * Schedule an ISP abort to return any FCP2-device
5248 /* NPIV - scan physical port only */
5250 spin_lock_irqsave(&ha->hardware_lock,
5252 req = ha->req_q_map[0];
5254 index < req->num_outstanding_cmds;
5258 sp = req->outstanding_cmds[index];
5261 if (sp->type != SRB_SCSI_CMD)
5264 if (!(sfcp->flags & FCF_FCP2_DEVICE))
5268 set_bit(FCOE_CTX_RESET_NEEDED,
5271 set_bit(ISP_ABORT_NEEDED,
5275 spin_unlock_irqrestore(&ha->hardware_lock,
5281 /* if the loop has been down for 4 minutes, reinit adapter */
5282 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5283 if (!(vha->device_flags & DFLG_NO_CABLE)) {
5284 ql_log(ql_log_warn, vha, 0x6009,
5285 "Loop down - aborting ISP.\n");
5288 set_bit(FCOE_CTX_RESET_NEEDED,
5291 set_bit(ISP_ABORT_NEEDED,
5295 ql_dbg(ql_dbg_timer, vha, 0x600a,
5296 "Loop down - seconds remaining %d.\n",
5297 atomic_read(&vha->loop_down_timer));
5299 /* Check if beacon LED needs to be blinked for physical host only */
5300 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5301 /* There is no beacon_blink function for ISP82xx */
5302 if (!IS_P3P_TYPE(ha)) {
5303 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5308 /* Process any deferred work. */
5309 if (!list_empty(&vha->work_list))
5312 /* Schedule the DPC routine if needed */
5313 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5314 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5315 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5317 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5318 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5319 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5320 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5321 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5322 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
5323 ql_dbg(ql_dbg_timer, vha, 0x600b,
5324 "isp_abort_needed=%d loop_resync_needed=%d "
5325 "fcport_update_needed=%d start_dpc=%d "
5326 "reset_marker_needed=%d",
5327 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5328 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5329 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5331 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5332 ql_dbg(ql_dbg_timer, vha, 0x600c,
5333 "beacon_blink_needed=%d isp_unrecoverable=%d "
5334 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5335 "relogin_needed=%d.\n",
5336 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5337 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5338 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5339 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5340 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
5341 qla2xxx_wake_dpc(vha);
5344 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5347 /* Firmware interface routines. */
5350 #define FW_ISP21XX 0
5351 #define FW_ISP22XX 1
5352 #define FW_ISP2300 2
5353 #define FW_ISP2322 3
5354 #define FW_ISP24XX 4
5355 #define FW_ISP25XX 5
5356 #define FW_ISP81XX 6
5357 #define FW_ISP82XX 7
5358 #define FW_ISP2031 8
5359 #define FW_ISP8031 9
5360 #define FW_ISP27XX 10
5362 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5363 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5364 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5365 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5366 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5367 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5368 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5369 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5370 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5371 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5372 #define FW_FILE_ISP27XX "ql2700_fw.bin"
5375 static DEFINE_MUTEX(qla_fw_lock);
5377 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5378 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5379 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5380 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5381 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5382 { .name = FW_FILE_ISP24XX, },
5383 { .name = FW_FILE_ISP25XX, },
5384 { .name = FW_FILE_ISP81XX, },
5385 { .name = FW_FILE_ISP82XX, },
5386 { .name = FW_FILE_ISP2031, },
5387 { .name = FW_FILE_ISP8031, },
5388 { .name = FW_FILE_ISP27XX, },
5392 qla2x00_request_firmware(scsi_qla_host_t *vha)
5394 struct qla_hw_data *ha = vha->hw;
5395 struct fw_blob *blob;
5397 if (IS_QLA2100(ha)) {
5398 blob = &qla_fw_blobs[FW_ISP21XX];
5399 } else if (IS_QLA2200(ha)) {
5400 blob = &qla_fw_blobs[FW_ISP22XX];
5401 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5402 blob = &qla_fw_blobs[FW_ISP2300];
5403 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5404 blob = &qla_fw_blobs[FW_ISP2322];
5405 } else if (IS_QLA24XX_TYPE(ha)) {
5406 blob = &qla_fw_blobs[FW_ISP24XX];
5407 } else if (IS_QLA25XX(ha)) {
5408 blob = &qla_fw_blobs[FW_ISP25XX];
5409 } else if (IS_QLA81XX(ha)) {
5410 blob = &qla_fw_blobs[FW_ISP81XX];
5411 } else if (IS_QLA82XX(ha)) {
5412 blob = &qla_fw_blobs[FW_ISP82XX];
5413 } else if (IS_QLA2031(ha)) {
5414 blob = &qla_fw_blobs[FW_ISP2031];
5415 } else if (IS_QLA8031(ha)) {
5416 blob = &qla_fw_blobs[FW_ISP8031];
5417 } else if (IS_QLA27XX(ha)) {
5418 blob = &qla_fw_blobs[FW_ISP27XX];
5423 mutex_lock(&qla_fw_lock);
5427 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5428 ql_log(ql_log_warn, vha, 0x0063,
5429 "Failed to load firmware image (%s).\n", blob->name);
5436 mutex_unlock(&qla_fw_lock);
5441 qla2x00_release_firmware(void)
5445 mutex_lock(&qla_fw_lock);
5446 for (idx = 0; idx < FW_BLOBS; idx++)
5447 release_firmware(qla_fw_blobs[idx].fw);
5448 mutex_unlock(&qla_fw_lock);
5451 static pci_ers_result_t
5452 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5454 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5455 struct qla_hw_data *ha = vha->hw;
5457 ql_dbg(ql_dbg_aer, vha, 0x9000,
5458 "PCI error detected, state %x.\n", state);
5461 case pci_channel_io_normal:
5462 ha->flags.eeh_busy = 0;
5463 return PCI_ERS_RESULT_CAN_RECOVER;
5464 case pci_channel_io_frozen:
5465 ha->flags.eeh_busy = 1;
5466 /* For ISP82XX complete any pending mailbox cmd */
5467 if (IS_QLA82XX(ha)) {
5468 ha->flags.isp82xx_fw_hung = 1;
5469 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5470 qla82xx_clear_pending_mbx(vha);
5472 qla2x00_free_irqs(vha);
5473 pci_disable_device(pdev);
5474 /* Return back all IOs */
5475 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5476 return PCI_ERS_RESULT_NEED_RESET;
5477 case pci_channel_io_perm_failure:
5478 ha->flags.pci_channel_io_perm_failure = 1;
5479 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5480 return PCI_ERS_RESULT_DISCONNECT;
5482 return PCI_ERS_RESULT_NEED_RESET;
5485 static pci_ers_result_t
5486 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5488 int risc_paused = 0;
5490 unsigned long flags;
5491 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5492 struct qla_hw_data *ha = base_vha->hw;
5493 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5494 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5497 return PCI_ERS_RESULT_RECOVERED;
5499 spin_lock_irqsave(&ha->hardware_lock, flags);
5500 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5501 stat = RD_REG_DWORD(®->hccr);
5502 if (stat & HCCR_RISC_PAUSE)
5504 } else if (IS_QLA23XX(ha)) {
5505 stat = RD_REG_DWORD(®->u.isp2300.host_status);
5506 if (stat & HSR_RISC_PAUSED)
5508 } else if (IS_FWI2_CAPABLE(ha)) {
5509 stat = RD_REG_DWORD(®24->host_status);
5510 if (stat & HSRX_RISC_PAUSED)
5513 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5516 ql_log(ql_log_info, base_vha, 0x9003,
5517 "RISC paused -- mmio_enabled, Dumping firmware.\n");
5518 ha->isp_ops->fw_dump(base_vha, 0);
5520 return PCI_ERS_RESULT_NEED_RESET;
5522 return PCI_ERS_RESULT_RECOVERED;
5526 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5528 uint32_t rval = QLA_FUNCTION_FAILED;
5529 uint32_t drv_active = 0;
5530 struct qla_hw_data *ha = base_vha->hw;
5532 struct pci_dev *other_pdev = NULL;
5534 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5535 "Entered %s.\n", __func__);
5537 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5539 if (base_vha->flags.online) {
5540 /* Abort all outstanding commands,
5541 * so as to be requeued later */
5542 qla2x00_abort_isp_cleanup(base_vha);
5546 fn = PCI_FUNC(ha->pdev->devfn);
5549 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5550 "Finding pci device at function = 0x%x.\n", fn);
5552 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5553 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5558 if (atomic_read(&other_pdev->enable_cnt)) {
5559 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5560 "Found PCI func available and enable at 0x%x.\n",
5562 pci_dev_put(other_pdev);
5565 pci_dev_put(other_pdev);
5570 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5571 "This devfn is reset owner = 0x%x.\n",
5573 qla82xx_idc_lock(ha);
5575 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5576 QLA8XXX_DEV_INITIALIZING);
5578 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5579 QLA82XX_IDC_VERSION);
5581 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5582 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5583 "drv_active = 0x%x.\n", drv_active);
5585 qla82xx_idc_unlock(ha);
5586 /* Reset if device is not already reset
5587 * drv_active would be 0 if a reset has already been done
5590 rval = qla82xx_start_firmware(base_vha);
5593 qla82xx_idc_lock(ha);
5595 if (rval != QLA_SUCCESS) {
5596 ql_log(ql_log_info, base_vha, 0x900b,
5597 "HW State: FAILED.\n");
5598 qla82xx_clear_drv_active(ha);
5599 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5600 QLA8XXX_DEV_FAILED);
5602 ql_log(ql_log_info, base_vha, 0x900c,
5603 "HW State: READY.\n");
5604 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5606 qla82xx_idc_unlock(ha);
5607 ha->flags.isp82xx_fw_hung = 0;
5608 rval = qla82xx_restart_isp(base_vha);
5609 qla82xx_idc_lock(ha);
5610 /* Clear driver state register */
5611 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5612 qla82xx_set_drv_active(base_vha);
5614 qla82xx_idc_unlock(ha);
5616 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5617 "This devfn is not reset owner = 0x%x.\n",
5619 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5620 QLA8XXX_DEV_READY)) {
5621 ha->flags.isp82xx_fw_hung = 0;
5622 rval = qla82xx_restart_isp(base_vha);
5623 qla82xx_idc_lock(ha);
5624 qla82xx_set_drv_active(base_vha);
5625 qla82xx_idc_unlock(ha);
5628 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5633 static pci_ers_result_t
5634 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5636 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5637 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5638 struct qla_hw_data *ha = base_vha->hw;
5639 struct rsp_que *rsp;
5640 int rc, retries = 10;
5642 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5645 /* Workaround: qla2xxx driver which access hardware earlier
5646 * needs error state to be pci_channel_io_online.
5647 * Otherwise mailbox command timesout.
5649 pdev->error_state = pci_channel_io_normal;
5651 pci_restore_state(pdev);
5653 /* pci_restore_state() clears the saved_state flag of the device
5654 * save restored state which resets saved_state flag
5656 pci_save_state(pdev);
5659 rc = pci_enable_device_mem(pdev);
5661 rc = pci_enable_device(pdev);
5664 ql_log(ql_log_warn, base_vha, 0x9005,
5665 "Can't re-enable PCI device after reset.\n");
5666 goto exit_slot_reset;
5669 rsp = ha->rsp_q_map[0];
5670 if (qla2x00_request_irqs(ha, rsp))
5671 goto exit_slot_reset;
5673 if (ha->isp_ops->pci_config(base_vha))
5674 goto exit_slot_reset;
5676 if (IS_QLA82XX(ha)) {
5677 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5678 ret = PCI_ERS_RESULT_RECOVERED;
5679 goto exit_slot_reset;
5681 goto exit_slot_reset;
5684 while (ha->flags.mbox_busy && retries--)
5687 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5688 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5689 ret = PCI_ERS_RESULT_RECOVERED;
5690 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5694 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5695 "slot_reset return %x.\n", ret);
5701 qla2xxx_pci_resume(struct pci_dev *pdev)
5703 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5704 struct qla_hw_data *ha = base_vha->hw;
5707 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5710 ret = qla2x00_wait_for_hba_online(base_vha);
5711 if (ret != QLA_SUCCESS) {
5712 ql_log(ql_log_fatal, base_vha, 0x9002,
5713 "The device failed to resume I/O from slot/link_reset.\n");
5716 pci_cleanup_aer_uncorrect_error_status(pdev);
5718 ha->flags.eeh_busy = 0;
5722 qla83xx_disable_laser(scsi_qla_host_t *vha)
5724 uint32_t reg, data, fn;
5725 struct qla_hw_data *ha = vha->hw;
5726 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5728 /* pci func #/port # */
5729 ql_dbg(ql_dbg_init, vha, 0x004b,
5730 "Disabling Laser for hba: %p\n", vha);
5732 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5733 (BIT_15|BIT_14|BIT_13|BIT_12));
5742 data = LASER_OFF_2031;
5744 qla83xx_wr_reg(vha, reg, data);
5747 static const struct pci_error_handlers qla2xxx_err_handler = {
5748 .error_detected = qla2xxx_pci_error_detected,
5749 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5750 .slot_reset = qla2xxx_pci_slot_reset,
5751 .resume = qla2xxx_pci_resume,
5754 static struct pci_device_id qla2xxx_pci_tbl[] = {
5755 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5756 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5757 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5758 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5759 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5760 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5761 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5762 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5763 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5764 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5765 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5766 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5767 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5768 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5769 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5770 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5771 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5772 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5773 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5774 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
5775 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5778 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5780 static struct pci_driver qla2xxx_pci_driver = {
5781 .name = QLA2XXX_DRIVER_NAME,
5783 .owner = THIS_MODULE,
5785 .id_table = qla2xxx_pci_tbl,
5786 .probe = qla2x00_probe_one,
5787 .remove = qla2x00_remove_one,
5788 .shutdown = qla2x00_shutdown,
5789 .err_handler = &qla2xxx_err_handler,
5792 static const struct file_operations apidev_fops = {
5793 .owner = THIS_MODULE,
5794 .llseek = noop_llseek,
5798 * qla2x00_module_init - Module initialization.
5801 qla2x00_module_init(void)
5805 /* Allocate cache for SRBs. */
5806 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5807 SLAB_HWCACHE_ALIGN, NULL);
5808 if (srb_cachep == NULL) {
5809 ql_log(ql_log_fatal, NULL, 0x0001,
5810 "Unable to allocate SRB cache...Failing load!.\n");
5814 /* Initialize target kmem_cache and mem_pools */
5817 kmem_cache_destroy(srb_cachep);
5819 } else if (ret > 0) {
5821 * If initiator mode is explictly disabled by qlt_init(),
5822 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5823 * performing scsi_scan_target() during LOOP UP event.
5825 qla2xxx_transport_functions.disable_target_scan = 1;
5826 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5829 /* Derive version string. */
5830 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5831 if (ql2xextended_error_logging)
5832 strcat(qla2x00_version_str, "-debug");
5834 qla2xxx_transport_template =
5835 fc_attach_transport(&qla2xxx_transport_functions);
5836 if (!qla2xxx_transport_template) {
5837 kmem_cache_destroy(srb_cachep);
5838 ql_log(ql_log_fatal, NULL, 0x0002,
5839 "fc_attach_transport failed...Failing load!.\n");
5844 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5845 if (apidev_major < 0) {
5846 ql_log(ql_log_fatal, NULL, 0x0003,
5847 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5850 qla2xxx_transport_vport_template =
5851 fc_attach_transport(&qla2xxx_transport_vport_functions);
5852 if (!qla2xxx_transport_vport_template) {
5853 kmem_cache_destroy(srb_cachep);
5855 fc_release_transport(qla2xxx_transport_template);
5856 ql_log(ql_log_fatal, NULL, 0x0004,
5857 "fc_attach_transport vport failed...Failing load!.\n");
5860 ql_log(ql_log_info, NULL, 0x0005,
5861 "QLogic Fibre Channel HBA Driver: %s.\n",
5862 qla2x00_version_str);
5863 ret = pci_register_driver(&qla2xxx_pci_driver);
5865 kmem_cache_destroy(srb_cachep);
5867 fc_release_transport(qla2xxx_transport_template);
5868 fc_release_transport(qla2xxx_transport_vport_template);
5869 ql_log(ql_log_fatal, NULL, 0x0006,
5870 "pci_register_driver failed...ret=%d Failing load!.\n",
5877 * qla2x00_module_exit - Module cleanup.
5880 qla2x00_module_exit(void)
5882 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5883 pci_unregister_driver(&qla2xxx_pci_driver);
5884 qla2x00_release_firmware();
5885 kmem_cache_destroy(srb_cachep);
5888 kmem_cache_destroy(ctx_cachep);
5889 fc_release_transport(qla2xxx_transport_template);
5890 fc_release_transport(qla2xxx_transport_vport_template);
5893 module_init(qla2x00_module_init);
5894 module_exit(qla2x00_module_exit);
5896 MODULE_AUTHOR("QLogic Corporation");
5897 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5898 MODULE_LICENSE("GPL");
5899 MODULE_VERSION(QLA2XXX_VERSION);
5900 MODULE_FIRMWARE(FW_FILE_ISP21XX);
5901 MODULE_FIRMWARE(FW_FILE_ISP22XX);
5902 MODULE_FIRMWARE(FW_FILE_ISP2300);
5903 MODULE_FIRMWARE(FW_FILE_ISP2322);
5904 MODULE_FIRMWARE(FW_FILE_ISP24XX);
5905 MODULE_FIRMWARE(FW_FILE_ISP25XX);