1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/list.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/completion.h>
22 #include <linux/interrupt.h>
23 #include <linux/workqueue.h>
24 #include <linux/firmware.h>
25 #include <linux/mutex.h>
26 #include <linux/btree.h>
28 #include <scsi/scsi.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_device.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <scsi/scsi_transport_fc.h>
33 #include <scsi/scsi_bsg_fc.h>
35 #include <uapi/scsi/fc/fc_els.h>
37 #define QLA_DFS_DEFINE_DENTRY(_debugfs_file_name) \
38 struct dentry *dfs_##_debugfs_file_name
39 #define QLA_DFS_ROOT_DEFINE_DENTRY(_debugfs_file_name) \
40 struct dentry *qla_dfs_##_debugfs_file_name
42 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
49 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
57 * 24 bit port ID type definition.
66 #elif defined(__LITTLE_ENDIAN)
71 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
76 #define INVALID_PORT_ID 0xFFFFFF
83 #define QLA2XXX_DRIVER_NAME "qla2xxx"
84 #define QLA2XXX_APIDEV "ql2xapidev"
85 #define QLA2XXX_MANUFACTURER "Marvell Semiconductor, Inc."
88 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
89 * but that's fine as we don't look at the last 24 ones for
92 #define MAILBOX_REGISTER_COUNT_2100 8
93 #define MAILBOX_REGISTER_COUNT_2200 24
94 #define MAILBOX_REGISTER_COUNT 32
96 #define QLA2200A_RISC_ROM_VER 4
100 #include "qla_settings.h"
102 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
105 * Data bit definitions
119 #define BIT_12 0x1000
120 #define BIT_13 0x2000
121 #define BIT_14 0x4000
122 #define BIT_15 0x8000
123 #define BIT_16 0x10000
124 #define BIT_17 0x20000
125 #define BIT_18 0x40000
126 #define BIT_19 0x80000
127 #define BIT_20 0x100000
128 #define BIT_21 0x200000
129 #define BIT_22 0x400000
130 #define BIT_23 0x800000
131 #define BIT_24 0x1000000
132 #define BIT_25 0x2000000
133 #define BIT_26 0x4000000
134 #define BIT_27 0x8000000
135 #define BIT_28 0x10000000
136 #define BIT_29 0x20000000
137 #define BIT_30 0x40000000
138 #define BIT_31 0x80000000
140 #define LSB(x) ((uint8_t)(x))
141 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
143 #define LSW(x) ((uint16_t)(x))
144 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
146 #define LSD(x) ((uint32_t)((uint64_t)(x)))
147 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
149 static inline uint32_t make_handle(uint16_t x, uint16_t y)
151 return ((uint32_t)x << 16) | y;
158 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)
163 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)
168 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)
173 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)
175 return readb_relaxed(addr);
178 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)
180 return readw_relaxed(addr);
183 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)
185 return readl_relaxed(addr);
188 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)
190 return writeb(data, addr);
193 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)
195 return writew(data, addr);
198 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)
200 return writel(data, addr);
204 * ISP83XX specific remote register addresses
206 #define QLA83XX_LED_PORT0 0x00201320
207 #define QLA83XX_LED_PORT1 0x00201328
208 #define QLA83XX_IDC_DEV_STATE 0x22102384
209 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
210 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
211 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
212 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
213 #define QLA83XX_IDC_CONTROL 0x22102390
214 #define QLA83XX_IDC_AUDIT 0x22102394
215 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
216 #define QLA83XX_DRIVER_LOCKID 0x22102104
217 #define QLA83XX_DRIVER_LOCK 0x8111c028
218 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
219 #define QLA83XX_FLASH_LOCKID 0x22102100
220 #define QLA83XX_FLASH_LOCK 0x8111c010
221 #define QLA83XX_FLASH_UNLOCK 0x8111c014
222 #define QLA83XX_DEV_PARTINFO1 0x221023e0
223 #define QLA83XX_DEV_PARTINFO2 0x221023e4
224 #define QLA83XX_FW_HEARTBEAT 0x221020b0
225 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
226 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
228 /* 83XX: Macros defining 8200 AEN Reason codes */
229 #define IDC_DEVICE_STATE_CHANGE BIT_0
230 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
231 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
232 #define IDC_HEARTBEAT_FAILURE BIT_3
234 /* 83XX: Macros defining 8200 AEN Error-levels */
235 #define ERR_LEVEL_NON_FATAL 0x1
236 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
237 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
239 /* 83XX: Macros for IDC Version */
240 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
241 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
243 /* 83XX: Macros for scheduling dpc tasks */
244 #define QLA83XX_NIC_CORE_RESET 0x1
245 #define QLA83XX_IDC_STATE_HANDLER 0x2
246 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
248 /* 83XX: Macros for defining IDC-Control bits */
249 #define QLA83XX_IDC_RESET_DISABLED BIT_0
250 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
252 /* 83XX: Macros for different timeouts */
253 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
254 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
255 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
257 /* 83XX: Macros for defining class in DEV-Partition Info register */
258 #define QLA83XX_CLASS_TYPE_NONE 0x0
259 #define QLA83XX_CLASS_TYPE_NIC 0x1
260 #define QLA83XX_CLASS_TYPE_FCOE 0x2
261 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
263 /* 83XX: Macros for IDC Lock-Recovery stages */
264 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
267 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
269 /* 83XX: Macros for IDC Audit type */
270 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
271 * dev-state change to NEED-RESET
274 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
275 * reset-recovery completion is
278 /* ISP2031: Values for laser on/off */
279 #define PORT_0_2031 0x00201340
280 #define PORT_1_2031 0x00201350
281 #define LASER_ON_2031 0x01800100
282 #define LASER_OFF_2031 0x01800180
285 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
288 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
289 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
292 * Fibre Channel device definitions.
294 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
295 #define MAX_FIBRE_DEVICES_2100 512
296 #define MAX_FIBRE_DEVICES_2400 2048
297 #define MAX_FIBRE_DEVICES_LOOP 128
298 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
299 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
300 #define MAX_FIBRE_LUNS 0xFFFF
301 #define MAX_HOST_COUNT 16
304 * Host adapter default definitions.
306 #define MAX_BUSES 1 /* We only have one bus today */
308 #define MAX_LUNS MAX_FIBRE_LUNS
309 #define MAX_CMDS_PER_LUN 255
312 * Fibre Channel device definitions.
314 #define SNS_LAST_LOOP_ID_2100 0xfe
315 #define SNS_LAST_LOOP_ID_2300 0x7ff
317 #define LAST_LOCAL_LOOP_ID 0x7d
318 #define SNS_FL_PORT 0x7e
319 #define FABRIC_CONTROLLER 0x7f
320 #define SIMPLE_NAME_SERVER 0x80
321 #define SNS_FIRST_LOOP_ID 0x81
322 #define MANAGEMENT_SERVER 0xfe
323 #define BROADCAST 0xff
326 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
327 * valid range of an N-PORT id is 0 through 0x7ef.
329 #define NPH_LAST_HANDLE 0x7ee
330 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
331 #define NPH_SNS 0x7fc /* FFFFFC */
332 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
333 #define NPH_F_PORT 0x7fe /* FFFFFE */
334 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
336 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
338 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
341 struct name_list_extended {
342 struct get_name_list_extended *l;
344 struct list_head fcports;
350 struct fc_els_ls_rjt *c;
356 * Timeout timer counts in seconds
358 #define PORT_RETRY_TIME 1
359 #define LOOP_DOWN_TIMEOUT 60
360 #define LOOP_DOWN_TIME 255 /* 240 */
361 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
363 #define DEFAULT_OUTSTANDING_COMMANDS 4096
364 #define MIN_OUTSTANDING_COMMANDS 128
366 /* ISP request and response entry counts (37-65535) */
367 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
368 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
369 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
370 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
371 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
372 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
373 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
374 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
375 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
376 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
377 #define FW_DEF_EXCHANGES_CNT 2048
378 #define FW_MAX_EXCHANGES_CNT (32 * 1024)
379 #define REDUCE_EXCHANGES_CNT (8 * 1024)
381 #define SET_DID_STATUS(stat_var, status) (stat_var = status << 16)
388 #define TAG_FREED 0xffff
397 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
398 uint32_t request_sense_length;
399 uint32_t fw_sense_length;
400 uint8_t *request_sense_ptr;
401 struct crc_context *crc_ctx;
402 struct ct6_dsd ct6_ctx;
403 struct qla_buf_dsc buf_dsc;
407 * SRB flag definitions
409 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
410 #define SRB_GOT_BUF BIT_1
411 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
412 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
413 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
414 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
415 #define SRB_WAKEUP_ON_COMP BIT_6
416 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
417 #define SRB_EDIF_CLEANUP_DELETE BIT_9
419 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
420 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
421 #define ISP_REG16_DISCONNECT 0xFFFF
423 static inline le_id_t be_id_to_le(be_id_t id)
427 res.domain = id.domain;
429 res.al_pa = id.al_pa;
434 static inline be_id_t le_id_to_be(le_id_t id)
438 res.domain = id.domain;
440 res.al_pa = id.al_pa;
445 static inline port_id_t be_to_port_id(be_id_t id)
449 res.b.domain = id.domain;
450 res.b.area = id.area;
451 res.b.al_pa = id.al_pa;
457 static inline be_id_t port_id_to_be_id(port_id_t port_id)
461 res.domain = port_id.b.domain;
462 res.area = port_id.b.area;
463 res.al_pa = port_id.b.al_pa;
469 struct qla_qpair *qpair;
470 struct fc_port *fcport;
471 struct scsi_qla_host *vha;
477 struct els_logo_payload {
482 uint8_t wwpn[WWN_SIZE];
485 struct els_plogi_payload {
488 __be32 data[112 / 4];
498 u32 req_allocated_size;
499 u32 rsp_allocated_size;
512 #define SRB_LOGIN_RETRIED BIT_0
513 #define SRB_LOGIN_COND_PLOGI BIT_1
514 #define SRB_LOGIN_SKIP_PRLI BIT_2
515 #define SRB_LOGIN_NVME_PRLI BIT_3
516 #define SRB_LOGIN_PRLI_ONLY BIT_4
517 #define SRB_LOGIN_FCSP BIT_5
522 #define ELS_DCMD_TIMEOUT 20
523 #define ELS_DCMD_LOGO 0x5
526 struct completion comp;
527 struct els_logo_payload *els_logo_pyld;
528 dma_addr_t els_logo_pyld_dma;
531 #define ELS_DCMD_PLOGI 0x3
534 struct completion comp;
535 struct els_plogi_payload *els_plogi_pyld;
536 struct els_plogi_payload *els_resp_pyld;
539 dma_addr_t els_plogi_pyld_dma;
540 dma_addr_t els_resp_pyld_dma;
547 * Values for flags field below are as
548 * defined in tsk_mgmt_entry struct
549 * for control_flags field in qla_fw.h.
554 struct completion comp;
562 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
563 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
564 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
565 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
566 #define FXDISC_TIMEOUT 20
572 dma_addr_t req_dma_handle;
573 dma_addr_t rsp_dma_handle;
575 __le32 adapter_id_hi;
576 __le16 req_func_type;
578 __le32 req_data_extra;
582 struct completion fxiocb_comp;
590 struct completion comp;
593 #define MAX_IOCB_MB_REG 28
594 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
596 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
597 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
599 dma_addr_t out_dma, in_dma;
600 struct completion comp;
604 struct imm_ntfy_from_isp *ntfy;
612 /* These are only used with ls4 requests */
617 enum nvmefc_fcp_datadir dir;
619 uint32_t timeout_sec;
620 struct list_head entry;
627 struct edif_sa_ctl *sa_ctl;
628 struct qla_sa_update_frame sa_frame;
632 struct timer_list timer;
633 void (*timeout)(void *);
636 /* Values for srb_ctx type */
637 #define SRB_LOGIN_CMD 1
638 #define SRB_LOGOUT_CMD 2
639 #define SRB_ELS_CMD_RPT 3
640 #define SRB_ELS_CMD_HST 4
642 #define SRB_ADISC_CMD 6
644 #define SRB_SCSI_CMD 8
645 #define SRB_BIDI_CMD 9
646 #define SRB_FXIOCB_DCMD 10
647 #define SRB_FXIOCB_BCMD 11
648 #define SRB_ABT_CMD 12
649 #define SRB_ELS_DCMD 13
650 #define SRB_MB_IOCB 14
651 #define SRB_CT_PTHRU_CMD 15
652 #define SRB_NACK_PLOGI 16
653 #define SRB_NACK_PRLI 17
654 #define SRB_NACK_LOGO 18
655 #define SRB_NVME_CMD 19
656 #define SRB_NVME_LS 20
657 #define SRB_PRLI_CMD 21
658 #define SRB_CTRL_VP 22
659 #define SRB_PRLO_CMD 23
660 #define SRB_SA_UPDATE 25
661 #define SRB_ELS_CMD_HST_NOLOGIN 26
662 #define SRB_SA_REPLACE 27
663 #define SRB_MARKER 28
665 struct qla_els_pt_arg {
669 u16 control_flags, ox_id;
670 __le32 rx_xchg_address;
672 u32 tx_len, tx_byte_count, rx_len, rx_byte_count;
673 dma_addr_t tx_addr, rx_addr;
680 TYPE_TGT_TMCMD, /* task management */
683 struct iocb_resource {
690 struct bsg_job *bsg_job;
692 struct qla_els_pt_arg els_arg;
698 * Do not move cmd_type field, it needs to
699 * line up with qla_tgt_cmd->cmd_type
703 struct iocb_resource iores;
704 struct kref cmd_kref; /* need to migrate ref_count over to this */
706 struct fc_port *fcport;
707 struct scsi_qla_host *vha;
708 unsigned int start_timer:1;
715 struct qla_qpair *qpair;
717 struct list_head elem;
718 u32 gen1; /* scratch */
719 u32 gen2; /* scratch */
722 struct completion *comp;
724 struct srb_iocb iocb_cmd;
725 struct bsg_job *bsg_job;
727 struct bsg_cmd bsg_cmd;
743 * Report completion status @res and call sp_put(@sp). @res is
744 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a
745 * QLA_* status value.
747 void (*done)(struct srb *sp, int res);
748 /* Stop the timer and free @sp. Only used by the FCP code. */
749 void (*free)(struct srb *sp);
751 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe
754 void (*put_fn)(struct kref *kref);
757 * Report completion for asynchronous commands.
759 void (*async_done)(struct srb *sp, int res);
762 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
764 #define GET_CMD_SENSE_LEN(sp) \
765 (sp->u.scmd.request_sense_length)
766 #define SET_CMD_SENSE_LEN(sp, len) \
767 (sp->u.scmd.request_sense_length = len)
768 #define GET_CMD_SENSE_PTR(sp) \
769 (sp->u.scmd.request_sense_ptr)
770 #define SET_CMD_SENSE_PTR(sp, ptr) \
771 (sp->u.scmd.request_sense_ptr = ptr)
772 #define GET_FW_SENSE_LEN(sp) \
773 (sp->u.scmd.fw_sense_length)
774 #define SET_FW_SENSE_LEN(sp, len) \
775 (sp->u.scmd.fw_sense_length = len)
783 uint32_t transfer_size;
784 uint32_t iteration_count;
788 * ISP I/O Register Set structure definitions.
790 struct device_reg_2xxx {
791 __le16 flash_address; /* Flash BIOS address */
792 __le16 flash_data; /* Flash BIOS data */
793 __le16 unused_1[1]; /* Gap */
794 __le16 ctrl_status; /* Control/Status */
795 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
796 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
797 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
799 __le16 ictrl; /* Interrupt control */
800 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
801 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
803 __le16 istatus; /* Interrupt status */
804 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
806 __le16 semaphore; /* Semaphore */
807 __le16 nvram; /* NVRAM register. */
808 #define NVR_DESELECT 0
809 #define NVR_BUSY BIT_15
810 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
811 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
812 #define NVR_DATA_IN BIT_3
813 #define NVR_DATA_OUT BIT_2
814 #define NVR_SELECT BIT_1
815 #define NVR_CLOCK BIT_0
817 #define NVR_WAIT_CNT 20000
829 __le16 unused_2[59]; /* Gap */
830 } __attribute__((packed)) isp2100;
833 __le16 req_q_in; /* In-Pointer */
834 __le16 req_q_out; /* Out-Pointer */
836 __le16 rsp_q_in; /* In-Pointer */
837 __le16 rsp_q_out; /* Out-Pointer */
839 /* RISC to Host Status */
841 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
842 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
844 /* Host to Host Semaphore */
845 __le16 host_semaphore;
846 __le16 unused_3[17]; /* Gap */
880 __le16 unused_4[10]; /* Gap */
881 } __attribute__((packed)) isp2300;
884 __le16 fpm_diag_config;
885 __le16 unused_5[0x4]; /* Gap */
887 __le16 unused_5_1; /* Gap */
888 __le16 pcr; /* Processor Control Register. */
889 __le16 unused_6[0x5]; /* Gap */
890 __le16 mctr; /* Memory Configuration and Timing. */
891 __le16 unused_7[0x3]; /* Gap */
892 __le16 fb_cmd_2100; /* Unused on 23XX */
893 __le16 unused_8[0x3]; /* Gap */
894 __le16 hccr; /* Host command & control register. */
895 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
896 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
898 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
899 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
900 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
901 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
902 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
903 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
904 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
905 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
907 __le16 unused_9[5]; /* Gap */
908 __le16 gpiod; /* GPIO Data register. */
909 __le16 gpioe; /* GPIO Enable register. */
910 #define GPIO_LED_MASK 0x00C0
911 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
912 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
913 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
914 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
915 #define GPIO_LED_ALL_OFF 0x0000
916 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
917 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
921 __le16 unused_10[8]; /* Gap */
937 __le16 mailbox23; /* Also probe reg. */
938 } __attribute__((packed)) isp2200;
942 struct device_reg_25xxmq {
952 struct device_reg_fx00 {
953 __le32 mailbox0; /* 00 */
954 __le32 mailbox1; /* 04 */
955 __le32 mailbox2; /* 08 */
956 __le32 mailbox3; /* 0C */
957 __le32 mailbox4; /* 10 */
958 __le32 mailbox5; /* 14 */
959 __le32 mailbox6; /* 18 */
960 __le32 mailbox7; /* 1C */
961 __le32 mailbox8; /* 20 */
962 __le32 mailbox9; /* 24 */
963 __le32 mailbox10; /* 28 */
994 __le32 req_q_in; /* A0 - Request Queue In-Pointer */
995 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */
996 /* Response Queue. */
997 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */
998 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */
999 /* Init values shadowed on FW Up Event */
1000 __le32 initval0; /* B0 */
1001 __le32 initval1; /* B4 */
1002 __le32 initval2; /* B8 */
1003 __le32 initval3; /* BC */
1004 __le32 initval4; /* C0 */
1005 __le32 initval5; /* C4 */
1006 __le32 initval6; /* C8 */
1007 __le32 initval7; /* CC */
1008 __le32 fwheartbeat; /* D0 */
1009 __le32 pseudoaen; /* D4 */
1015 struct device_reg_2xxx isp;
1016 struct device_reg_24xx isp24;
1017 struct device_reg_25xxmq isp25mq;
1018 struct device_reg_82xx isp82;
1019 struct device_reg_fx00 ispfx00;
1020 } __iomem device_reg_t;
1022 #define ISP_REQ_Q_IN(ha, reg) \
1023 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1024 &(reg)->u.isp2100.mailbox4 : \
1025 &(reg)->u.isp2300.req_q_in)
1026 #define ISP_REQ_Q_OUT(ha, reg) \
1027 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1028 &(reg)->u.isp2100.mailbox4 : \
1029 &(reg)->u.isp2300.req_q_out)
1030 #define ISP_RSP_Q_IN(ha, reg) \
1031 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1032 &(reg)->u.isp2100.mailbox5 : \
1033 &(reg)->u.isp2300.rsp_q_in)
1034 #define ISP_RSP_Q_OUT(ha, reg) \
1035 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1036 &(reg)->u.isp2100.mailbox5 : \
1037 &(reg)->u.isp2300.rsp_q_out)
1039 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
1040 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
1042 #define MAILBOX_REG(ha, reg, num) \
1043 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1045 &(reg)->u.isp2100.mailbox0 + (num) : \
1046 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
1047 &(reg)->u.isp2300.mailbox0 + (num))
1048 #define RD_MAILBOX_REG(ha, reg, num) \
1049 rd_reg_word(MAILBOX_REG(ha, reg, num))
1050 #define WRT_MAILBOX_REG(ha, reg, num, data) \
1051 wrt_reg_word(MAILBOX_REG(ha, reg, num), data)
1053 #define FB_CMD_REG(ha, reg) \
1054 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1055 &(reg)->fb_cmd_2100 : \
1056 &(reg)->u.isp2300.fb_cmd)
1057 #define RD_FB_CMD_REG(ha, reg) \
1058 rd_reg_word(FB_CMD_REG(ha, reg))
1059 #define WRT_FB_CMD_REG(ha, reg, data) \
1060 wrt_reg_word(FB_CMD_REG(ha, reg), data)
1063 uint32_t out_mb; /* outbound from driver */
1064 uint32_t in_mb; /* Incoming from RISC */
1065 uint16_t mb[MAILBOX_REGISTER_COUNT];
1070 #define MBX_DMA_IN BIT_0
1071 #define MBX_DMA_OUT BIT_1
1072 #define IOCTL_CMD BIT_2
1076 uint32_t out_mb; /* outbound from driver */
1077 uint32_t in_mb; /* Incoming from RISC */
1078 uint32_t mb[MAILBOX_REGISTER_COUNT];
1083 #define MBX_DMA_IN BIT_0
1084 #define MBX_DMA_OUT BIT_1
1085 #define IOCTL_CMD BIT_2
1089 #define MBX_TOV_SECONDS 30
1092 * ISP product identification definitions in mailboxes after reset.
1094 #define PROD_ID_1 0x4953
1095 #define PROD_ID_2 0x0000
1096 #define PROD_ID_2a 0x5020
1097 #define PROD_ID_3 0x2020
1100 * ISP mailbox Self-Test status codes
1102 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
1103 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
1104 #define MBS_BUSY 4 /* Busy. */
1107 * ISP mailbox command complete status codes
1109 #define MBS_COMMAND_COMPLETE 0x4000
1110 #define MBS_INVALID_COMMAND 0x4001
1111 #define MBS_HOST_INTERFACE_ERROR 0x4002
1112 #define MBS_TEST_FAILED 0x4003
1113 #define MBS_COMMAND_ERROR 0x4005
1114 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
1115 #define MBS_PORT_ID_USED 0x4007
1116 #define MBS_LOOP_ID_USED 0x4008
1117 #define MBS_ALL_IDS_IN_USE 0x4009
1118 #define MBS_NOT_LOGGED_IN 0x400A
1119 #define MBS_LINK_DOWN_ERROR 0x400B
1120 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1122 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
1124 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
1128 * ISP mailbox asynchronous event status codes
1130 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
1131 #define MBA_RESET 0x8001 /* Reset Detected. */
1132 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
1133 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
1134 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
1135 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
1136 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
1138 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
1139 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
1140 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
1141 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
1142 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
1143 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
1144 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
1145 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
1146 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */
1147 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
1148 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
1149 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
1150 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
1151 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
1152 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
1153 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
1154 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
1156 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
1157 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
1158 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
1159 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
1160 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
1161 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
1162 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
1163 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
1164 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
1165 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
1166 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
1167 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
1168 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
1169 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
1170 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
1171 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
1172 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
1173 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
1174 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
1175 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
1176 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
1177 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
1178 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */
1179 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
1180 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
1182 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
1183 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
1184 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
1185 /* 83XX FCoE specific */
1186 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
1188 /* Interrupt type codes */
1189 #define INTR_ROM_MB_SUCCESS 0x1
1190 #define INTR_ROM_MB_FAILED 0x2
1191 #define INTR_MB_SUCCESS 0x10
1192 #define INTR_MB_FAILED 0x11
1193 #define INTR_ASYNC_EVENT 0x12
1194 #define INTR_RSP_QUE_UPDATE 0x13
1195 #define INTR_RSP_QUE_UPDATE_83XX 0x14
1196 #define INTR_ATIO_QUE_UPDATE 0x1C
1197 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
1198 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E
1200 /* ISP mailbox loopback echo diagnostic error code */
1201 #define MBS_LB_RESET 0x17
1203 /* AEN mailbox Port Diagnostics test */
1204 #define AEN_START_DIAG_TEST 0x0 /* start the diagnostics */
1205 #define AEN_DONE_DIAG_TEST_WITH_NOERR 0x1 /* Done with no errors */
1206 #define AEN_DONE_DIAG_TEST_WITH_ERR 0x2 /* Done with error.*/
1209 * Firmware options 1, 2, 3.
1211 #define FO1_AE_ON_LIPF8 BIT_0
1212 #define FO1_AE_ALL_LIP_RESET BIT_1
1213 #define FO1_CTIO_RETRY BIT_3
1214 #define FO1_DISABLE_LIP_F7_SW BIT_4
1215 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1216 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1217 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1218 #define FO1_SET_EMPHASIS_SWING BIT_8
1219 #define FO1_AE_AUTO_BYPASS BIT_9
1220 #define FO1_ENABLE_PURE_IOCB BIT_10
1221 #define FO1_AE_PLOGI_RJT BIT_11
1222 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1223 #define FO1_AE_QUEUE_FULL BIT_13
1225 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1226 #define FO2_REV_LOOPBACK BIT_1
1228 #define FO3_ENABLE_EMERG_IOCB BIT_0
1229 #define FO3_AE_RND_ERROR BIT_1
1231 /* 24XX additional firmware options */
1232 #define ADD_FO_COUNT 3
1233 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
1234 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1236 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1238 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1241 * ISP mailbox commands
1243 #define MBC_LOAD_RAM 1 /* Load RAM. */
1244 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
1245 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
1246 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
1247 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
1248 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
1249 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
1250 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
1251 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
1252 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
1253 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
1254 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
1255 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
1256 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
1257 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1258 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
1259 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
1260 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
1261 #define MBC_RESET 0x18 /* Reset. */
1262 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
1263 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
1264 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
1265 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
1266 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
1267 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
1268 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
1269 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
1270 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */
1271 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1272 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1273 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
1274 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
1275 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
1276 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
1277 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
1278 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
1279 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
1280 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
1281 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
1282 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
1283 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
1284 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
1285 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
1286 #define MBC_DATA_RATE 0x5d /* Data Rate */
1287 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
1288 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
1289 /* Initialization Procedure */
1290 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
1291 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
1292 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
1293 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
1294 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
1295 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
1296 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
1297 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
1298 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
1299 #define MBC_LIP_RESET 0x6c /* LIP reset. */
1300 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
1302 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
1303 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
1304 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
1305 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1306 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1307 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1308 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1309 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1310 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1311 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1312 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
1315 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1316 * should be defined with MBC_MR_*
1318 #define MBC_MR_DRV_SHUTDOWN 0x6A
1321 * ISP24xx mailbox commands
1323 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1324 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1325 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1326 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1327 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1328 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1329 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1330 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1331 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1332 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1333 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1334 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1335 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1336 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1337 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1338 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1339 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1340 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1341 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1342 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1343 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1344 #define MBC_PORT_RESET 0x120 /* Port Reset */
1345 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1346 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1349 * ISP81xx mailbox commands
1351 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1354 * ISP8044 mailbox commands
1356 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1357 #define HCS_WRITE_SERDES 0x3
1358 #define HCS_READ_SERDES 0x4
1360 /* Firmware return data sizes */
1361 #define FCAL_MAP_SIZE 128
1363 /* Mailbox bit definitions for out_mb and in_mb */
1364 #define MBX_31 BIT_31
1365 #define MBX_30 BIT_30
1366 #define MBX_29 BIT_29
1367 #define MBX_28 BIT_28
1368 #define MBX_27 BIT_27
1369 #define MBX_26 BIT_26
1370 #define MBX_25 BIT_25
1371 #define MBX_24 BIT_24
1372 #define MBX_23 BIT_23
1373 #define MBX_22 BIT_22
1374 #define MBX_21 BIT_21
1375 #define MBX_20 BIT_20
1376 #define MBX_19 BIT_19
1377 #define MBX_18 BIT_18
1378 #define MBX_17 BIT_17
1379 #define MBX_16 BIT_16
1380 #define MBX_15 BIT_15
1381 #define MBX_14 BIT_14
1382 #define MBX_13 BIT_13
1383 #define MBX_12 BIT_12
1384 #define MBX_11 BIT_11
1385 #define MBX_10 BIT_10
1397 #define RNID_TYPE_ELS_CMD 0x5
1398 #define RNID_TYPE_PORT_LOGIN 0x7
1399 #define RNID_BUFFER_CREDITS 0x8
1400 #define RNID_TYPE_SET_VERSION 0x9
1401 #define RNID_TYPE_ASIC_TEMP 0xC
1403 #define ELS_CMD_MAP_SIZE 32
1406 * Firmware state codes from get firmware state mailbox command
1408 #define FSTATE_CONFIG_WAIT 0
1409 #define FSTATE_WAIT_AL_PA 1
1410 #define FSTATE_WAIT_LOGIN 2
1411 #define FSTATE_READY 3
1412 #define FSTATE_LOSS_OF_SYNC 4
1413 #define FSTATE_ERROR 5
1414 #define FSTATE_REINIT 6
1415 #define FSTATE_NON_PART 7
1417 #define FSTATE_CONFIG_CORRECT 0
1418 #define FSTATE_P2P_RCV_LIP 1
1419 #define FSTATE_P2P_CHOOSE_LOOP 2
1420 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1421 #define FSTATE_FATAL_ERROR 4
1422 #define FSTATE_LOOP_BACK_CONN 5
1424 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1425 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1426 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1427 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1428 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1429 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1430 #define QLA27XX_DEFAULT_IMAGE 0
1431 #define QLA27XX_PRIMARY_IMAGE 1
1432 #define QLA27XX_SECONDARY_IMAGE 2
1435 * Port Database structure definition
1436 * Little endian except where noted.
1438 #define PORT_DATABASE_SIZE 128 /* bytes */
1442 uint8_t master_state;
1443 uint8_t slave_state;
1444 uint8_t reserved[2];
1445 uint8_t hard_address;
1448 uint8_t node_name[WWN_SIZE];
1449 uint8_t port_name[WWN_SIZE];
1450 __le16 execution_throttle;
1451 uint16_t execution_count;
1452 uint8_t reset_count;
1454 uint16_t resource_allocation;
1455 uint16_t current_allocation;
1456 uint16_t queue_head;
1457 uint16_t queue_tail;
1458 uint16_t transmit_execution_list_next;
1459 uint16_t transmit_execution_list_previous;
1460 uint16_t common_features;
1461 uint16_t total_concurrent_sequences;
1462 uint16_t RO_by_information_category;
1465 uint16_t receive_data_size;
1466 uint16_t concurrent_sequences;
1467 uint16_t open_sequences_per_exchange;
1468 uint16_t lun_abort_flags;
1469 uint16_t lun_stop_flags;
1470 uint16_t stop_queue_head;
1471 uint16_t stop_queue_tail;
1472 uint16_t port_retry_timer;
1473 uint16_t next_sequence_id;
1474 uint16_t frame_count;
1475 uint16_t PRLI_payload_length;
1476 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1477 /* Bits 15-0 of word 0 */
1478 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1479 /* Bits 15-0 of word 3 */
1481 uint16_t extended_lun_info_list_pointer;
1482 uint16_t extended_lun_stop_list_pointer;
1486 * Port database slave/master states
1488 #define PD_STATE_DISCOVERY 0
1489 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1490 #define PD_STATE_PORT_LOGIN 2
1491 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1492 #define PD_STATE_PROCESS_LOGIN 4
1493 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1494 #define PD_STATE_PORT_LOGGED_IN 6
1495 #define PD_STATE_PORT_UNAVAILABLE 7
1496 #define PD_STATE_PROCESS_LOGOUT 8
1497 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1498 #define PD_STATE_PORT_LOGOUT 10
1499 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1502 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1503 #define QLA_ZIO_DISABLED 0
1504 #define QLA_ZIO_DEFAULT_TIMER 2
1507 * ISP Initialization Control Block.
1508 * Little endian except where noted.
1510 #define ICB_VERSION 1
1516 * LSB BIT 0 = Enable Hard Loop Id
1517 * LSB BIT 1 = Enable Fairness
1518 * LSB BIT 2 = Enable Full-Duplex
1519 * LSB BIT 3 = Enable Fast Posting
1520 * LSB BIT 4 = Enable Target Mode
1521 * LSB BIT 5 = Disable Initiator Mode
1522 * LSB BIT 6 = Enable ADISC
1523 * LSB BIT 7 = Enable Target Inquiry Data
1525 * MSB BIT 0 = Enable PDBC Notify
1526 * MSB BIT 1 = Non Participating LIP
1527 * MSB BIT 2 = Descending Loop ID Search
1528 * MSB BIT 3 = Acquire Loop ID in LIPA
1529 * MSB BIT 4 = Stop PortQ on Full Status
1530 * MSB BIT 5 = Full Login after LIP
1531 * MSB BIT 6 = Node Name Option
1532 * MSB BIT 7 = Ext IFWCB enable bit
1534 uint8_t firmware_options[2];
1536 __le16 frame_payload_size;
1537 __le16 max_iocb_allocation;
1538 __le16 execution_throttle;
1539 uint8_t retry_count;
1540 uint8_t retry_delay; /* unused */
1541 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1542 uint16_t hard_address;
1543 uint8_t inquiry_data;
1544 uint8_t login_timeout;
1545 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1547 __le16 request_q_outpointer;
1548 __le16 response_q_inpointer;
1549 __le16 request_q_length;
1550 __le16 response_q_length;
1551 __le64 request_q_address __packed;
1552 __le64 response_q_address __packed;
1555 uint8_t command_resource_count;
1556 uint8_t immediate_notify_resource_count;
1558 uint8_t reserved_2[2];
1561 * LSB BIT 0 = Timer Operation mode bit 0
1562 * LSB BIT 1 = Timer Operation mode bit 1
1563 * LSB BIT 2 = Timer Operation mode bit 2
1564 * LSB BIT 3 = Timer Operation mode bit 3
1565 * LSB BIT 4 = Init Config Mode bit 0
1566 * LSB BIT 5 = Init Config Mode bit 1
1567 * LSB BIT 6 = Init Config Mode bit 2
1568 * LSB BIT 7 = Enable Non part on LIHA failure
1570 * MSB BIT 0 = Enable class 2
1571 * MSB BIT 1 = Enable ACK0
1574 * MSB BIT 4 = FC Tape Enable
1575 * MSB BIT 5 = Enable FC Confirm
1576 * MSB BIT 6 = Enable command queuing in target mode
1577 * MSB BIT 7 = No Logo On Link Down
1579 uint8_t add_firmware_options[2];
1581 uint8_t response_accumulation_timer;
1582 uint8_t interrupt_delay_timer;
1585 * LSB BIT 0 = Enable Read xfr_rdy
1586 * LSB BIT 1 = Soft ID only
1589 * LSB BIT 4 = FCP RSP Payload [0]
1590 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1591 * LSB BIT 6 = Enable Out-of-Order frame handling
1592 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1594 * MSB BIT 0 = Sbus enable - 2300
1598 * MSB BIT 4 = LED mode
1599 * MSB BIT 5 = enable 50 ohm termination
1600 * MSB BIT 6 = Data Rate (2300 only)
1601 * MSB BIT 7 = Data Rate (2300 only)
1603 uint8_t special_options[2];
1605 uint8_t reserved_3[26];
1608 /* Special Features Control Block */
1613 * BIT 15-14 = Reserved
1614 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled)
1615 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled)
1616 * BIT 11-0 = Reserved
1619 uint8_t reserved1[32];
1620 uint16_t discard_OHRB_timeout_value;
1621 uint16_t remote_write_opt_queue_num;
1622 uint8_t reserved2[40];
1623 uint8_t scm_related_parameter[16];
1624 uint8_t reserved3[32];
1628 * Get Link Status mailbox command return buffer.
1630 #define GLSO_SEND_RPS BIT_0
1631 #define GLSO_USE_DID BIT_3
1633 struct link_statistics {
1634 __le32 link_fail_cnt;
1635 __le32 loss_sync_cnt;
1636 __le32 loss_sig_cnt;
1637 __le32 prim_seq_err_cnt;
1638 __le32 inval_xmit_word_cnt;
1639 __le32 inval_crc_cnt;
1642 __le32 link_down_loop_init_tmo;
1643 __le32 link_down_los;
1644 __le32 link_down_loss_rcv_clk;
1645 uint32_t reserved0[5];
1646 __le32 port_cfg_chg;
1647 uint32_t reserved1[11];
1651 __le32 els_proto_err;
1655 __le32 discarded_frames;
1656 __le32 dropped_frames;
1659 uint32_t reserved4[4];
1663 __le32 seq_frm_miss;
1669 __le64 fpm_recv_word_cnt;
1670 __le64 fpm_disc_word_cnt;
1671 __le64 fpm_xmit_word_cnt;
1672 uint32_t reserved6[70];
1676 * NVRAM Command values.
1678 #define NV_START_BIT BIT_2
1679 #define NV_WRITE_OP (BIT_26+BIT_24)
1680 #define NV_READ_OP (BIT_26+BIT_25)
1681 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1682 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1683 #define NV_DELAY_COUNT 10
1686 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1693 uint8_t nvram_version;
1697 * NVRAM RISC parameter block
1699 uint8_t parameter_block_version;
1703 * LSB BIT 0 = Enable Hard Loop Id
1704 * LSB BIT 1 = Enable Fairness
1705 * LSB BIT 2 = Enable Full-Duplex
1706 * LSB BIT 3 = Enable Fast Posting
1707 * LSB BIT 4 = Enable Target Mode
1708 * LSB BIT 5 = Disable Initiator Mode
1709 * LSB BIT 6 = Enable ADISC
1710 * LSB BIT 7 = Enable Target Inquiry Data
1712 * MSB BIT 0 = Enable PDBC Notify
1713 * MSB BIT 1 = Non Participating LIP
1714 * MSB BIT 2 = Descending Loop ID Search
1715 * MSB BIT 3 = Acquire Loop ID in LIPA
1716 * MSB BIT 4 = Stop PortQ on Full Status
1717 * MSB BIT 5 = Full Login after LIP
1718 * MSB BIT 6 = Node Name Option
1719 * MSB BIT 7 = Ext IFWCB enable bit
1721 uint8_t firmware_options[2];
1723 __le16 frame_payload_size;
1724 __le16 max_iocb_allocation;
1725 __le16 execution_throttle;
1726 uint8_t retry_count;
1727 uint8_t retry_delay; /* unused */
1728 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1729 uint16_t hard_address;
1730 uint8_t inquiry_data;
1731 uint8_t login_timeout;
1732 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1735 * LSB BIT 0 = Timer Operation mode bit 0
1736 * LSB BIT 1 = Timer Operation mode bit 1
1737 * LSB BIT 2 = Timer Operation mode bit 2
1738 * LSB BIT 3 = Timer Operation mode bit 3
1739 * LSB BIT 4 = Init Config Mode bit 0
1740 * LSB BIT 5 = Init Config Mode bit 1
1741 * LSB BIT 6 = Init Config Mode bit 2
1742 * LSB BIT 7 = Enable Non part on LIHA failure
1744 * MSB BIT 0 = Enable class 2
1745 * MSB BIT 1 = Enable ACK0
1748 * MSB BIT 4 = FC Tape Enable
1749 * MSB BIT 5 = Enable FC Confirm
1750 * MSB BIT 6 = Enable command queuing in target mode
1751 * MSB BIT 7 = No Logo On Link Down
1753 uint8_t add_firmware_options[2];
1755 uint8_t response_accumulation_timer;
1756 uint8_t interrupt_delay_timer;
1759 * LSB BIT 0 = Enable Read xfr_rdy
1760 * LSB BIT 1 = Soft ID only
1763 * LSB BIT 4 = FCP RSP Payload [0]
1764 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1765 * LSB BIT 6 = Enable Out-of-Order frame handling
1766 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1768 * MSB BIT 0 = Sbus enable - 2300
1772 * MSB BIT 4 = LED mode
1773 * MSB BIT 5 = enable 50 ohm termination
1774 * MSB BIT 6 = Data Rate (2300 only)
1775 * MSB BIT 7 = Data Rate (2300 only)
1777 uint8_t special_options[2];
1779 /* Reserved for expanded RISC parameter block */
1780 uint8_t reserved_2[22];
1783 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1784 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1785 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1786 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1787 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1788 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1789 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1790 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1792 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1793 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1794 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1795 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1796 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1797 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1798 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1799 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1801 * LSB BIT 0 = Output Swing 1G bit 0
1802 * LSB BIT 1 = Output Swing 1G bit 1
1803 * LSB BIT 2 = Output Swing 1G bit 2
1804 * LSB BIT 3 = Output Emphasis 1G bit 0
1805 * LSB BIT 4 = Output Emphasis 1G bit 1
1806 * LSB BIT 5 = Output Swing 2G bit 0
1807 * LSB BIT 6 = Output Swing 2G bit 1
1808 * LSB BIT 7 = Output Swing 2G bit 2
1810 * MSB BIT 0 = Output Emphasis 2G bit 0
1811 * MSB BIT 1 = Output Emphasis 2G bit 1
1812 * MSB BIT 2 = Output Enable
1819 uint8_t seriallink_options[4];
1822 * NVRAM host parameter block
1824 * LSB BIT 0 = Enable spinup delay
1825 * LSB BIT 1 = Disable BIOS
1826 * LSB BIT 2 = Enable Memory Map BIOS
1827 * LSB BIT 3 = Enable Selectable Boot
1828 * LSB BIT 4 = Disable RISC code load
1829 * LSB BIT 5 = Set cache line size 1
1830 * LSB BIT 6 = PCI Parity Disable
1831 * LSB BIT 7 = Enable extended logging
1833 * MSB BIT 0 = Enable 64bit addressing
1834 * MSB BIT 1 = Enable lip reset
1835 * MSB BIT 2 = Enable lip full login
1836 * MSB BIT 3 = Enable target reset
1837 * MSB BIT 4 = Enable database storage
1838 * MSB BIT 5 = Enable cache flush read
1839 * MSB BIT 6 = Enable database load
1840 * MSB BIT 7 = Enable alternate WWN
1844 uint8_t boot_node_name[WWN_SIZE];
1845 uint8_t boot_lun_number;
1846 uint8_t reset_delay;
1847 uint8_t port_down_retry_count;
1848 uint8_t boot_id_number;
1849 __le16 max_luns_per_target;
1850 uint8_t fcode_boot_port_name[WWN_SIZE];
1851 uint8_t alternate_port_name[WWN_SIZE];
1852 uint8_t alternate_node_name[WWN_SIZE];
1855 * BIT 0 = Selective Login
1856 * BIT 1 = Alt-Boot Enable
1858 * BIT 3 = Boot Order List
1860 * BIT 5 = Selective LUN
1864 uint8_t efi_parameters;
1866 uint8_t link_down_timeout;
1868 uint8_t adapter_id[16];
1870 uint8_t alt1_boot_node_name[WWN_SIZE];
1871 uint16_t alt1_boot_lun_number;
1872 uint8_t alt2_boot_node_name[WWN_SIZE];
1873 uint16_t alt2_boot_lun_number;
1874 uint8_t alt3_boot_node_name[WWN_SIZE];
1875 uint16_t alt3_boot_lun_number;
1876 uint8_t alt4_boot_node_name[WWN_SIZE];
1877 uint16_t alt4_boot_lun_number;
1878 uint8_t alt5_boot_node_name[WWN_SIZE];
1879 uint16_t alt5_boot_lun_number;
1880 uint8_t alt6_boot_node_name[WWN_SIZE];
1881 uint16_t alt6_boot_lun_number;
1882 uint8_t alt7_boot_node_name[WWN_SIZE];
1883 uint16_t alt7_boot_lun_number;
1885 uint8_t reserved_3[2];
1887 /* Offset 200-215 : Model Number */
1888 uint8_t model_number[16];
1890 /* OEM related items */
1891 uint8_t oem_specific[16];
1894 * NVRAM Adapter Features offset 232-239
1896 * LSB BIT 0 = External GBIC
1897 * LSB BIT 1 = Risc RAM parity
1898 * LSB BIT 2 = Buffer Plus Module
1899 * LSB BIT 3 = Multi Chip Adapter
1900 * LSB BIT 4 = Internal connector
1914 uint8_t adapter_features[2];
1916 uint8_t reserved_4[16];
1918 /* Subsystem vendor ID for ISP2200 */
1919 uint16_t subsystem_vendor_id_2200;
1921 /* Subsystem device ID for ISP2200 */
1922 uint16_t subsystem_device_id_2200;
1929 * ISP queue - response queue entry definition.
1932 uint8_t entry_type; /* Entry type. */
1933 uint8_t entry_count; /* Entry count. */
1934 uint8_t sys_define; /* System defined. */
1935 uint8_t entry_status; /* Entry Status. */
1936 uint32_t handle; /* System defined handle */
1939 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1943 * ISP queue - ATIO queue entry definition.
1946 uint8_t entry_type; /* Entry type. */
1947 uint8_t entry_count; /* Entry count. */
1948 __le16 attr_n_length;
1951 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1962 #define SET_TARGET_ID(ha, to, from) \
1964 if (HAS_EXTENDED_IDS(ha)) \
1965 to.extended = cpu_to_le16(from); \
1967 to.id.standard = (uint8_t)from; \
1971 * ISP queue - command entry structure definition.
1973 #define COMMAND_TYPE 0x11 /* Command entry */
1975 uint8_t entry_type; /* Entry type. */
1976 uint8_t entry_count; /* Entry count. */
1977 uint8_t sys_define; /* System defined. */
1978 uint8_t entry_status; /* Entry Status. */
1979 uint32_t handle; /* System handle. */
1980 target_id_t target; /* SCSI ID */
1981 __le16 lun; /* SCSI LUN */
1982 __le16 control_flags; /* Control flags. */
1983 #define CF_WRITE BIT_6
1984 #define CF_READ BIT_5
1985 #define CF_SIMPLE_TAG BIT_3
1986 #define CF_ORDERED_TAG BIT_2
1987 #define CF_HEAD_TAG BIT_1
1988 uint16_t reserved_1;
1989 __le16 timeout; /* Command timeout. */
1990 __le16 dseg_count; /* Data segment count. */
1991 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1992 __le32 byte_count; /* Total byte count. */
1994 struct dsd32 dsd32[3];
1995 struct dsd64 dsd64[2];
2000 * ISP queue - 64-Bit addressing, command entry structure definition.
2002 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
2004 uint8_t entry_type; /* Entry type. */
2005 uint8_t entry_count; /* Entry count. */
2006 uint8_t sys_define; /* System defined. */
2007 uint8_t entry_status; /* Entry Status. */
2008 uint32_t handle; /* System handle. */
2009 target_id_t target; /* SCSI ID */
2010 __le16 lun; /* SCSI LUN */
2011 __le16 control_flags; /* Control flags. */
2012 uint16_t reserved_1;
2013 __le16 timeout; /* Command timeout. */
2014 __le16 dseg_count; /* Data segment count. */
2015 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
2016 uint32_t byte_count; /* Total byte count. */
2017 struct dsd64 dsd[2];
2018 } cmd_a64_entry_t, request_t;
2021 * ISP queue - continuation entry structure definition.
2023 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
2025 uint8_t entry_type; /* Entry type. */
2026 uint8_t entry_count; /* Entry count. */
2027 uint8_t sys_define; /* System defined. */
2028 uint8_t entry_status; /* Entry Status. */
2030 struct dsd32 dsd[7];
2034 * ISP queue - 64-Bit addressing, continuation entry structure definition.
2036 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
2038 uint8_t entry_type; /* Entry type. */
2039 uint8_t entry_count; /* Entry count. */
2040 uint8_t sys_define; /* System defined. */
2041 uint8_t entry_status; /* Entry Status. */
2042 struct dsd64 dsd[5];
2045 #define PO_MODE_DIF_INSERT 0
2046 #define PO_MODE_DIF_REMOVE 1
2047 #define PO_MODE_DIF_PASS 2
2048 #define PO_MODE_DIF_REPLACE 3
2049 #define PO_MODE_DIF_TCP_CKSUM 6
2050 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
2051 #define PO_DISABLE_GUARD_CHECK BIT_4
2052 #define PO_DISABLE_INCR_REF_TAG BIT_5
2053 #define PO_DIS_HEADER_MODE BIT_7
2054 #define PO_ENABLE_DIF_BUNDLING BIT_8
2055 #define PO_DIS_FRAME_MODE BIT_9
2056 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
2057 #define PO_DIS_VALD_APP_REF_ESC BIT_11
2059 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
2060 #define PO_DIS_REF_TAG_REPL BIT_13
2061 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
2062 #define PO_DIS_REF_TAG_VALD BIT_15
2065 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
2067 struct crc_context {
2068 uint32_t handle; /* System handle. */
2071 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
2072 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
2073 __le16 guard_seed; /* Initial Guard Seed */
2074 __le16 prot_opts; /* Requested Data Protection Mode */
2075 __le16 blk_size; /* Data size in bytes */
2076 __le16 runt_blk_guard; /* Guard value for runt block (tape
2078 __le32 byte_count; /* Total byte count/ total data
2082 uint32_t reserved_1;
2083 uint16_t reserved_2;
2084 uint16_t reserved_3;
2085 uint32_t reserved_4;
2086 struct dsd64 data_dsd[1];
2087 uint32_t reserved_5[2];
2088 uint32_t reserved_6;
2091 __le32 dif_byte_count; /* Total DIF byte
2093 uint16_t reserved_1;
2094 __le16 dseg_count; /* Data segment count */
2095 uint32_t reserved_2;
2096 struct dsd64 data_dsd[1];
2097 struct dsd64 dif_dsd;
2101 struct fcp_cmnd fcp_cmnd;
2102 dma_addr_t crc_ctx_dma;
2103 /* List of DMA context transfers */
2104 struct list_head dsd_list;
2106 /* List of DIF Bundling context DMA address */
2107 struct list_head ldif_dsd_list;
2110 struct list_head ldif_dma_hndl_list;
2113 /* This structure should not exceed 512 bytes */
2116 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
2117 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
2120 * ISP queue - status entry structure definition.
2122 #define STATUS_TYPE 0x03 /* Status entry. */
2124 uint8_t entry_type; /* Entry type. */
2125 uint8_t entry_count; /* Entry count. */
2126 uint8_t sys_define; /* System defined. */
2127 uint8_t entry_status; /* Entry Status. */
2128 uint32_t handle; /* System handle. */
2129 __le16 scsi_status; /* SCSI status. */
2130 __le16 comp_status; /* Completion status. */
2131 __le16 state_flags; /* State flags. */
2132 __le16 status_flags; /* Status flags. */
2133 __le16 rsp_info_len; /* Response Info Length. */
2134 __le16 req_sense_length; /* Request sense data length. */
2135 __le32 residual_length; /* Residual transfer length. */
2136 uint8_t rsp_info[8]; /* FCP response information. */
2137 uint8_t req_sense_data[32]; /* Request sense data. */
2141 * Status entry entry status
2143 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
2144 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2145 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
2146 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
2147 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
2148 #define RF_BUSY BIT_1 /* Busy */
2149 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
2150 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
2151 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
2155 * Status entry SCSI status bit definitions.
2157 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
2158 #define SS_RESIDUAL_UNDER BIT_11
2159 #define SS_RESIDUAL_OVER BIT_10
2160 #define SS_SENSE_LEN_VALID BIT_9
2161 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
2162 #define SS_SCSI_STATUS_BYTE 0xff
2164 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
2165 #define SS_BUSY_CONDITION BIT_3
2166 #define SS_CONDITION_MET BIT_2
2167 #define SS_CHECK_CONDITION BIT_1
2170 * Status entry completion status
2172 #define CS_COMPLETE 0x0 /* No errors */
2173 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
2174 #define CS_DMA 0x2 /* A DMA direction error. */
2175 #define CS_TRANSPORT 0x3 /* Transport error. */
2176 #define CS_RESET 0x4 /* SCSI bus reset occurred */
2177 #define CS_ABORTED 0x5 /* System aborted command. */
2178 #define CS_TIMEOUT 0x6 /* Timeout error. */
2179 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
2180 #define CS_DIF_ERROR 0xC /* DIF error detected */
2182 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
2183 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
2184 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
2185 /* (selection timeout) */
2186 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
2187 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
2188 #define CS_PORT_BUSY 0x2B /* Port Busy */
2189 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
2190 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
2192 #define CS_REJECT_RECEIVED 0x4E /* Reject received */
2193 #define CS_EDIF_AUTH_ERROR 0x63 /* decrypt error */
2194 #define CS_EDIF_PAD_LEN_ERROR 0x65 /* pad > frame size, not 4byte align */
2195 #define CS_EDIF_INV_REQ 0x66 /* invalid request */
2196 #define CS_EDIF_SPI_ERROR 0x67 /* rx frame unable to locate sa */
2197 #define CS_EDIF_HDR_ERROR 0x69 /* data frame != expected len */
2198 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
2199 #define CS_UNKNOWN 0x81 /* Driver defined */
2200 #define CS_RETRY 0x82 /* Driver defined */
2201 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
2203 #define CS_BIDIR_RD_OVERRUN 0x700
2204 #define CS_BIDIR_RD_WR_OVERRUN 0x707
2205 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
2206 #define CS_BIDIR_RD_UNDERRUN 0x1500
2207 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
2208 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
2209 #define CS_BIDIR_DMA 0x200
2211 * Status entry status flags
2213 #define SF_ABTS_TERMINATED BIT_10
2214 #define SF_LOGOUT_SENT BIT_13
2217 * ISP queue - status continuation entry structure definition.
2219 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
2221 uint8_t entry_type; /* Entry type. */
2222 uint8_t entry_count; /* Entry count. */
2223 uint8_t sys_define; /* System defined. */
2224 uint8_t entry_status; /* Entry Status. */
2225 uint8_t data[60]; /* data */
2229 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
2230 * structure definition.
2232 #define STATUS_TYPE_21 0x21 /* Status entry. */
2234 uint8_t entry_type; /* Entry type. */
2235 uint8_t entry_count; /* Entry count. */
2236 uint8_t handle_count; /* Handle count. */
2237 uint8_t entry_status; /* Entry Status. */
2238 uint32_t handle[15]; /* System handles. */
2242 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
2243 * structure definition.
2245 #define STATUS_TYPE_22 0x22 /* Status entry. */
2247 uint8_t entry_type; /* Entry type. */
2248 uint8_t entry_count; /* Entry count. */
2249 uint8_t handle_count; /* Handle count. */
2250 uint8_t entry_status; /* Entry Status. */
2251 uint16_t handle[30]; /* System handles. */
2255 * ISP queue - marker entry structure definition.
2257 #define MARKER_TYPE 0x04 /* Marker entry. */
2259 uint8_t entry_type; /* Entry type. */
2260 uint8_t entry_count; /* Entry count. */
2261 uint8_t handle_count; /* Handle count. */
2262 uint8_t entry_status; /* Entry Status. */
2263 uint32_t sys_define_2; /* System defined. */
2264 target_id_t target; /* SCSI ID */
2265 uint8_t modifier; /* Modifier (7-0). */
2266 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
2267 #define MK_SYNC_ID 1 /* Synchronize ID */
2268 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
2269 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
2270 /* clear port changed, */
2271 /* use sequence number. */
2273 __le16 sequence_number; /* Sequence number of event */
2274 __le16 lun; /* SCSI LUN */
2275 uint8_t reserved_2[48];
2279 * ISP queue - Management Server entry structure definition.
2281 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
2283 uint8_t entry_type; /* Entry type. */
2284 uint8_t entry_count; /* Entry count. */
2285 uint8_t handle_count; /* Handle count. */
2286 uint8_t entry_status; /* Entry Status. */
2287 uint32_t handle1; /* System handle. */
2288 target_id_t loop_id;
2290 __le16 control_flags; /* Control flags. */
2293 __le16 cmd_dsd_count;
2294 __le16 total_dsd_count;
2300 __le32 rsp_bytecount;
2301 __le32 req_bytecount;
2302 struct dsd64 req_dsd;
2303 struct dsd64 rsp_dsd;
2306 #define SCM_EDC_ACC_RECEIVED BIT_6
2307 #define SCM_RDF_ACC_RECEIVED BIT_7
2310 * ISP queue - Mailbox Command entry structure definition.
2312 #define MBX_IOCB_TYPE 0x39
2315 uint8_t entry_count;
2316 uint8_t sys_define1;
2317 /* Use sys_define1 for source type */
2318 #define SOURCE_SCSI 0x00
2319 #define SOURCE_IP 0x01
2320 #define SOURCE_VI 0x02
2321 #define SOURCE_SCTP 0x03
2322 #define SOURCE_MP 0x04
2323 #define SOURCE_MPIOCTL 0x05
2324 #define SOURCE_ASYNC_IOCB 0x07
2326 uint8_t entry_status;
2329 target_id_t loop_id;
2333 __le16 status_flags;
2335 uint32_t sys_define2[2];
2345 uint32_t reserved_2[2];
2346 uint8_t node_name[WWN_SIZE];
2347 uint8_t port_name[WWN_SIZE];
2350 #ifndef IMMED_NOTIFY_TYPE
2351 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2353 * ISP queue - immediate notify entry structure definition.
2354 * This is sent by the ISP to the Target driver.
2355 * This IOCB would have report of events sent by the
2356 * initiator, that needs to be handled by the target
2357 * driver immediately.
2359 struct imm_ntfy_from_isp {
2360 uint8_t entry_type; /* Entry type. */
2361 uint8_t entry_count; /* Entry count. */
2362 uint8_t sys_define; /* System defined. */
2363 uint8_t entry_status; /* Entry Status. */
2366 __le32 sys_define_2; /* System defined. */
2371 __le16 status_modifier;
2376 __le32 srr_rel_offs;
2378 #define SRR_IU_DATA_IN 0x1
2379 #define SRR_IU_DATA_OUT 0x5
2380 #define SRR_IU_STATUS 0x7
2382 uint8_t reserved_2[28];
2386 __le16 nport_handle;
2387 uint16_t reserved_2;
2389 #define NOTIFY24XX_FLAGS_FCSP BIT_5
2390 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2391 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2394 uint8_t status_subcode;
2396 __le32 exchange_address;
2397 __le32 srr_rel_offs;
2402 uint8_t node_name[8];
2403 } plogi; /* PLOGI/ADISC/PDISC */
2405 /* PRLI word 3 bit 0-15 */
2412 __le16 nport_handle;
2416 uint8_t port_name[8];
2419 uint32_t reserved_5;
2424 uint16_t reserved_7;
2430 * ISP request and response queue entry sizes
2432 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2433 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2438 * Switch info gathering structure.
2442 uint8_t node_name[WWN_SIZE];
2443 uint8_t port_name[WWN_SIZE];
2444 uint8_t fabric_port_name[WWN_SIZE];
2447 uint8_t fc4_features;
2451 #define FC4_TYPE_FCP_SCSI 0x08
2452 #define FC4_TYPE_NVME 0x28
2453 #define FC4_TYPE_OTHER 0x0
2454 #define FC4_TYPE_UNKNOWN 0xff
2456 /* mailbox command 4G & above */
2457 struct mbx_24xx_entry {
2459 uint8_t entry_count;
2460 uint8_t sys_define1;
2461 uint8_t entry_status;
2466 #define IOCB_SIZE 64
2469 * Fibre channel port type.
2473 FCT_BROADCAST = 0x01,
2474 FCT_INITIATOR = 0x02,
2476 FCT_NVME_INITIATOR = 0x10,
2477 FCT_NVME_TARGET = 0x20,
2478 FCT_NVME_DISCOVERY = 0x40,
2482 enum qla_sess_deletion {
2483 QLA_SESS_DELETION_NONE = 0,
2484 QLA_SESS_DELETION_IN_PROGRESS,
2488 enum qlt_plogi_link_t {
2489 QLT_PLOGI_LINK_SAME_WWN,
2490 QLT_PLOGI_LINK_CONFLICT,
2494 struct qlt_plogi_ack_t {
2495 struct list_head list;
2496 struct imm_ntfy_from_isp iocb;
2502 struct ct_sns_desc {
2503 struct ct_sns_pkt *ct_sns;
2504 dma_addr_t ct_sns_dma;
2507 enum discovery_state {
2517 DSC_LOGIN_AUTH_PEND,
2520 enum login_state { /* FW control Target side */
2521 DSC_LS_LLIOCB_SENT = 2,
2526 DSC_LS_PORT_UNAVAIL,
2527 DSC_LS_PRLO_PEND = 9,
2531 enum rscn_addr_format {
2539 * Fibre channel port structure.
2541 typedef struct fc_port {
2542 struct list_head list;
2543 struct scsi_qla_host *vha;
2544 struct list_head tmf_pending;
2546 unsigned int conf_compl_supported:1;
2547 unsigned int deleted:2;
2548 unsigned int free_pending:1;
2549 unsigned int local:1;
2550 unsigned int logout_on_delete:1;
2551 unsigned int logo_ack_needed:1;
2552 unsigned int keep_nport_handle:1;
2553 unsigned int send_els_logo:1;
2554 unsigned int login_pause:1;
2555 unsigned int login_succ:1;
2556 unsigned int query:1;
2557 unsigned int id_changed:1;
2558 unsigned int scan_needed:1;
2559 unsigned int n2n_flag:1;
2560 unsigned int explicit_logout:1;
2561 unsigned int prli_pend_timer:1;
2562 unsigned int do_prli_nvme:1;
2566 #define MAX_ACTIVE_TMF 8
2568 uint8_t node_name[WWN_SIZE];
2569 uint8_t port_name[WWN_SIZE];
2572 uint16_t old_loop_id;
2574 struct completion nvme_del_done;
2575 uint32_t nvme_prli_service_param;
2576 #define NVME_PRLI_SP_PI_CTRL BIT_9
2577 #define NVME_PRLI_SP_SLER BIT_8
2578 #define NVME_PRLI_SP_CONF BIT_7
2579 #define NVME_PRLI_SP_INITIATOR BIT_5
2580 #define NVME_PRLI_SP_TARGET BIT_4
2581 #define NVME_PRLI_SP_DISCOVERY BIT_3
2582 #define NVME_PRLI_SP_FIRST_BURST BIT_0
2584 uint32_t nvme_first_burst_size;
2585 #define NVME_FLAG_REGISTERED 4
2586 #define NVME_FLAG_DELETING 2
2587 #define NVME_FLAG_RESETTING 1
2589 struct fc_port *conflict;
2590 unsigned char logout_completed;
2593 struct se_session *se_sess;
2594 struct list_head sess_cmd_list;
2595 spinlock_t sess_cmd_lock;
2596 struct kref sess_kref;
2597 struct qla_tgt *tgt;
2598 unsigned long expires;
2599 struct list_head del_list_entry;
2600 struct work_struct free_work;
2601 struct work_struct reg_work;
2602 uint64_t jiffies_at_registration;
2603 unsigned long prli_expired;
2604 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2607 uint16_t old_tgt_id;
2608 uint16_t sec_since_registration;
2612 uint8_t fabric_port_name[WWN_SIZE];
2615 fc_port_type_t port_type;
2622 struct fc_rport *rport;
2623 u32 supported_classes;
2626 uint8_t fc4_features;
2629 unsigned long last_queue_full;
2630 unsigned long last_ramp_up;
2634 struct nvme_fc_remote_port *nvme_remote_port;
2636 unsigned long retry_delay_timestamp;
2637 struct qla_tgt_sess *tgt_session;
2638 struct ct_sns_desc ct_desc;
2639 enum discovery_state disc_state;
2640 atomic_t shadow_disc_state;
2641 enum discovery_state next_disc_state;
2642 enum login_state fw_login_state;
2643 unsigned long dm_login_expire;
2644 unsigned long plogi_nack_done_deadline;
2646 u32 login_gen, last_login_gen;
2647 u32 rscn_gen, last_rscn_gen;
2649 struct list_head gnl_entry;
2650 struct work_struct del_work;
2652 u8 current_login_state;
2653 u8 last_login_state;
2654 u16 n2n_link_reset_cnt;
2657 struct dentry *dfs_rport_dir;
2659 u64 tgt_short_link_down_cnt;
2660 u64 tgt_link_down_time;
2663 * EDIF parameters for encryption.
2666 uint32_t enable:1; /* device is edif enabled/req'd */
2667 uint32_t app_stop:2;
2668 uint32_t aes_gmac:1;
2669 uint32_t app_sess_online:1;
2670 uint32_t tx_sa_set:1;
2671 uint32_t rx_sa_set:1;
2672 uint32_t tx_sa_pending:1;
2673 uint32_t rx_sa_pending:1;
2674 uint32_t tx_rekey_cnt;
2675 uint32_t rx_rekey_cnt;
2678 uint8_t sess_down_acked;
2682 struct list_head edif_indx_list;
2683 spinlock_t indx_list_lock;
2685 struct list_head tx_sa_list;
2686 struct list_head rx_sa_list;
2687 spinlock_t sa_list_lock;
2692 FC4_PRIORITY_NVME = 1,
2693 FC4_PRIORITY_FCP = 2,
2696 #define QLA_FCPORT_SCAN 1
2697 #define QLA_FCPORT_FOUND 2
2704 u8 port_name[WWN_SIZE];
2711 * Fibre channel port/lun states.
2721 extern const char *const port_state_str[5];
2723 static const char *const port_dstate_str[] = {
2724 [DSC_DELETED] = "DELETED",
2726 [DSC_LOGIN_PEND] = "LOGIN_PEND",
2727 [DSC_LOGIN_FAILED] = "LOGIN_FAILED",
2728 [DSC_GPDB] = "GPDB",
2729 [DSC_UPD_FCPORT] = "UPD_FCPORT",
2730 [DSC_LOGIN_COMPLETE] = "LOGIN_COMPLETE",
2731 [DSC_ADISC] = "ADISC",
2732 [DSC_DELETE_PEND] = "DELETE_PEND",
2733 [DSC_LOGIN_AUTH_PEND] = "LOGIN_AUTH_PEND",
2739 #define FCF_FABRIC_DEVICE BIT_0
2740 #define FCF_LOGIN_NEEDED BIT_1
2741 #define FCF_FCP2_DEVICE BIT_2
2742 #define FCF_ASYNC_SENT BIT_3
2743 #define FCF_CONF_COMP_SUPPORTED BIT_4
2744 #define FCF_ASYNC_ACTIVE BIT_5
2745 #define FCF_FCSP_DEVICE BIT_6
2746 #define FCF_EDIF_DELETE BIT_7
2748 /* No loop ID flag. */
2749 #define FC_NO_LOOP_ID 0x1000
2754 * NOTE: All structures are big-endian in form.
2757 #define CT_REJECT_RESPONSE 0x8001
2758 #define CT_ACCEPT_RESPONSE 0x8002
2759 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2760 #define CT_REASON_CANNOT_PERFORM 0x09
2761 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2762 #define CT_EXPL_ALREADY_REGISTERED 0x10
2763 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2764 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2765 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2766 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2767 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2768 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2769 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2770 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2771 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2772 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2773 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2775 #define NS_N_PORT_TYPE 0x01
2776 #define NS_NL_PORT_TYPE 0x02
2777 #define NS_NX_PORT_TYPE 0x7F
2779 #define GA_NXT_CMD 0x100
2780 #define GA_NXT_REQ_SIZE (16 + 4)
2781 #define GA_NXT_RSP_SIZE (16 + 620)
2783 #define GPN_FT_CMD 0x172
2784 #define GPN_FT_REQ_SIZE (16 + 4)
2785 #define GNN_FT_CMD 0x173
2786 #define GNN_FT_REQ_SIZE (16 + 4)
2788 #define GID_PT_CMD 0x1A1
2789 #define GID_PT_REQ_SIZE (16 + 4)
2791 #define GPN_ID_CMD 0x112
2792 #define GPN_ID_REQ_SIZE (16 + 4)
2793 #define GPN_ID_RSP_SIZE (16 + 8)
2795 #define GNN_ID_CMD 0x113
2796 #define GNN_ID_REQ_SIZE (16 + 4)
2797 #define GNN_ID_RSP_SIZE (16 + 8)
2799 #define GFT_ID_CMD 0x117
2800 #define GFT_ID_REQ_SIZE (16 + 4)
2801 #define GFT_ID_RSP_SIZE (16 + 32)
2803 #define GID_PN_CMD 0x121
2804 #define GID_PN_REQ_SIZE (16 + 8)
2805 #define GID_PN_RSP_SIZE (16 + 4)
2807 #define RFT_ID_CMD 0x217
2808 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2809 #define RFT_ID_RSP_SIZE 16
2811 #define RFF_ID_CMD 0x21F
2812 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2813 #define RFF_ID_RSP_SIZE 16
2815 #define RNN_ID_CMD 0x213
2816 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2817 #define RNN_ID_RSP_SIZE 16
2819 #define RSNN_NN_CMD 0x239
2820 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2821 #define RSNN_NN_RSP_SIZE 16
2823 #define GFPN_ID_CMD 0x11C
2824 #define GFPN_ID_REQ_SIZE (16 + 4)
2825 #define GFPN_ID_RSP_SIZE (16 + 8)
2827 #define GPSC_CMD 0x127
2828 #define GPSC_REQ_SIZE (16 + 8)
2829 #define GPSC_RSP_SIZE (16 + 2 + 2)
2831 #define GFF_ID_CMD 0x011F
2832 #define GFF_ID_REQ_SIZE (16 + 4)
2833 #define GFF_ID_RSP_SIZE (16 + 128)
2836 * FDMI HBA attribute types.
2838 #define FDMI1_HBA_ATTR_COUNT 10
2839 #define FDMI2_HBA_ATTR_COUNT 17
2841 #define FDMI_HBA_NODE_NAME 0x1
2842 #define FDMI_HBA_MANUFACTURER 0x2
2843 #define FDMI_HBA_SERIAL_NUMBER 0x3
2844 #define FDMI_HBA_MODEL 0x4
2845 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2846 #define FDMI_HBA_HARDWARE_VERSION 0x6
2847 #define FDMI_HBA_DRIVER_VERSION 0x7
2848 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2849 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2850 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2851 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2853 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2854 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
2855 #define FDMI_HBA_NUM_PORTS 0xe
2856 #define FDMI_HBA_FABRIC_NAME 0xf
2857 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2858 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
2860 struct ct_fdmi_hba_attr {
2864 uint8_t node_name[WWN_SIZE];
2865 uint8_t manufacturer[64];
2866 uint8_t serial_num[32];
2867 uint8_t model[16+1];
2868 uint8_t model_desc[80];
2869 uint8_t hw_version[32];
2870 uint8_t driver_version[32];
2871 uint8_t orom_version[16];
2872 uint8_t fw_version[32];
2873 uint8_t os_version[128];
2876 uint8_t sym_name[256];
2877 __be32 vendor_specific_info;
2879 uint8_t fabric_name[WWN_SIZE];
2880 uint8_t bios_name[32];
2881 uint8_t vendor_identifier[8];
2885 struct ct_fdmi1_hba_attributes {
2887 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
2890 struct ct_fdmi2_hba_attributes {
2892 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
2896 * FDMI Port attribute types.
2898 #define FDMI1_PORT_ATTR_COUNT 6
2899 #define FDMI2_PORT_ATTR_COUNT 16
2900 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
2902 #define FDMI_PORT_FC4_TYPES 0x1
2903 #define FDMI_PORT_SUPPORT_SPEED 0x2
2904 #define FDMI_PORT_CURRENT_SPEED 0x3
2905 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2906 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2907 #define FDMI_PORT_HOST_NAME 0x6
2909 #define FDMI_PORT_NODE_NAME 0x7
2910 #define FDMI_PORT_NAME 0x8
2911 #define FDMI_PORT_SYM_NAME 0x9
2912 #define FDMI_PORT_TYPE 0xa
2913 #define FDMI_PORT_SUPP_COS 0xb
2914 #define FDMI_PORT_FABRIC_NAME 0xc
2915 #define FDMI_PORT_FC4_TYPE 0xd
2916 #define FDMI_PORT_STATE 0x101
2917 #define FDMI_PORT_COUNT 0x102
2918 #define FDMI_PORT_IDENTIFIER 0x103
2920 #define FDMI_SMARTSAN_SERVICE 0xF100
2921 #define FDMI_SMARTSAN_GUID 0xF101
2922 #define FDMI_SMARTSAN_VERSION 0xF102
2923 #define FDMI_SMARTSAN_PROD_NAME 0xF103
2924 #define FDMI_SMARTSAN_PORT_INFO 0xF104
2925 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
2926 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
2928 #define FDMI_PORT_SPEED_1GB 0x1
2929 #define FDMI_PORT_SPEED_2GB 0x2
2930 #define FDMI_PORT_SPEED_10GB 0x4
2931 #define FDMI_PORT_SPEED_4GB 0x8
2932 #define FDMI_PORT_SPEED_8GB 0x10
2933 #define FDMI_PORT_SPEED_16GB 0x20
2934 #define FDMI_PORT_SPEED_32GB 0x40
2935 #define FDMI_PORT_SPEED_20GB 0x80
2936 #define FDMI_PORT_SPEED_40GB 0x100
2937 #define FDMI_PORT_SPEED_128GB 0x200
2938 #define FDMI_PORT_SPEED_64GB 0x400
2939 #define FDMI_PORT_SPEED_256GB 0x800
2940 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2942 #define FC_CLASS_2 0x04
2943 #define FC_CLASS_3 0x08
2944 #define FC_CLASS_2_3 0x0C
2946 struct ct_fdmi_port_attr {
2950 uint8_t fc4_types[32];
2953 __be32 max_frame_size;
2954 uint8_t os_dev_name[32];
2955 uint8_t host_name[256];
2957 uint8_t node_name[WWN_SIZE];
2958 uint8_t port_name[WWN_SIZE];
2959 uint8_t port_sym_name[128];
2961 __be32 port_supported_cos;
2962 uint8_t fabric_name[WWN_SIZE];
2963 uint8_t port_fc4_type[32];
2968 uint8_t smartsan_service[24];
2969 uint8_t smartsan_guid[16];
2970 uint8_t smartsan_version[24];
2971 uint8_t smartsan_prod_name[16];
2972 __be32 smartsan_port_info;
2973 __be32 smartsan_qos_support;
2974 __be32 smartsan_security_support;
2978 struct ct_fdmi1_port_attributes {
2980 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
2983 struct ct_fdmi2_port_attributes {
2985 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
2988 #define FDMI_ATTR_TYPELEN(obj) \
2989 (sizeof((obj)->type) + sizeof((obj)->len))
2991 #define FDMI_ATTR_ALIGNMENT(len) \
2994 /* FDMI register call options */
2995 #define CALLOPT_FDMI1 0
2996 #define CALLOPT_FDMI2 1
2997 #define CALLOPT_FDMI2_SMARTSAN 2
2999 /* FDMI definitions. */
3000 #define GRHL_CMD 0x100
3001 #define GHAT_CMD 0x101
3002 #define GRPL_CMD 0x102
3003 #define GPAT_CMD 0x110
3005 #define RHBA_CMD 0x200
3006 #define RHBA_RSP_SIZE 16
3008 #define RHAT_CMD 0x201
3010 #define RPRT_CMD 0x210
3011 #define RPRT_RSP_SIZE 24
3013 #define RPA_CMD 0x211
3014 #define RPA_RSP_SIZE 16
3015 #define SMARTSAN_RPA_RSP_SIZE 24
3017 #define DHBA_CMD 0x300
3018 #define DHBA_REQ_SIZE (16 + 8)
3019 #define DHBA_RSP_SIZE 16
3021 #define DHAT_CMD 0x301
3022 #define DPRT_CMD 0x310
3023 #define DPA_CMD 0x311
3025 /* CT command header -- request/response common fields */
3035 /* CT command request */
3037 struct ct_cmd_hdr header;
3039 __be16 max_rsp_size;
3040 uint8_t fragment_id;
3041 uint8_t reserved[3];
3044 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
3067 uint8_t fc4_types[32];
3074 uint8_t fc4_feature;
3081 uint8_t node_name[8];
3085 uint8_t node_name[8];
3087 uint8_t sym_node_name[255];
3091 uint8_t hba_identifier[8];
3095 uint8_t hba_identifier[8];
3097 uint8_t port_name[8];
3098 struct ct_fdmi2_hba_attributes attrs;
3102 uint8_t hba_identifier[8];
3103 struct ct_fdmi1_hba_attributes attrs;
3107 uint8_t port_name[8];
3108 struct ct_fdmi2_port_attributes attrs;
3112 uint8_t hba_identifier[8];
3113 uint8_t port_name[8];
3114 struct ct_fdmi2_port_attributes attrs;
3118 uint8_t port_name[8];
3122 uint8_t port_name[8];
3126 uint8_t port_name[8];
3130 uint8_t port_name[8];
3134 uint8_t port_name[8];
3143 uint8_t port_name[8];
3148 /* CT command response header */
3150 struct ct_cmd_hdr header;
3153 uint8_t fragment_id;
3154 uint8_t reason_code;
3155 uint8_t explanation_code;
3156 uint8_t vendor_unique;
3159 struct ct_sns_gid_pt_data {
3160 uint8_t control_byte;
3164 /* It's the same for both GPN_FT and GNN_FT */
3165 struct ct_sns_gpnft_rsp {
3167 struct ct_cmd_hdr header;
3170 uint8_t fragment_id;
3171 uint8_t reason_code;
3172 uint8_t explanation_code;
3173 uint8_t vendor_unique;
3175 /* Assume the largest number of targets for the union */
3176 DECLARE_FLEX_ARRAY(struct ct_sns_gpn_ft_data {
3184 /* CT command response */
3186 struct ct_rsp_hdr header;
3192 uint8_t port_name[8];
3193 uint8_t sym_port_name_len;
3194 uint8_t sym_port_name[255];
3195 uint8_t node_name[8];
3196 uint8_t sym_node_name_len;
3197 uint8_t sym_node_name[255];
3198 uint8_t init_proc_assoc[8];
3199 uint8_t node_ip_addr[16];
3200 uint8_t class_of_service[4];
3201 uint8_t fc4_types[32];
3202 uint8_t ip_address[16];
3203 uint8_t fabric_port_name[8];
3205 uint8_t hard_address[3];
3209 /* Assume the largest number of targets for the union */
3210 struct ct_sns_gid_pt_data
3211 entries[MAX_FIBRE_DEVICES_MAX];
3215 uint8_t port_name[8];
3219 uint8_t node_name[8];
3223 uint8_t fc4_types[32];
3227 uint32_t entry_count;
3228 uint8_t port_name[8];
3229 struct ct_fdmi1_hba_attributes attrs;
3233 uint8_t port_name[8];
3241 #define GFF_FCP_SCSI_OFFSET 7
3242 #define GFF_NVME_OFFSET 23 /* type = 28h */
3244 uint8_t fc4_features[128];
3245 #define FC4_FF_TARGET BIT_0
3246 #define FC4_FF_INITIATOR BIT_1
3257 struct ct_sns_req req;
3258 struct ct_sns_rsp rsp;
3262 struct ct_sns_gpnft_pkt {
3264 struct ct_sns_req req;
3265 struct ct_sns_gpnft_rsp rsp;
3270 SF_SCANNING = BIT_0,
3275 FS_FC4TYPE_FCP = BIT_0,
3276 FS_FC4TYPE_NVME = BIT_1,
3277 FS_FCP_IS_N2N = BIT_7,
3280 struct fab_scan_rp {
3282 enum fc4type_t fc4type;
3288 struct fab_scan_rp *l;
3291 #define MAX_SCAN_RETRIES 5
3292 enum scan_flags_t scan_flags;
3293 struct delayed_work scan_work;
3297 * SNS command structures -- for 2200 compatibility.
3299 #define RFT_ID_SNS_SCMD_LEN 22
3300 #define RFT_ID_SNS_CMD_SIZE 60
3301 #define RFT_ID_SNS_DATA_SIZE 16
3303 #define RNN_ID_SNS_SCMD_LEN 10
3304 #define RNN_ID_SNS_CMD_SIZE 36
3305 #define RNN_ID_SNS_DATA_SIZE 16
3307 #define GA_NXT_SNS_SCMD_LEN 6
3308 #define GA_NXT_SNS_CMD_SIZE 28
3309 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
3311 #define GID_PT_SNS_SCMD_LEN 6
3312 #define GID_PT_SNS_CMD_SIZE 28
3314 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
3317 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3319 #define GPN_ID_SNS_SCMD_LEN 6
3320 #define GPN_ID_SNS_CMD_SIZE 28
3321 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
3323 #define GNN_ID_SNS_SCMD_LEN 6
3324 #define GNN_ID_SNS_CMD_SIZE 28
3325 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
3327 struct sns_cmd_pkt {
3330 __le16 buffer_length;
3332 __le64 buffer_address __packed;
3333 __le16 subcommand_length;
3337 uint32_t reserved_3;
3341 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3342 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3343 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3344 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3345 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3346 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3353 const struct firmware *fw;
3356 /* Return data from MBC_GET_ID_LIST call. */
3357 struct gid_list_info {
3361 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
3362 __le16 loop_id; /* ISP23XX -- 6 bytes. */
3363 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
3367 typedef struct vport_info {
3368 uint8_t port_name[WWN_SIZE];
3369 uint8_t node_name[WWN_SIZE];
3372 unsigned long host_no;
3377 typedef struct vport_params {
3378 uint8_t port_name[WWN_SIZE];
3379 uint8_t node_name[WWN_SIZE];
3381 #define VP_OPTS_RETRY_ENABLE BIT_0
3382 #define VP_OPTS_VP_DISABLE BIT_1
3385 /* NPIV - return codes of VP create and modify */
3386 #define VP_RET_CODE_OK 0
3387 #define VP_RET_CODE_FATAL 1
3388 #define VP_RET_CODE_WRONG_ID 2
3389 #define VP_RET_CODE_WWPN 3
3390 #define VP_RET_CODE_RESOURCES 4
3391 #define VP_RET_CODE_NO_MEM 5
3392 #define VP_RET_CODE_NOT_FOUND 6
3399 struct isp_operations {
3401 int (*pci_config) (struct scsi_qla_host *);
3402 int (*reset_chip)(struct scsi_qla_host *);
3403 int (*chip_diag) (struct scsi_qla_host *);
3404 void (*config_rings) (struct scsi_qla_host *);
3405 int (*reset_adapter)(struct scsi_qla_host *);
3406 int (*nvram_config) (struct scsi_qla_host *);
3407 void (*update_fw_options) (struct scsi_qla_host *);
3408 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3410 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
3411 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3413 irq_handler_t intr_handler;
3414 void (*enable_intrs) (struct qla_hw_data *);
3415 void (*disable_intrs) (struct qla_hw_data *);
3417 int (*abort_command) (srb_t *);
3418 int (*target_reset) (struct fc_port *, uint64_t, int);
3419 int (*lun_reset) (struct fc_port *, uint64_t, int);
3420 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3421 uint8_t, uint8_t, uint16_t *, uint8_t);
3422 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3425 uint16_t (*calc_req_entries) (uint16_t);
3426 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3427 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3428 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3431 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3432 uint32_t, uint32_t);
3433 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3436 void (*fw_dump)(struct scsi_qla_host *vha);
3437 void (*mpi_fw_dump)(struct scsi_qla_host *, int);
3439 /* Context: task, might sleep */
3440 int (*beacon_on) (struct scsi_qla_host *);
3441 int (*beacon_off) (struct scsi_qla_host *);
3443 void (*beacon_blink) (struct scsi_qla_host *);
3445 void *(*read_optrom)(struct scsi_qla_host *, void *,
3446 uint32_t, uint32_t);
3447 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3450 int (*get_flash_version) (struct scsi_qla_host *, void *);
3451 int (*start_scsi) (srb_t *);
3452 int (*start_scsi_mq) (srb_t *);
3454 /* Context: task, might sleep */
3455 int (*abort_isp) (struct scsi_qla_host *);
3457 int (*iospace_config)(struct qla_hw_data *);
3458 int (*initialize_adapter)(struct scsi_qla_host *);
3461 /* MSI-X Support *************************************************************/
3463 #define QLA_MSIX_CHIP_REV_24XX 3
3464 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3465 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3467 #define QLA_BASE_VECTORS 2 /* default + RSP */
3468 #define QLA_MSIX_RSP_Q 0x01
3469 #define QLA_ATIO_VECTOR 0x02
3470 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3471 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
3473 #define QLA_MIDX_DEFAULT 0
3474 #define QLA_MIDX_RSP_Q 1
3475 #define QLA_PCI_MSIX_CONTROL 0xa2
3476 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3478 struct scsi_qla_host;
3481 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3483 struct qla_msix_entry {
3487 uint32_t vector_base0;
3494 #define WATCH_INTERVAL 1 /* number of seconds */
3497 enum qla_work_type {
3500 QLA_EVT_ASYNC_LOGIN,
3501 QLA_EVT_ASYNC_LOGOUT,
3502 QLA_EVT_ASYNC_ADISC,
3514 QLA_EVT_ASYNC_PRLO_DONE,
3526 struct qla_work_evt {
3527 struct list_head list;
3528 enum qla_work_type type;
3530 #define QLA_EVT_FLAG_FREE 0x1
3534 enum fc_host_event_code code;
3538 #define QLA_IDC_ACK_REGS 7
3539 uint16_t mb[QLA_IDC_ACK_REGS];
3542 struct fc_port *fcport;
3543 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3548 #define QLA_UEVENT_CODE_FW_DUMP 0
3565 struct { /*Get PDB, Get Speed, update fcport, gnl */
3579 struct edif_sa_ctl *sa_ctl;
3581 uint16_t nport_handle;
3586 struct qla_chip_state_84xx {
3587 struct list_head list;
3591 spinlock_t access_lock;
3592 struct mutex fw_update_mutex;
3594 uint32_t op_fw_version;
3595 uint32_t op_fw_size;
3596 uint32_t op_fw_seq_size;
3597 uint32_t diag_fw_version;
3598 uint32_t gold_fw_version;
3601 struct qla_dif_statistics {
3602 uint64_t dif_input_bytes;
3603 uint64_t dif_output_bytes;
3604 uint64_t dif_input_requests;
3605 uint64_t dif_output_requests;
3606 uint32_t dif_guard_err;
3607 uint32_t dif_ref_tag_err;
3608 uint32_t dif_app_tag_err;
3611 struct qla_statistics {
3612 uint32_t total_isp_aborts;
3613 uint64_t input_bytes;
3614 uint64_t output_bytes;
3615 uint64_t input_requests;
3616 uint64_t output_requests;
3617 uint32_t control_requests;
3619 uint64_t jiffies_at_last_reset;
3620 uint32_t stat_max_pend_cmds;
3621 uint32_t stat_max_qfull_cmds_alloc;
3622 uint32_t stat_max_qfull_cmds_dropped;
3624 struct qla_dif_statistics qla_dif_stats;
3627 struct bidi_statistics {
3628 unsigned long long io_count;
3629 unsigned long long transfer_bytes;
3632 struct qla_tc_param {
3633 struct scsi_qla_host *vha;
3636 struct scatterlist *sg;
3637 struct scatterlist *prot_sg;
3638 struct crc_context *ctx;
3639 uint8_t *ctx_dsd_alloced;
3642 /* Multi queue support */
3643 #define MBC_INITIALIZE_MULTIQ 0x1f
3644 #define QLA_QUE_PAGE 0X1000
3645 #define QLA_MQ_SIZE 32
3646 #define QLA_MAX_QUEUES 256
3647 #define ISP_QUE_REG(ha, id) \
3648 ((ha->mqenable || IS_QLA83XX(ha) || \
3649 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3650 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3651 ((void __iomem *)ha->iobase))
3652 #define QLA_REQ_QUE_ID(tag) \
3653 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3654 #define QLA_DEFAULT_QUE_QOS 5
3655 #define QLA_PRECONFIG_VPORTS 32
3656 #define QLA_MAX_VPORTS_QLA24XX 128
3657 #define QLA_MAX_VPORTS_QLA25XX 256
3659 struct qla_tgt_counters {
3660 uint64_t qla_core_sbt_cmd;
3661 uint64_t core_qla_que_buf;
3662 uint64_t qla_core_ret_ctio;
3663 uint64_t core_qla_snd_status;
3664 uint64_t qla_core_ret_sta_ctio;
3665 uint64_t core_qla_free_cmd;
3666 uint64_t num_q_full_sent;
3667 uint64_t num_alloc_iocb_failed;
3668 uint64_t num_term_xchg_sent;
3671 struct qla_counters {
3672 uint64_t input_bytes;
3673 uint64_t input_requests;
3674 uint64_t output_bytes;
3675 uint64_t output_requests;
3681 /* Response queue data structure */
3685 response_t *ring_ptr;
3686 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */
3687 __le32 __iomem *rsp_q_out;
3688 uint16_t ring_index;
3690 uint16_t *in_ptr; /* queue shadow in index */
3696 struct qla_hw_data *hw;
3697 struct qla_msix_entry *msix;
3698 struct req_que *req;
3699 srb_t *status_srb; /* status continuation entry */
3700 struct qla_qpair *qpair;
3702 dma_addr_t dma_fx00;
3703 response_t *ring_fx00;
3704 uint16_t length_fx00;
3705 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3708 /* Request queue data structure */
3712 request_t *ring_ptr;
3713 __le32 __iomem *req_q_in; /* FWI2-capable only. */
3714 __le32 __iomem *req_q_out;
3715 uint16_t ring_index;
3717 uint16_t *out_ptr; /* queue shadow out index */
3725 struct rsp_que *rsp;
3726 srb_t **outstanding_cmds;
3727 uint32_t current_outstanding_cmd;
3728 uint16_t num_outstanding_cmds;
3731 dma_addr_t dma_fx00;
3732 request_t *ring_fx00;
3733 uint16_t length_fx00;
3734 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3737 struct qla_fw_resources {
3748 #define QLA_IOCB_PCT_LIMIT 95
3750 struct qla_buf_pool {
3757 uint32_t take_snapshot:1;
3758 unsigned long *buf_map;
3760 dma_addr_t *dma_array;
3763 /*Queue pair data structure */
3769 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3770 * legacy code. For other Qpair(s), it will point at qp_lock.
3772 spinlock_t *qp_lock_ptr;
3773 struct scsi_qla_host *vha;
3776 /* distill these fields down to 'online=0/1'
3777 * ha->flags.eeh_busy
3778 * ha->flags.pci_channel_io_perm_failure
3779 * base_vha->loop_state
3782 /* move vha->flags.difdix_supported here */
3783 uint32_t difdix_supported:1;
3784 uint32_t delete_in_progress:1;
3785 uint32_t fw_started:1;
3786 uint32_t enable_class_2:1;
3787 uint32_t enable_explicit_conf:1;
3788 uint32_t use_shadow_reg:1;
3789 uint32_t rcv_intr:1;
3791 uint16_t id; /* qp number used with FW */
3792 uint16_t vp_idx; /* vport ID */
3793 mempool_t *srb_mempool;
3795 struct pci_dev *pdev;
3796 void (*reqq_start_iocbs)(struct qla_qpair *);
3798 /* to do: New driver: move queues to here instead of pointers */
3799 struct req_que *req;
3800 struct rsp_que *rsp;
3801 struct atio_que *atio;
3802 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3803 struct qla_hw_data *hw;
3804 struct work_struct q_work;
3805 struct qla_counters counters;
3807 struct list_head qp_list_elem; /* vha->qp_list */
3808 struct list_head hints_list;
3810 uint16_t retry_term_cnt;
3811 __le32 retry_term_exchg_addr;
3812 uint64_t retry_term_jiff;
3813 struct qla_tgt_counters tgt_counters;
3816 struct qla_fw_resources fwres ____cacheline_aligned;
3817 struct qla_buf_pool buf_pool;
3819 u32 cmd_completion_cnt;
3820 u32 prev_completion_cnt;
3823 /* Place holder for FW buffer parameters */
3830 struct rdp_req_payload {
3831 uint32_t els_request;
3832 uint32_t desc_list_len;
3834 /* NPIV descriptor */
3839 uint8_t nport_id[3];
3843 struct rdp_rsp_payload {
3849 /* LS Request Info descriptor */
3853 __be32 req_payload_word_0;
3856 /* LS Request Info descriptor */
3860 __be32 req_payload_word_0;
3861 } ls_req_info_desc2;
3863 /* SFP diagnostic param descriptor */
3875 /* Port Speed Descriptor */
3880 __be16 operating_speed;
3883 /* Link Error Status Descriptor */
3887 __be32 link_fail_cnt;
3888 __be32 loss_sync_cnt;
3889 __be32 loss_sig_cnt;
3890 __be32 prim_seq_err_cnt;
3891 __be32 inval_xmit_word_cnt;
3892 __be32 inval_crc_cnt;
3893 uint8_t pn_port_phy_type;
3894 uint8_t reserved[3];
3897 /* Port name description with diag param */
3901 uint8_t WWNN[WWN_SIZE];
3902 uint8_t WWPN[WWN_SIZE];
3903 } port_name_diag_desc;
3905 /* Port Name desc for Direct attached Fx_Port or Nx_Port */
3909 uint8_t WWNN[WWN_SIZE];
3910 uint8_t WWPN[WWN_SIZE];
3911 } port_name_direct_desc;
3913 /* Buffer Credit descriptor */
3918 __be32 attached_fcport_b2b;
3920 } buffer_credit_desc;
3922 /* Optical Element Data Descriptor */
3930 __be32 element_flags;
3931 } optical_elmt_desc[5];
3933 /* Optical Product Data Descriptor */
3937 uint8_t vendor_name[16];
3938 uint8_t part_number[16];
3939 uint8_t serial_number[16];
3940 uint8_t revision[4];
3942 } optical_prod_desc;
3945 #define RDP_DESC_LEN(obj) \
3946 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
3948 #define RDP_PORT_SPEED_1GB BIT_15
3949 #define RDP_PORT_SPEED_2GB BIT_14
3950 #define RDP_PORT_SPEED_4GB BIT_13
3951 #define RDP_PORT_SPEED_10GB BIT_12
3952 #define RDP_PORT_SPEED_8GB BIT_11
3953 #define RDP_PORT_SPEED_16GB BIT_10
3954 #define RDP_PORT_SPEED_32GB BIT_9
3955 #define RDP_PORT_SPEED_64GB BIT_8
3956 #define RDP_PORT_SPEED_UNKNOWN BIT_0
3958 struct scsi_qlt_host {
3959 void *target_lport_ptr;
3960 struct mutex tgt_mutex;
3961 struct mutex tgt_host_action_mutex;
3962 struct qla_tgt *qla_tgt;
3965 struct qlt_hw_data {
3966 /* Protected by hw lock */
3967 uint32_t node_name_set:1;
3969 dma_addr_t atio_dma; /* Physical address. */
3970 struct atio *atio_ring; /* Base virtual address */
3971 struct atio *atio_ring_ptr; /* Current address. */
3972 uint16_t atio_ring_index; /* Current index. */
3973 uint16_t atio_q_length;
3974 __le32 __iomem *atio_q_in;
3975 __le32 __iomem *atio_q_out;
3977 const struct qla_tgt_func_tmpl *tgt_ops;
3980 __le16 saved_exchange_count;
3981 __le32 saved_firmware_options_1;
3982 __le32 saved_firmware_options_2;
3983 __le32 saved_firmware_options_3;
3984 uint8_t saved_firmware_options[2];
3985 uint8_t saved_add_firmware_options[2];
3987 uint8_t tgt_node_name[WWN_SIZE];
3989 struct dentry *dfs_tgt_sess;
3990 struct dentry *dfs_tgt_port_database;
3991 struct dentry *dfs_naqp;
3993 struct list_head q_full_list;
3994 uint32_t num_pend_cmds;
3995 uint32_t num_qfull_cmds_alloc;
3996 uint32_t num_qfull_cmds_dropped;
3997 spinlock_t q_full_lock;
3998 uint32_t leak_exchg_thresh_hold;
3999 spinlock_t sess_lock;
4001 #define DEFAULT_NAQP 2
4002 spinlock_t atio_lock ____cacheline_aligned;
4005 #define MAX_QFULL_CMDS_ALLOC 8192
4006 #define Q_FULL_THRESH_HOLD_PERCENT 90
4007 #define Q_FULL_THRESH_HOLD(ha) \
4008 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
4010 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
4012 struct qla_hw_data_stat {
4017 /* refer to pcie_do_recovery reference */
4020 QLA_PCI_ERR_DETECTED,
4021 QLA_PCI_MMIO_ENABLED,
4023 } pci_error_state_t;
4025 * Qlogic host adapter specific data structure.
4027 struct qla_hw_data {
4028 struct pci_dev *pdev;
4030 #define SRB_MIN_REQ 128
4031 mempool_t *srb_mempool;
4032 u8 port_name[WWN_SIZE];
4035 uint32_t mbox_int :1;
4036 uint32_t mbox_busy :1;
4037 uint32_t disable_risc_code_load :1;
4038 uint32_t enable_64bit_addressing :1;
4039 uint32_t enable_lip_reset :1;
4040 uint32_t enable_target_reset :1;
4041 uint32_t enable_lip_full_login :1;
4042 uint32_t enable_led_scheme :1;
4044 uint32_t msi_enabled :1;
4045 uint32_t msix_enabled :1;
4046 uint32_t disable_serdes :1;
4047 uint32_t gpsc_supported :1;
4048 uint32_t npiv_supported :1;
4049 uint32_t pci_channel_io_perm_failure :1;
4050 uint32_t fce_enabled :1;
4051 uint32_t fac_supported :1;
4053 uint32_t chip_reset_done :1;
4054 uint32_t running_gold_fw :1;
4055 uint32_t eeh_busy :1;
4056 uint32_t disable_msix_handshake :1;
4057 uint32_t fcp_prio_enabled :1;
4058 uint32_t isp82xx_fw_hung:1;
4059 uint32_t nic_core_hung:1;
4061 uint32_t quiesce_owner:1;
4062 uint32_t nic_core_reset_hdlr_active:1;
4063 uint32_t nic_core_reset_owner:1;
4064 uint32_t isp82xx_no_md_cap:1;
4065 uint32_t host_shutting_down:1;
4066 uint32_t idc_compl_status:1;
4067 uint32_t mr_reset_hdlr_active:1;
4068 uint32_t mr_intr_valid:1;
4070 uint32_t dport_enabled:1;
4071 uint32_t fawwpn_enabled:1;
4072 uint32_t exlogins_enabled:1;
4073 uint32_t exchoffld_enabled:1;
4077 uint32_t fw_started:1;
4078 uint32_t fw_init_done:1;
4080 uint32_t lr_detected:1;
4082 uint32_t rida_fmt2:1;
4083 uint32_t purge_mbox:1;
4084 uint32_t n2n_bigger:1;
4085 uint32_t secure_adapter:1;
4086 uint32_t secure_fw:1;
4087 /* Supported by Adapter */
4088 uint32_t scm_supported_a:1;
4089 /* Supported by Firmware */
4090 uint32_t scm_supported_f:1;
4091 /* Enabled in Driver */
4092 uint32_t scm_enabled:1;
4094 uint32_t edif_enabled:1;
4095 uint32_t n2n_fw_acc_sec:1;
4096 uint32_t plogi_template_valid:1;
4097 uint32_t port_isolated:1;
4098 uint32_t eeh_flush:2;
4099 #define EEH_FLUSH_RDY 1
4100 #define EEH_FLUSH_DONE 2
4104 uint16_t lr_distance; /* 32G & above */
4105 #define LR_DISTANCE_5K 1
4106 #define LR_DISTANCE_10K 0
4108 /* This spinlock is used to protect "io transactions", you must
4109 * acquire it before doing any IO to the card, eg with RD_REG*() and
4110 * WRT_REG*() for the duration of your entire commandtransaction.
4112 * This spinlock is of lower priority than the io request lock.
4115 spinlock_t hardware_lock ____cacheline_aligned;
4118 device_reg_t *iobase; /* Base I/O address */
4119 resource_size_t pio_address;
4121 #define MIN_IOBASE_LEN 0x100
4122 dma_addr_t bar0_hdl;
4124 void __iomem *cregbase;
4125 dma_addr_t bar2_hdl;
4126 #define BAR0_LEN_FX00 (1024 * 1024)
4127 #define BAR2_LEN_FX00 (128 * 1024)
4129 uint32_t rqstq_intr_code;
4130 uint32_t mbx_intr_code;
4131 uint32_t req_que_len;
4132 uint32_t rsp_que_len;
4133 uint32_t req_que_off;
4134 uint32_t rsp_que_off;
4135 unsigned long eeh_jif;
4137 /* Multi queue data structs */
4138 device_reg_t *mqiobase;
4139 device_reg_t *msixbase;
4140 uint16_t msix_count;
4142 struct req_que **req_q_map;
4143 struct rsp_que **rsp_q_map;
4144 struct qla_qpair **queue_pair_map;
4145 struct qla_qpair **qp_cpu_map;
4146 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
4147 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
4148 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
4149 / sizeof(unsigned long)];
4150 uint8_t max_req_queues;
4151 uint8_t max_rsp_queues;
4154 struct qla_qpair *base_qpair;
4155 struct qla_npiv_entry *npiv_info;
4156 uint16_t nvram_npiv_size;
4158 uint16_t switch_cap;
4159 #define FLOGI_SEQ_DEL BIT_8
4160 #define FLOGI_MID_SUPPORT BIT_10
4161 #define FLOGI_VSAN_SUPPORT BIT_12
4162 #define FLOGI_SP_SUPPORT BIT_13
4164 uint8_t port_no; /* Physical port of adapter */
4165 uint8_t exch_starvation;
4167 /* Timeout timers. */
4168 uint8_t loop_down_abort_time; /* port down timer */
4169 atomic_t loop_down_timer; /* loop down timer */
4170 uint8_t link_down_timeout; /* link down timeout */
4171 uint16_t max_loop_id;
4172 uint16_t max_fibre_devices; /* Maximum number of targets */
4175 uint16_t min_external_loopid; /* First external loop Id */
4177 #define PORT_SPEED_UNKNOWN 0xFFFF
4178 #define PORT_SPEED_1GB 0x00
4179 #define PORT_SPEED_2GB 0x01
4180 #define PORT_SPEED_AUTO 0x02
4181 #define PORT_SPEED_4GB 0x03
4182 #define PORT_SPEED_8GB 0x04
4183 #define PORT_SPEED_16GB 0x05
4184 #define PORT_SPEED_32GB 0x06
4185 #define PORT_SPEED_64GB 0x07
4186 #define PORT_SPEED_10GB 0x13
4187 uint16_t link_data_rate; /* F/W operating speed */
4188 uint16_t set_data_rate; /* Set by user */
4190 uint8_t current_topology;
4191 uint8_t prev_topology;
4192 #define ISP_CFG_NL 1
4194 #define ISP_CFG_FL 4
4197 uint8_t operating_mode; /* F/W operating mode */
4202 uint8_t interrupts_on;
4203 uint32_t isp_abort_cnt;
4204 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
4205 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
4206 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
4207 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
4208 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
4209 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
4210 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
4211 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
4212 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
4213 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
4214 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
4215 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
4216 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
4219 #define DT_ISP2100 BIT_0
4220 #define DT_ISP2200 BIT_1
4221 #define DT_ISP2300 BIT_2
4222 #define DT_ISP2312 BIT_3
4223 #define DT_ISP2322 BIT_4
4224 #define DT_ISP6312 BIT_5
4225 #define DT_ISP6322 BIT_6
4226 #define DT_ISP2422 BIT_7
4227 #define DT_ISP2432 BIT_8
4228 #define DT_ISP5422 BIT_9
4229 #define DT_ISP5432 BIT_10
4230 #define DT_ISP2532 BIT_11
4231 #define DT_ISP8432 BIT_12
4232 #define DT_ISP8001 BIT_13
4233 #define DT_ISP8021 BIT_14
4234 #define DT_ISP2031 BIT_15
4235 #define DT_ISP8031 BIT_16
4236 #define DT_ISPFX00 BIT_17
4237 #define DT_ISP8044 BIT_18
4238 #define DT_ISP2071 BIT_19
4239 #define DT_ISP2271 BIT_20
4240 #define DT_ISP2261 BIT_21
4241 #define DT_ISP2061 BIT_22
4242 #define DT_ISP2081 BIT_23
4243 #define DT_ISP2089 BIT_24
4244 #define DT_ISP2281 BIT_25
4245 #define DT_ISP2289 BIT_26
4246 #define DT_ISP_LAST (DT_ISP2289 << 1)
4248 uint32_t device_type;
4249 #define DT_T10_PI BIT_25
4250 #define DT_IIDMA BIT_26
4251 #define DT_FWI2 BIT_27
4252 #define DT_ZIO_SUPPORTED BIT_28
4253 #define DT_OEM_001 BIT_29
4254 #define DT_ISP2200A BIT_30
4255 #define DT_EXTENDED_IDS BIT_31
4257 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
4258 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
4259 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
4260 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
4261 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
4262 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
4263 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
4264 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
4265 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
4266 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
4267 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
4268 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
4269 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
4270 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
4271 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
4272 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
4273 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
4274 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
4275 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
4276 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
4277 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
4278 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
4279 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
4280 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
4281 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
4282 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
4284 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
4285 IS_QLA6312(ha) || IS_QLA6322(ha))
4286 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
4287 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
4288 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
4289 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
4290 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
4291 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
4292 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
4293 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
4295 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
4296 IS_QLA8031(ha) || IS_QLA8044(ha))
4297 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
4298 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
4299 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
4300 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
4301 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
4303 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4304 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4305 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
4306 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4307 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4308 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4309 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4310 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
4312 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
4313 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
4314 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
4315 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
4316 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
4317 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
4318 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
4319 #define IS_MQUE_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4321 #define IS_BIDI_CAPABLE(ha) \
4322 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4323 /* Bit 21 of fw_attributes decides the MCTP capabilities */
4324 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
4325 ((ha)->fw_attributes_ext[0] & BIT_0))
4326 #define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14)
4327 #define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS)
4328 #define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD)
4329 #define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp))
4330 #define QLA_LS_ABTS_WAIT_ENABLED(_sp) \
4331 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4332 #define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \
4333 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4334 #define QLA_ABTS_WAIT_ENABLED(_sp) \
4335 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4337 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4339 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4341 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
4342 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4344 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
4345 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
4346 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4348 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
4349 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
4350 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4352 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4354 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
4355 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4356 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
4357 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4358 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4359 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
4360 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4362 #define IS_ZIO_THRESHOLD_CAPABLE(ha) \
4363 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\
4364 (ha->zio_mode == QLA_ZIO_MODE_6))
4366 /* HBA serial number */
4371 /* NVRAM configuration data */
4372 #define MAX_NVRAM_SIZE 4096
4373 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
4374 uint16_t nvram_size;
4375 uint16_t nvram_base;
4381 uint16_t loop_reset_delay;
4382 uint8_t retry_count;
4383 uint8_t login_timeout;
4385 int port_down_retry_count;
4387 uint8_t aen_mbx_count;
4388 atomic_t num_pend_mbx_stage1;
4389 atomic_t num_pend_mbx_stage2;
4390 atomic_t num_pend_mbx_stage3;
4391 uint16_t frame_payload_size;
4393 uint32_t login_retry_count;
4394 /* SNS command interfaces. */
4395 ms_iocb_entry_t *ms_iocb;
4396 dma_addr_t ms_iocb_dma;
4397 struct ct_sns_pkt *ct_sns;
4398 dma_addr_t ct_sns_dma;
4399 /* SNS command interfaces for 2200. */
4400 struct sns_cmd_pkt *sns_cmd;
4401 dma_addr_t sns_cmd_dma;
4403 #define SFP_DEV_SIZE 512
4404 #define SFP_BLOCK_SIZE 64
4405 #define SFP_RTDI_LEN SFP_BLOCK_SIZE
4408 dma_addr_t sfp_data_dma;
4410 struct qla_flt_header *flt;
4413 #define XGMAC_DATA_SIZE 4096
4415 dma_addr_t xgmac_data_dma;
4417 #define DCBX_TLV_DATA_SIZE 4096
4419 dma_addr_t dcbx_tlv_dma;
4421 struct task_struct *dpc_thread;
4422 uint8_t dpc_active; /* DPC routine is active */
4424 dma_addr_t gid_list_dma;
4425 struct gid_list_info *gid_list;
4426 int gid_list_info_size;
4428 /* Small DMA pool allocations -- maximum 256 bytes in length. */
4429 #define DMA_POOL_SIZE 256
4430 struct dma_pool *s_dma_pool;
4432 dma_addr_t init_cb_dma;
4435 dma_addr_t ex_init_cb_dma;
4436 struct ex_init_cb_81xx *ex_init_cb;
4437 dma_addr_t sf_init_cb_dma;
4438 struct init_sf_cb *sf_init_cb;
4440 void *scm_fpin_els_buff;
4441 uint64_t scm_fpin_els_buff_size;
4442 bool scm_fpin_valid;
4443 bool scm_fpin_payload_size;
4446 dma_addr_t async_pd_dma;
4448 #define ENABLE_EXTENDED_LOGIN BIT_7
4450 /* Extended Logins */
4452 dma_addr_t exlogin_buf_dma;
4453 uint32_t exlogin_size;
4455 #define ENABLE_EXCHANGE_OFFLD BIT_2
4457 /* Exchange Offload */
4458 void *exchoffld_buf;
4459 dma_addr_t exchoffld_buf_dma;
4461 int exchoffld_count;
4464 struct fc_els_flogi plogi_els_payld;
4465 #define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4)
4469 /* These are used by mailbox operations. */
4470 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
4471 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
4472 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
4475 struct mbx_cmd_32 *mcp32;
4477 unsigned long mbx_cmd_flags;
4478 #define MBX_INTERRUPT 1
4479 #define MBX_INTR_WAIT 2
4480 #define MBX_UPDATE_FLASH_ACTIVE 3
4482 struct mutex vport_lock; /* Virtual port synchronization */
4483 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
4484 struct mutex mq_lock; /* multi-queue synchronization */
4485 struct completion mbx_cmd_comp; /* Serialize mbx access */
4486 struct completion mbx_intr_comp; /* Used for completion notification */
4487 struct completion dcbx_comp; /* For set port config notification */
4488 struct completion lb_portup_comp; /* Used to wait for link up during
4490 #define DCBX_COMP_TIMEOUT 20
4491 #define LB_PORTUP_COMP_TIMEOUT 10
4493 int notify_dcbx_comp;
4494 int notify_lb_portup_comp;
4495 struct mutex selflogin_lock;
4497 /* Basic firmware related information. */
4498 uint16_t fw_major_version;
4499 uint16_t fw_minor_version;
4500 uint16_t fw_subminor_version;
4501 uint16_t fw_attributes;
4502 uint16_t fw_attributes_h;
4503 #define FW_ATTR_H_NVME_FBURST BIT_1
4504 #define FW_ATTR_H_NVME BIT_10
4505 #define FW_ATTR_H_NVME_UPDATED BIT_14
4507 /* About firmware SCM support */
4508 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12
4509 /* Brocade fabric attached */
4510 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000
4511 /* Cisco fabric attached */
4512 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000
4513 #define FW_ATTR_EXT0_NVME2 BIT_13
4514 #define FW_ATTR_EXT0_EDIF BIT_5
4515 uint16_t fw_attributes_ext[2];
4516 uint32_t fw_memory_size;
4517 uint32_t fw_transfer_size;
4518 uint32_t fw_srisc_address;
4519 #define RISC_START_ADDRESS_2100 0x1000
4520 #define RISC_START_ADDRESS_2300 0x800
4521 #define RISC_START_ADDRESS_2400 0x100000
4523 uint16_t orig_fw_tgt_xcb_count;
4524 uint16_t cur_fw_tgt_xcb_count;
4525 uint16_t orig_fw_xcb_count;
4526 uint16_t cur_fw_xcb_count;
4527 uint16_t orig_fw_iocb_count;
4528 uint16_t cur_fw_iocb_count;
4529 uint16_t fw_max_fcf_count;
4531 uint32_t fw_shared_ram_start;
4532 uint32_t fw_shared_ram_end;
4533 uint32_t fw_ddr_ram_start;
4534 uint32_t fw_ddr_ram_end;
4536 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
4537 uint8_t fw_seriallink_options[4];
4538 __le16 fw_seriallink_options24[4];
4540 uint8_t serdes_version[3];
4541 uint8_t mpi_version[3];
4542 uint32_t mpi_capabilities;
4543 uint8_t phy_version[3];
4544 uint8_t pep_version[3];
4546 /* Firmware dump template */
4552 struct qla2xxx_fw_dump *fw_dump;
4553 uint32_t fw_dump_len;
4554 u32 fw_dump_alloc_len;
4556 unsigned long fw_dump_cap_flags;
4557 #define RISC_PAUSE_CMPL 0
4558 #define DMA_SHUTDOWN_CMPL 1
4559 #define ISP_RESET_CMPL 2
4560 #define RISC_RDY_AFT_RESET 3
4561 #define RISC_SRAM_DUMP_CMPL 4
4562 #define RISC_EXT_MEM_DUMP_CMPL 5
4563 #define ISP_MBX_RDY 6
4564 #define ISP_SOFT_RESET_CMPL 7
4565 int fw_dump_reading;
4567 u32 mpi_fw_dump_len;
4568 unsigned int mpi_fw_dump_reading:1;
4569 unsigned int mpi_fw_dumped:1;
4570 int prev_minidump_failed;
4573 /* Current size of mctp dump is 0x086064 bytes */
4574 #define MCTP_DUMP_SIZE 0x086064
4575 dma_addr_t mctp_dump_dma;
4578 int mctp_dump_reading;
4579 uint32_t chain_offset;
4580 struct dentry *dfs_dir;
4581 struct dentry *dfs_fce;
4582 struct dentry *dfs_tgt_counters;
4583 struct dentry *dfs_fw_resource_cnt;
4589 uint64_t fce_wr, fce_rd;
4590 struct mutex fce_mutex;
4593 uint16_t chip_revision;
4595 uint16_t product_id[4];
4597 uint8_t model_number[16+1];
4598 char model_desc[80];
4599 uint8_t adapter_id[16+1];
4601 /* Option ROM information. */
4602 char *optrom_buffer;
4603 uint32_t optrom_size;
4605 #define QLA_SWAITING 0
4606 #define QLA_SREADING 1
4607 #define QLA_SWRITING 2
4608 uint32_t optrom_region_start;
4609 uint32_t optrom_region_size;
4610 struct mutex optrom_mutex;
4612 /* PCI expansion ROM image information. */
4613 #define ROM_CODE_TYPE_BIOS 0
4614 #define ROM_CODE_TYPE_FCODE 1
4615 #define ROM_CODE_TYPE_EFI 3
4616 uint8_t bios_revision[2];
4617 uint8_t efi_revision[2];
4618 uint8_t fcode_revision[16];
4619 uint32_t fw_revision[4];
4621 uint32_t gold_fw_version[4];
4623 /* Offsets for flash/nvram access (set to ~0 if not used). */
4624 uint32_t flash_conf_off;
4625 uint32_t flash_data_off;
4626 uint32_t nvram_conf_off;
4627 uint32_t nvram_data_off;
4629 uint32_t fdt_wrt_disable;
4630 uint32_t fdt_wrt_enable;
4631 uint32_t fdt_erase_cmd;
4632 uint32_t fdt_block_size;
4633 uint32_t fdt_unprotect_sec_cmd;
4634 uint32_t fdt_protect_sec_cmd;
4635 uint32_t fdt_wrt_sts_reg_cmd;
4638 uint32_t flt_region_flt;
4639 uint32_t flt_region_fdt;
4640 uint32_t flt_region_boot;
4641 uint32_t flt_region_boot_sec;
4642 uint32_t flt_region_fw;
4643 uint32_t flt_region_fw_sec;
4644 uint32_t flt_region_vpd_nvram;
4645 uint32_t flt_region_vpd_nvram_sec;
4646 uint32_t flt_region_vpd;
4647 uint32_t flt_region_vpd_sec;
4648 uint32_t flt_region_nvram;
4649 uint32_t flt_region_nvram_sec;
4650 uint32_t flt_region_npiv_conf;
4651 uint32_t flt_region_gold_fw;
4652 uint32_t flt_region_fcp_prio;
4653 uint32_t flt_region_bootload;
4654 uint32_t flt_region_img_status_pri;
4655 uint32_t flt_region_img_status_sec;
4656 uint32_t flt_region_aux_img_status_pri;
4657 uint32_t flt_region_aux_img_status_sec;
4659 uint8_t active_image;
4661 /* Needed for BEACON */
4662 uint16_t beacon_blink_led;
4663 uint8_t beacon_color_state;
4664 #define QLA_LED_GRN_ON 0x01
4665 #define QLA_LED_YLW_ON 0x02
4666 #define QLA_LED_ABR_ON 0x04
4667 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
4668 /* ISP2322: red, green, amber. */
4672 struct qla_msix_entry *msix_entries;
4674 struct list_head vp_list; /* list of VP */
4675 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4676 sizeof(unsigned long)];
4677 uint16_t num_vhosts; /* number of vports created */
4678 uint16_t num_vsans; /* number of vsan created */
4679 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
4680 int cur_vport_count;
4682 struct qla_chip_state_84xx *cs84xx;
4683 struct isp_operations *isp_ops;
4684 struct workqueue_struct *wq;
4685 struct work_struct heartbeat_work;
4686 struct qlfc_fw fw_buf;
4687 unsigned long last_heartbeat_run_jiffies;
4689 /* FCP_CMND priority support */
4690 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4692 struct dma_pool *dl_dma_pool;
4693 #define DSD_LIST_DMA_POOL_SIZE 512
4695 struct dma_pool *fcp_cmnd_dma_pool;
4696 mempool_t *ctx_mempool;
4697 #define FCP_CMND_DMA_POOL_SIZE 512
4699 void __iomem *nx_pcibase; /* Base I/O address */
4700 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
4701 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
4704 uint32_t curr_window;
4705 uint32_t ddr_mn_window;
4706 unsigned long mn_win_crb;
4707 unsigned long ms_win_crb;
4709 uint32_t fcoe_dev_init_timeout;
4710 uint32_t fcoe_reset_timeout;
4712 uint16_t portnum; /* port number */
4714 struct fw_blob *hablob;
4715 struct qla82xx_legacy_intr_set nx_legacy_intr;
4717 uint16_t gbl_dsd_inuse;
4718 uint16_t gbl_dsd_avail;
4719 struct list_head gbl_dsd_list;
4720 #define NUM_DSD_CHAIN 4096
4723 uint32_t file_prd_off; /* File firmware product offset */
4725 uint32_t md_template_size;
4727 dma_addr_t md_tmplt_hdr_dma;
4729 uint32_t md_dump_size;
4733 /* QLA83XX IDC specific fields */
4734 uint32_t idc_audit_ts;
4735 uint32_t idc_extend_tmo;
4737 /* DPC low-priority workqueue */
4738 struct workqueue_struct *dpc_lp_wq;
4739 struct work_struct idc_aen;
4740 /* DPC high-priority workqueue */
4741 struct workqueue_struct *dpc_hp_wq;
4742 struct work_struct nic_core_reset;
4743 struct work_struct idc_state_handler;
4744 struct work_struct nic_core_unrecoverable;
4745 struct work_struct board_disable;
4747 struct mr_data_fx00 mr;
4748 uint32_t chip_reset;
4750 struct qlt_hw_data tgt;
4751 int allow_cna_fw_dump;
4752 uint32_t fw_ability_mask;
4753 uint16_t min_supported_speed;
4754 uint16_t max_supported_speed;
4756 /* DMA pool for the DIF bundling buffers */
4757 struct dma_pool *dif_bundl_pool;
4758 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4761 struct list_head head;
4765 struct list_head head;
4770 unsigned long long dif_bundle_crossed_pages;
4771 unsigned long long dif_bundle_reads;
4772 unsigned long long dif_bundle_writes;
4773 unsigned long long dif_bundle_kallocs;
4774 unsigned long long dif_bundle_dma_allocs;
4776 atomic_t nvme_active_aen_cnt;
4777 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
4779 uint8_t fc4_type_priority;
4781 atomic_t zio_threshold;
4782 uint16_t last_zio_threshold;
4784 #define DEFAULT_ZIO_THRESHOLD 5
4786 struct qla_hw_data_stat stat;
4787 pci_error_state_t pci_error_state;
4788 struct dma_pool *purex_dma_pool;
4789 struct btree_head32 host_map;
4791 #define EDIF_NUM_SA_INDEX 512
4792 #define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX
4793 void *edif_rx_sa_id_map;
4794 void *edif_tx_sa_id_map;
4795 spinlock_t sadb_fp_lock;
4797 struct list_head sadb_tx_index_list;
4798 struct list_head sadb_rx_index_list;
4799 spinlock_t sadb_lock; /* protects list */
4800 struct els_reject elsrej;
4801 u8 edif_post_stop_cnt_down;
4802 struct qla_vp_map *vp_map;
4805 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))
4807 struct active_regions {
4810 uint8_t board_config;
4812 uint8_t npiv_config_0_1;
4813 uint8_t npiv_config_2_3;
4814 uint8_t nvme_params;
4818 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4819 #define FW_ABILITY_MAX_SPEED_16G 0x0
4820 #define FW_ABILITY_MAX_SPEED_32G 0x1
4821 #define FW_ABILITY_MAX_SPEED(ha) \
4822 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4824 #define QLA_GET_DATA_RATE 0
4825 #define QLA_SET_DATA_RATE_NOLR 1
4826 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
4828 #define QLA_DEFAULT_PAYLOAD_SIZE 64
4830 * This item might be allocated with a size > sizeof(struct purex_item).
4831 * The "size" variable gives the size of the payload (which
4832 * is variable) starting at "iocb".
4835 struct list_head list;
4836 struct scsi_qla_host *vha;
4837 void (*process_item)(struct scsi_qla_host *vha,
4838 struct purex_item *pkt);
4846 #include "qla_edif.h"
4848 #define SCM_FLAG_RDF_REJECT 0x00
4849 #define SCM_FLAG_RDF_COMPLETED 0x01
4851 #define QLA_CON_PRIMITIVE_RECEIVED 0x1
4852 #define QLA_CONGESTION_ARB_WARNING 0x1
4853 #define QLA_CONGESTION_ARB_ALARM 0X2
4856 * Qlogic scsi host structure
4858 typedef struct scsi_qla_host {
4859 struct list_head list;
4860 struct list_head vp_fcports; /* list of fcports */
4861 struct list_head work_list;
4862 spinlock_t work_lock;
4863 struct work_struct iocb_work;
4865 /* Commonly used flags and state information. */
4866 struct Scsi_Host *host;
4867 unsigned long host_no;
4868 uint8_t host_str[16];
4871 uint32_t init_done :1;
4873 uint32_t reset_active :1;
4875 uint32_t management_server_logged_in :1;
4876 uint32_t process_response_queue :1;
4877 uint32_t difdix_supported:1;
4878 uint32_t delete_progress:1;
4880 uint32_t fw_tgt_reported:1;
4881 uint32_t bbcr_enable:1;
4882 uint32_t qpairs_available:1;
4883 uint32_t qpairs_req_created:1;
4884 uint32_t qpairs_rsp_created:1;
4885 uint32_t nvme_enabled:1;
4886 uint32_t nvme_first_burst:1;
4887 uint32_t nvme2_enabled:1;
4890 atomic_t loop_state;
4891 #define LOOP_TIMEOUT 1
4894 #define LOOP_UPDATE 4
4895 #define LOOP_READY 5
4898 unsigned long buf_expired;
4899 unsigned long relogin_jif;
4900 unsigned long dpc_flags;
4901 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4902 #define RESET_ACTIVE 1
4903 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4904 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4905 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4906 #define LOOP_RESYNC_ACTIVE 5
4907 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4908 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
4909 #define RELOGIN_NEEDED 8
4910 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4911 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
4912 #define BEACON_BLINK_NEEDED 11
4913 #define REGISTER_FDMI_NEEDED 12
4914 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4915 #define UNLOADING 15
4916 #define NPIV_CONFIG_NEEDED 16
4917 #define ISP_UNRECOVERABLE 17
4918 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4919 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4920 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4921 #define N2N_LINK_RESET 21
4922 #define PORT_UPDATE_NEEDED 22
4923 #define FX00_RESET_RECOVERY 23
4924 #define FX00_TARGET_SCAN 24
4925 #define FX00_CRITEMP_RECOVERY 25
4926 #define FX00_HOST_INFO_RESEND 26
4927 #define QPAIR_ONLINE_CHECK_NEEDED 27
4928 #define DO_EEH_RECOVERY 28
4929 #define DETECT_SFP_CHANGE 29
4930 #define N2N_LOGIN_NEEDED 30
4931 #define IOCB_WORK_ACTIVE 31
4932 #define SET_ZIO_THRESHOLD_NEEDED 32
4933 #define ISP_ABORT_TO_ROM 33
4934 #define VPORT_DELETE 34
4936 #define PROCESS_PUREX_IOCB 63
4938 unsigned long pci_flags;
4939 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4940 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4941 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4943 uint32_t device_flags;
4944 #define SWITCH_FOUND BIT_0
4945 #define DFLG_NO_CABLE BIT_1
4946 #define DFLG_DEV_FAILED BIT_5
4948 /* ISP configuration data. */
4949 uint16_t loop_id; /* Host adapter loop id */
4950 uint16_t self_login_loop_id; /* host adapter loop id
4951 * get it on self login
4953 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4954 * no need of allocating it for
4958 port_id_t d_id; /* Host adapter port id */
4959 uint8_t marker_needed;
4960 uint16_t mgmt_svr_loop_id;
4964 /* Timeout timers. */
4965 uint8_t loop_down_abort_time; /* port down timer */
4966 atomic_t loop_down_timer; /* loop down timer */
4967 uint8_t link_down_timeout; /* link down timeout */
4969 uint32_t timer_active;
4970 struct timer_list timer;
4972 uint8_t node_name[WWN_SIZE];
4973 uint8_t port_name[WWN_SIZE];
4974 uint8_t fabric_node_name[WWN_SIZE];
4975 uint8_t fabric_port_name[WWN_SIZE];
4977 struct nvme_fc_local_port *nvme_local_port;
4978 struct completion nvme_del_done;
4980 uint16_t fcoe_vlan_id;
4981 uint16_t fcoe_fcf_idx;
4982 uint8_t fcoe_vn_port_mac[6];
4984 /* list of commands waiting on workqueue */
4985 struct list_head qla_cmd_list;
4986 struct list_head unknown_atio_list;
4987 spinlock_t cmd_list_lock;
4988 struct delayed_work unknown_atio_work;
4990 /* Counter to detect races between ELS and RSCN events */
4991 atomic_t generation_tick;
4992 /* Time when global fcport update has been scheduled */
4993 int total_fcport_update_gen;
4994 /* List of pending LOGOs, protected by tgt_mutex */
4995 struct list_head logo_list;
4996 /* List of pending PLOGI acks, protected by hw lock */
4997 struct list_head plogi_ack_list;
4999 struct list_head qp_list;
5001 uint32_t vp_abort_cnt;
5003 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
5004 uint16_t vp_idx; /* vport ID */
5005 struct qla_qpair *qpair; /* base qpair */
5007 unsigned long vp_flags;
5008 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
5009 #define VP_CREATE_NEEDED 1
5010 #define VP_BIND_NEEDED 2
5011 #define VP_DELETE_NEEDED 3
5012 #define VP_SCR_NEEDED 4 /* State Change Request registration */
5013 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
5015 #define VP_OFFLINE 0
5018 // #define VP_DISABLE 3
5019 uint16_t vp_err_state;
5020 uint16_t vp_prev_err_state;
5021 #define VP_ERR_UNKWN 0
5022 #define VP_ERR_PORTDWN 1
5023 #define VP_ERR_FAB_UNSUPPORTED 2
5024 #define VP_ERR_FAB_NORESOURCES 3
5025 #define VP_ERR_FAB_LOGOUT 4
5026 #define VP_ERR_ADAP_NORESOURCES 5
5027 struct qla_hw_data *hw;
5028 struct scsi_qlt_host vha_tgt;
5029 struct req_que *req;
5030 int fw_heartbeat_counter;
5031 int seconds_since_last_heartbeat;
5032 struct fc_host_statistics fc_host_stat;
5033 struct qla_statistics qla_stats;
5034 struct bidi_statistics bidi_stats;
5035 atomic_t vref_count;
5036 struct qla8044_reset_template reset_tmplt;
5039 uint16_t u_ql2xexchoffld;
5040 uint16_t u_ql2xiniexchg;
5041 uint16_t qlini_mode;
5042 uint16_t ql2xexchoffld;
5043 uint16_t ql2xiniexchg;
5045 struct dentry *dfs_rport_root;
5048 struct list_head head;
5051 struct purex_item default_item;
5053 struct name_list_extended gnl;
5054 /* Count of active session/fcport */
5056 wait_queue_head_t fcport_waitQ;
5057 wait_queue_head_t vref_waitq;
5058 uint8_t min_supported_speed;
5059 uint8_t n2n_node_name[WWN_SIZE];
5060 uint8_t n2n_port_name[WWN_SIZE];
5062 __le16 dport_data[4];
5063 struct fab_scan scan;
5064 uint8_t scm_fabric_connection_flags;
5066 unsigned int irq_offset;
5069 u64 interface_err_cnt;
5070 u64 cmd_timeout_cnt;
5071 u64 reset_cmd_err_cnt;
5073 u64 short_link_down_cnt;
5074 struct edif_dbell e_dbell;
5075 struct pur_core pur_cinfo;
5077 #define DPORT_DIAG_IN_PROGRESS BIT_0
5078 #define DPORT_DIAG_CHIP_RESET_IN_PROGRESS BIT_1
5079 uint16_t dport_status;
5082 struct qla27xx_image_status {
5083 uint8_t image_status_mask;
5087 uint8_t bitmap; /* 28xx only */
5088 uint8_t reserved[2];
5093 /* 28xx aux image status bimap values */
5094 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
5095 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
5096 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
5097 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
5098 #define QLA28XX_AUX_IMG_NVME_PARAMS BIT_4
5100 #define SET_VP_IDX 1
5102 #define RESET_VP_IDX 3
5103 #define RESET_AL_PA 4
5106 scsi_qla_host_t *vha;
5110 dma_addr_t dma_addr; /* OUT */
5111 uint32_t dma_len; /* OUT */
5113 uint32_t tot_bytes; /* IN */
5114 struct scatterlist *cur_sg; /* IN */
5116 /* for book keeping, bzero on initial invocation */
5117 uint32_t bytes_consumed;
5119 uint32_t tot_partial;
5126 #define QLA_FW_STARTED(_ha) { \
5128 _ha->flags.fw_started = 1; \
5129 _ha->base_qpair->fw_started = 1; \
5130 for (i = 0; i < _ha->max_qpairs; i++) { \
5131 if (_ha->queue_pair_map[i]) \
5132 _ha->queue_pair_map[i]->fw_started = 1; \
5136 #define QLA_FW_STOPPED(_ha) { \
5138 _ha->flags.fw_started = 0; \
5139 _ha->base_qpair->fw_started = 0; \
5140 for (i = 0; i < _ha->max_qpairs; i++) { \
5141 if (_ha->queue_pair_map[i]) \
5142 _ha->queue_pair_map[i]->fw_started = 0; \
5147 #define SFUB_CHECKSUM_SIZE 4
5149 struct secure_flash_update_block {
5150 uint32_t block_info;
5151 uint32_t signature_lo;
5152 uint32_t signature_hi;
5153 uint32_t signature_upper[0x3e];
5156 struct secure_flash_update_block_pk {
5157 uint32_t block_info;
5158 uint32_t signature_lo;
5159 uint32_t signature_hi;
5160 uint32_t signature_upper[0x3e];
5161 uint32_t public_key[0x41];
5165 * Macros to help code, maintain, etc.
5167 #define LOOP_TRANSITION(ha) \
5168 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
5169 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
5170 atomic_read(&ha->loop_state) == LOOP_DOWN)
5172 #define STATE_TRANSITION(ha) \
5173 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
5174 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
5176 static inline bool qla_vha_mark_busy(scsi_qla_host_t *vha)
5178 atomic_inc(&vha->vref_count);
5180 if (vha->flags.delete_progress) {
5181 atomic_dec(&vha->vref_count);
5182 wake_up(&vha->vref_waitq);
5188 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
5189 atomic_dec(&__vha->vref_count); \
5190 wake_up(&__vha->vref_waitq); \
5193 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
5194 atomic_inc(&__qpair->ref_count); \
5196 if (__qpair->delete_in_progress) { \
5197 atomic_dec(&__qpair->ref_count); \
5204 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
5205 atomic_dec(&__qpair->ref_count)
5207 #define QLA_ENA_CONF(_ha) {\
5209 _ha->base_qpair->enable_explicit_conf = 1; \
5210 for (i = 0; i < _ha->max_qpairs; i++) { \
5211 if (_ha->queue_pair_map[i]) \
5212 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
5216 #define QLA_DIS_CONF(_ha) {\
5218 _ha->base_qpair->enable_explicit_conf = 0; \
5219 for (i = 0; i < _ha->max_qpairs; i++) { \
5220 if (_ha->queue_pair_map[i]) \
5221 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
5226 * qla2x00 local function return status codes
5228 #define MBS_MASK 0x3fff
5230 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
5231 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
5232 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
5233 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
5234 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
5235 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
5236 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
5237 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
5238 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
5239 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
5241 #define QLA_FUNCTION_TIMEOUT 0x100
5242 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
5243 #define QLA_FUNCTION_FAILED 0x102
5244 #define QLA_MEMORY_ALLOC_FAILED 0x103
5245 #define QLA_LOCK_TIMEOUT 0x104
5246 #define QLA_ABORTED 0x105
5247 #define QLA_SUSPENDED 0x106
5248 #define QLA_BUSY 0x107
5249 #define QLA_ALREADY_REGISTERED 0x109
5250 #define QLA_OS_TIMER_EXPIRED 0x10a
5251 #define QLA_ERR_NO_QPAIR 0x10b
5252 #define QLA_ERR_NOT_FOUND 0x10c
5253 #define QLA_ERR_FROM_FW 0x10d
5255 #define NVRAM_DELAY() udelay(10)
5258 * Flash support definitions
5260 #define OPTROM_SIZE_2300 0x20000
5261 #define OPTROM_SIZE_2322 0x100000
5262 #define OPTROM_SIZE_24XX 0x100000
5263 #define OPTROM_SIZE_25XX 0x200000
5264 #define OPTROM_SIZE_81XX 0x400000
5265 #define OPTROM_SIZE_82XX 0x800000
5266 #define OPTROM_SIZE_83XX 0x1000000
5267 #define OPTROM_SIZE_28XX 0x2000000
5269 #define OPTROM_BURST_SIZE 0x1000
5270 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
5272 #define QLA_DSDS_PER_IOCB 37
5274 #define QLA_SG_ALL 1024
5276 enum nexus_wait_type {
5282 #define INVALID_EDIF_SA_INDEX 0xffff
5283 #define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe
5285 #define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE
5287 /* edif hash element */
5288 struct edif_list_entry {
5289 uint16_t handle; /* nport_handle */
5290 uint32_t update_sa_index;
5291 uint32_t delete_sa_index;
5292 uint32_t count; /* counter for filtering sa_index */
5293 #define EDIF_ENTRY_FLAGS_CLEANUP 0x01 /* this index is being cleaned up */
5294 uint32_t flags; /* used by sadb cleanup code */
5295 fc_port_t *fcport; /* needed by rx delay timer function */
5296 struct timer_list timer; /* rx delay timer */
5297 struct list_head next;
5300 #define EDIF_TX_INDX_BASE 512
5301 #define EDIF_RX_INDX_BASE 0
5302 #define EDIF_RX_DELETE_FILTER_COUNT 3 /* delay queuing rx delete until this many */
5304 /* entry in the sa_index free pool */
5306 struct sa_index_pair {
5311 /* edif sa_index data structure */
5312 struct edif_sa_index_entry {
5313 struct sa_index_pair sa_pair[2];
5316 struct list_head next;
5319 /* Refer to SNIA SFF 8247 */
5320 struct sff_8247_a0 {
5321 u8 txid; /* transceiver id */
5324 /* compliance code */
5325 u8 eth_infi_cc3; /* ethernet, inifiband */
5329 #define FC_LL_VL BIT_7 /* very long */
5330 #define FC_LL_S BIT_6 /* Short */
5331 #define FC_LL_I BIT_5 /* Intermidiate*/
5332 #define FC_LL_L BIT_4 /* Long */
5333 #define FC_LL_M BIT_3 /* Medium */
5334 #define FC_LL_SA BIT_2 /* ShortWave laser */
5335 #define FC_LL_LC BIT_1 /* LongWave laser */
5336 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */
5339 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
5340 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */
5341 #define FC_TEC_SL BIT_5 /* short wave with OFC */
5342 #define FC_TEC_LL BIT_4 /* Longwave Laser */
5343 #define FC_TEC_ACT BIT_3 /* Active cable */
5344 #define FC_TEC_PAS BIT_2 /* Passive cable */
5346 /* Transmission Media */
5347 #define FC_MED_TW BIT_7 /* Twin Ax */
5348 #define FC_MED_TP BIT_6 /* Twited Pair */
5349 #define FC_MED_MI BIT_5 /* Min Coax */
5350 #define FC_MED_TV BIT_4 /* Video Coax */
5351 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
5352 #define FC_MED_M5 BIT_2 /* Multimode, 50um */
5353 #define FC_MED_SM BIT_0 /* Single Mode */
5355 /* speed FC_SP_12: 12*100M = 1200 MB/s */
5356 #define FC_SP_12 BIT_7
5357 #define FC_SP_8 BIT_6
5358 #define FC_SP_16 BIT_5
5359 #define FC_SP_4 BIT_4
5360 #define FC_SP_32 BIT_3
5361 #define FC_SP_2 BIT_2
5362 #define FC_SP_1 BIT_0
5367 u8 length_km; /* offset 14/eh */
5373 #define SFF_VEN_NAME_LEN 16
5374 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
5377 #define SFF_PART_NAME_LEN 16
5378 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
5383 u8 options[2]; /* offset 64 */
5392 u8 vendor_specific[32];
5396 /* BPM -- Buffer Plus Management support. */
5397 #define IS_BPM_CAPABLE(ha) \
5398 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
5399 IS_QLA27XX(ha) || IS_QLA28XX(ha))
5400 #define IS_BPM_RANGE_CAPABLE(ha) \
5401 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5402 #define IS_BPM_ENABLED(vha) \
5403 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
5405 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
5407 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
5408 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
5410 #define SAVE_TOPO(_ha) { \
5411 if (_ha->current_topology) \
5412 _ha->prev_topology = _ha->current_topology; \
5415 #define N2N_TOPO(ha) \
5416 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
5417 ha->current_topology == ISP_CFG_N || \
5418 !ha->current_topology)
5420 #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */
5422 #define NVME_TYPE(fcport) \
5423 (fcport->fc4_type & FS_FC4TYPE_NVME) \
5425 #define FCP_TYPE(fcport) \
5426 (fcport->fc4_type & FS_FC4TYPE_FCP) \
5428 #define NVME_ONLY_TARGET(fcport) \
5429 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
5431 #define NVME_FCP_TARGET(fcport) \
5432 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
5434 #define NVME_PRIORITY(ha, fcport) \
5435 (NVME_FCP_TARGET(fcport) && \
5436 (ha->fc4_type_priority == FC4_PRIORITY_NVME))
5438 #define NVME_TARGET(ha, fcport) \
5439 (fcport->do_prli_nvme || \
5440 NVME_ONLY_TARGET(fcport)) \
5442 #define PRLI_PHASE(_cls) \
5443 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
5445 enum ql_vnd_host_stat_action {
5451 struct ql_vnd_mng_host_stats_param {
5453 enum ql_vnd_host_stat_action action;
5456 struct ql_vnd_mng_host_stats_resp {
5460 struct ql_vnd_stats_param {
5464 struct ql_vnd_tgt_stats_param {
5469 enum ql_vnd_host_port_action {
5474 struct ql_vnd_mng_host_port_param {
5475 enum ql_vnd_host_port_action action;
5478 struct ql_vnd_mng_host_port_resp {
5482 struct ql_vnd_stat_entry {
5483 u32 stat_type; /* Failure type */
5484 u32 tgt_num; /* Target Num */
5485 u64 cnt; /* Counter value */
5488 struct ql_vnd_stats {
5489 u64 entry_count; /* Num of entries */
5491 struct ql_vnd_stat_entry entry[]; /* Place holder of entries */
5494 struct ql_vnd_host_stats_resp {
5496 struct ql_vnd_stats stats;
5499 struct ql_vnd_tgt_stats_resp {
5501 struct ql_vnd_stats stats;
5504 #include "qla_target.h"
5505 #include "qla_gbl.h"
5506 #include "qla_dbg.h"
5507 #include "qla_inline.h"
5509 #define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \
5510 _fcport->disc_state == DSC_DELETED)
5512 #define DBG_FCPORT_PRFMT(_fp, _fmt, _args...) \
5513 "%s: %8phC: " _fmt " (state=%d disc_state=%d scan_state=%d loopid=0x%x deleted=%d flags=0x%x)\n", \
5514 __func__, _fp->port_name, ##_args, atomic_read(&_fp->state), \
5515 _fp->disc_state, _fp->scan_state, _fp->loop_id, _fp->deleted, \
5518 #define TMF_NOT_READY(_fcport) \
5519 (!_fcport || IS_SESSION_DELETED(_fcport) || atomic_read(&_fcport->state) != FCS_ONLINE || \
5520 !_fcport->vha->hw->flags.fw_started)