2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28 #include <linux/btree.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport_fc.h>
35 #include <scsi/scsi_bsg_fc.h>
40 #define QLA2XXX_DRIVER_NAME "qla2xxx"
41 #define QLA2XXX_APIDEV "ql2xapidev"
42 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
45 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
46 * but that's fine as we don't look at the last 24 ones for
49 #define MAILBOX_REGISTER_COUNT_2100 8
50 #define MAILBOX_REGISTER_COUNT_2200 24
51 #define MAILBOX_REGISTER_COUNT 32
53 #define QLA2200A_RISC_ROM_VER 4
57 #include "qla_settings.h"
59 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
62 * Data bit definitions
80 #define BIT_16 0x10000
81 #define BIT_17 0x20000
82 #define BIT_18 0x40000
83 #define BIT_19 0x80000
84 #define BIT_20 0x100000
85 #define BIT_21 0x200000
86 #define BIT_22 0x400000
87 #define BIT_23 0x800000
88 #define BIT_24 0x1000000
89 #define BIT_25 0x2000000
90 #define BIT_26 0x4000000
91 #define BIT_27 0x8000000
92 #define BIT_28 0x10000000
93 #define BIT_29 0x20000000
94 #define BIT_30 0x40000000
95 #define BIT_31 0x80000000
97 #define LSB(x) ((uint8_t)(x))
98 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
100 #define LSW(x) ((uint16_t)(x))
101 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
103 #define LSD(x) ((uint32_t)((uint64_t)(x)))
104 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
106 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
112 #define RD_REG_BYTE(addr) readb(addr)
113 #define RD_REG_WORD(addr) readw(addr)
114 #define RD_REG_DWORD(addr) readl(addr)
115 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
116 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
117 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
118 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
119 #define WRT_REG_WORD(addr, data) writew(data,addr)
120 #define WRT_REG_DWORD(addr, data) writel(data,addr)
123 * ISP83XX specific remote register addresses
125 #define QLA83XX_LED_PORT0 0x00201320
126 #define QLA83XX_LED_PORT1 0x00201328
127 #define QLA83XX_IDC_DEV_STATE 0x22102384
128 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
129 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
130 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
131 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
132 #define QLA83XX_IDC_CONTROL 0x22102390
133 #define QLA83XX_IDC_AUDIT 0x22102394
134 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
135 #define QLA83XX_DRIVER_LOCKID 0x22102104
136 #define QLA83XX_DRIVER_LOCK 0x8111c028
137 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
138 #define QLA83XX_FLASH_LOCKID 0x22102100
139 #define QLA83XX_FLASH_LOCK 0x8111c010
140 #define QLA83XX_FLASH_UNLOCK 0x8111c014
141 #define QLA83XX_DEV_PARTINFO1 0x221023e0
142 #define QLA83XX_DEV_PARTINFO2 0x221023e4
143 #define QLA83XX_FW_HEARTBEAT 0x221020b0
144 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
145 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
147 /* 83XX: Macros defining 8200 AEN Reason codes */
148 #define IDC_DEVICE_STATE_CHANGE BIT_0
149 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
150 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
151 #define IDC_HEARTBEAT_FAILURE BIT_3
153 /* 83XX: Macros defining 8200 AEN Error-levels */
154 #define ERR_LEVEL_NON_FATAL 0x1
155 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
156 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
158 /* 83XX: Macros for IDC Version */
159 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
160 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
162 /* 83XX: Macros for scheduling dpc tasks */
163 #define QLA83XX_NIC_CORE_RESET 0x1
164 #define QLA83XX_IDC_STATE_HANDLER 0x2
165 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
167 /* 83XX: Macros for defining IDC-Control bits */
168 #define QLA83XX_IDC_RESET_DISABLED BIT_0
169 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
171 /* 83XX: Macros for different timeouts */
172 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
173 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
174 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
176 /* 83XX: Macros for defining class in DEV-Partition Info register */
177 #define QLA83XX_CLASS_TYPE_NONE 0x0
178 #define QLA83XX_CLASS_TYPE_NIC 0x1
179 #define QLA83XX_CLASS_TYPE_FCOE 0x2
180 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
182 /* 83XX: Macros for IDC Lock-Recovery stages */
183 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
186 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
188 /* 83XX: Macros for IDC Audit type */
189 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
190 * dev-state change to NEED-RESET
193 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
194 * reset-recovery completion is
197 /* ISP2031: Values for laser on/off */
198 #define PORT_0_2031 0x00201340
199 #define PORT_1_2031 0x00201350
200 #define LASER_ON_2031 0x01800100
201 #define LASER_OFF_2031 0x01800180
204 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
207 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
208 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
211 * Fibre Channel device definitions.
213 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
214 #define MAX_FIBRE_DEVICES_2100 512
215 #define MAX_FIBRE_DEVICES_2400 2048
216 #define MAX_FIBRE_DEVICES_LOOP 128
217 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
218 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
219 #define MAX_FIBRE_LUNS 0xFFFF
220 #define MAX_HOST_COUNT 16
223 * Host adapter default definitions.
225 #define MAX_BUSES 1 /* We only have one bus today */
227 #define MAX_LUNS MAX_FIBRE_LUNS
228 #define MAX_CMDS_PER_LUN 255
231 * Fibre Channel device definitions.
233 #define SNS_LAST_LOOP_ID_2100 0xfe
234 #define SNS_LAST_LOOP_ID_2300 0x7ff
236 #define LAST_LOCAL_LOOP_ID 0x7d
237 #define SNS_FL_PORT 0x7e
238 #define FABRIC_CONTROLLER 0x7f
239 #define SIMPLE_NAME_SERVER 0x80
240 #define SNS_FIRST_LOOP_ID 0x81
241 #define MANAGEMENT_SERVER 0xfe
242 #define BROADCAST 0xff
245 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
246 * valid range of an N-PORT id is 0 through 0x7ef.
248 #define NPH_LAST_HANDLE 0x7ef
249 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
250 #define NPH_SNS 0x7fc /* FFFFFC */
251 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
252 #define NPH_F_PORT 0x7fe /* FFFFFE */
253 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
255 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
257 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
260 struct name_list_extended {
261 struct get_name_list_extended *l;
263 struct list_head fcports; /* protect by sess_list */
268 * Timeout timer counts in seconds
270 #define PORT_RETRY_TIME 1
271 #define LOOP_DOWN_TIMEOUT 60
272 #define LOOP_DOWN_TIME 255 /* 240 */
273 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
275 #define DEFAULT_OUTSTANDING_COMMANDS 4096
276 #define MIN_OUTSTANDING_COMMANDS 128
278 /* ISP request and response entry counts (37-65535) */
279 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
280 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
281 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
282 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
283 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
284 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
285 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
286 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
287 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
288 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
289 #define FW_DEF_EXCHANGES_CNT 2048
298 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
299 uint32_t request_sense_length;
300 uint32_t fw_sense_length;
301 uint8_t *request_sense_ptr;
306 * SRB flag definitions
308 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
309 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
310 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
311 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
312 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
314 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
315 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
317 struct els_logo_payload {
322 uint8_t wwpn[WWN_SIZE];
343 #define SRB_LOGIN_RETRIED BIT_0
344 #define SRB_LOGIN_COND_PLOGI BIT_1
345 #define SRB_LOGIN_SKIP_PRLI BIT_2
350 #define ELS_DCMD_TIMEOUT 20
351 #define ELS_DCMD_LOGO 0x5
354 struct completion comp;
355 struct els_logo_payload *els_logo_pyld;
356 dma_addr_t els_logo_pyld_dma;
360 * Values for flags field below are as
361 * defined in tsk_mgmt_entry struct
362 * for control_flags field in qla_fw.h.
367 struct completion comp;
371 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
372 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
373 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
374 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
375 #define FXDISC_TIMEOUT 20
381 dma_addr_t req_dma_handle;
382 dma_addr_t rsp_dma_handle;
384 __le32 adapter_id_hi;
385 __le16 req_func_type;
387 __le32 req_data_extra;
391 struct completion fxiocb_comp;
398 struct completion comp;
401 #define MAX_IOCB_MB_REG 28
402 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
404 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
405 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
407 dma_addr_t out_dma, in_dma;
408 struct completion comp;
412 struct imm_ntfy_from_isp *ntfy;
416 struct timer_list timer;
417 void (*timeout)(void *);
420 /* Values for srb_ctx type */
421 #define SRB_LOGIN_CMD 1
422 #define SRB_LOGOUT_CMD 2
423 #define SRB_ELS_CMD_RPT 3
424 #define SRB_ELS_CMD_HST 4
426 #define SRB_ADISC_CMD 6
428 #define SRB_SCSI_CMD 8
429 #define SRB_BIDI_CMD 9
430 #define SRB_FXIOCB_DCMD 10
431 #define SRB_FXIOCB_BCMD 11
432 #define SRB_ABT_CMD 12
433 #define SRB_ELS_DCMD 13
434 #define SRB_MB_IOCB 14
435 #define SRB_CT_PTHRU_CMD 15
436 #define SRB_NACK_PLOGI 16
437 #define SRB_NACK_PRLI 17
438 #define SRB_NACK_LOGO 18
447 * Do not move cmd_type field, it needs to
448 * line up with qla_tgt_cmd->cmd_type
453 struct fc_port *fcport;
454 struct scsi_qla_host *vha;
460 struct qla_qpair *qpair;
461 u32 gen1; /* scratch */
462 u32 gen2; /* scratch */
464 struct srb_iocb iocb_cmd;
465 struct bsg_job *bsg_job;
468 void (*done)(void *, int);
469 void (*free)(void *);
472 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
473 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
474 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
476 #define GET_CMD_SENSE_LEN(sp) \
477 (sp->u.scmd.request_sense_length)
478 #define SET_CMD_SENSE_LEN(sp, len) \
479 (sp->u.scmd.request_sense_length = len)
480 #define GET_CMD_SENSE_PTR(sp) \
481 (sp->u.scmd.request_sense_ptr)
482 #define SET_CMD_SENSE_PTR(sp, ptr) \
483 (sp->u.scmd.request_sense_ptr = ptr)
484 #define GET_FW_SENSE_LEN(sp) \
485 (sp->u.scmd.fw_sense_length)
486 #define SET_FW_SENSE_LEN(sp, len) \
487 (sp->u.scmd.fw_sense_length = len)
495 uint32_t transfer_size;
496 uint32_t iteration_count;
500 * ISP I/O Register Set structure definitions.
502 struct device_reg_2xxx {
503 uint16_t flash_address; /* Flash BIOS address */
504 uint16_t flash_data; /* Flash BIOS data */
505 uint16_t unused_1[1]; /* Gap */
506 uint16_t ctrl_status; /* Control/Status */
507 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
508 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
509 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
511 uint16_t ictrl; /* Interrupt control */
512 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
513 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
515 uint16_t istatus; /* Interrupt status */
516 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
518 uint16_t semaphore; /* Semaphore */
519 uint16_t nvram; /* NVRAM register. */
520 #define NVR_DESELECT 0
521 #define NVR_BUSY BIT_15
522 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
523 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
524 #define NVR_DATA_IN BIT_3
525 #define NVR_DATA_OUT BIT_2
526 #define NVR_SELECT BIT_1
527 #define NVR_CLOCK BIT_0
529 #define NVR_WAIT_CNT 20000
541 uint16_t unused_2[59]; /* Gap */
542 } __attribute__((packed)) isp2100;
545 uint16_t req_q_in; /* In-Pointer */
546 uint16_t req_q_out; /* Out-Pointer */
548 uint16_t rsp_q_in; /* In-Pointer */
549 uint16_t rsp_q_out; /* Out-Pointer */
551 /* RISC to Host Status */
552 uint32_t host_status;
553 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
554 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
556 /* Host to Host Semaphore */
557 uint16_t host_semaphore;
558 uint16_t unused_3[17]; /* Gap */
592 uint16_t unused_4[10]; /* Gap */
593 } __attribute__((packed)) isp2300;
596 uint16_t fpm_diag_config;
597 uint16_t unused_5[0x4]; /* Gap */
599 uint16_t unused_5_1; /* Gap */
600 uint16_t pcr; /* Processor Control Register. */
601 uint16_t unused_6[0x5]; /* Gap */
602 uint16_t mctr; /* Memory Configuration and Timing. */
603 uint16_t unused_7[0x3]; /* Gap */
604 uint16_t fb_cmd_2100; /* Unused on 23XX */
605 uint16_t unused_8[0x3]; /* Gap */
606 uint16_t hccr; /* Host command & control register. */
607 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
608 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
610 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
611 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
612 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
613 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
614 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
615 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
616 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
617 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
619 uint16_t unused_9[5]; /* Gap */
620 uint16_t gpiod; /* GPIO Data register. */
621 uint16_t gpioe; /* GPIO Enable register. */
622 #define GPIO_LED_MASK 0x00C0
623 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
624 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
625 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
626 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
627 #define GPIO_LED_ALL_OFF 0x0000
628 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
629 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
633 uint16_t unused_10[8]; /* Gap */
649 uint16_t mailbox23; /* Also probe reg. */
650 } __attribute__((packed)) isp2200;
654 struct device_reg_25xxmq {
664 struct device_reg_fx00 {
665 uint32_t mailbox0; /* 00 */
666 uint32_t mailbox1; /* 04 */
667 uint32_t mailbox2; /* 08 */
668 uint32_t mailbox3; /* 0C */
669 uint32_t mailbox4; /* 10 */
670 uint32_t mailbox5; /* 14 */
671 uint32_t mailbox6; /* 18 */
672 uint32_t mailbox7; /* 1C */
673 uint32_t mailbox8; /* 20 */
674 uint32_t mailbox9; /* 24 */
675 uint32_t mailbox10; /* 28 */
697 uint32_t aenmailbox0;
698 uint32_t aenmailbox1;
699 uint32_t aenmailbox2;
700 uint32_t aenmailbox3;
701 uint32_t aenmailbox4;
702 uint32_t aenmailbox5;
703 uint32_t aenmailbox6;
704 uint32_t aenmailbox7;
706 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
707 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
708 /* Response Queue. */
709 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
710 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
711 /* Init values shadowed on FW Up Event */
712 uint32_t initval0; /* B0 */
713 uint32_t initval1; /* B4 */
714 uint32_t initval2; /* B8 */
715 uint32_t initval3; /* BC */
716 uint32_t initval4; /* C0 */
717 uint32_t initval5; /* C4 */
718 uint32_t initval6; /* C8 */
719 uint32_t initval7; /* CC */
720 uint32_t fwheartbeat; /* D0 */
721 uint32_t pseudoaen; /* D4 */
727 struct device_reg_2xxx isp;
728 struct device_reg_24xx isp24;
729 struct device_reg_25xxmq isp25mq;
730 struct device_reg_82xx isp82;
731 struct device_reg_fx00 ispfx00;
732 } __iomem device_reg_t;
734 #define ISP_REQ_Q_IN(ha, reg) \
735 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
736 &(reg)->u.isp2100.mailbox4 : \
737 &(reg)->u.isp2300.req_q_in)
738 #define ISP_REQ_Q_OUT(ha, reg) \
739 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
740 &(reg)->u.isp2100.mailbox4 : \
741 &(reg)->u.isp2300.req_q_out)
742 #define ISP_RSP_Q_IN(ha, reg) \
743 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
744 &(reg)->u.isp2100.mailbox5 : \
745 &(reg)->u.isp2300.rsp_q_in)
746 #define ISP_RSP_Q_OUT(ha, reg) \
747 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
748 &(reg)->u.isp2100.mailbox5 : \
749 &(reg)->u.isp2300.rsp_q_out)
751 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
752 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
754 #define MAILBOX_REG(ha, reg, num) \
755 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
757 &(reg)->u.isp2100.mailbox0 + (num) : \
758 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
759 &(reg)->u.isp2300.mailbox0 + (num))
760 #define RD_MAILBOX_REG(ha, reg, num) \
761 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
762 #define WRT_MAILBOX_REG(ha, reg, num, data) \
763 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
765 #define FB_CMD_REG(ha, reg) \
766 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
767 &(reg)->fb_cmd_2100 : \
768 &(reg)->u.isp2300.fb_cmd)
769 #define RD_FB_CMD_REG(ha, reg) \
770 RD_REG_WORD(FB_CMD_REG(ha, reg))
771 #define WRT_FB_CMD_REG(ha, reg, data) \
772 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
775 uint32_t out_mb; /* outbound from driver */
776 uint32_t in_mb; /* Incoming from RISC */
777 uint16_t mb[MAILBOX_REGISTER_COUNT];
782 #define MBX_DMA_IN BIT_0
783 #define MBX_DMA_OUT BIT_1
784 #define IOCTL_CMD BIT_2
788 uint32_t out_mb; /* outbound from driver */
789 uint32_t in_mb; /* Incoming from RISC */
790 uint32_t mb[MAILBOX_REGISTER_COUNT];
795 #define MBX_DMA_IN BIT_0
796 #define MBX_DMA_OUT BIT_1
797 #define IOCTL_CMD BIT_2
801 #define MBX_TOV_SECONDS 30
804 * ISP product identification definitions in mailboxes after reset.
806 #define PROD_ID_1 0x4953
807 #define PROD_ID_2 0x0000
808 #define PROD_ID_2a 0x5020
809 #define PROD_ID_3 0x2020
812 * ISP mailbox Self-Test status codes
814 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
815 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
816 #define MBS_BUSY 4 /* Busy. */
819 * ISP mailbox command complete status codes
821 #define MBS_COMMAND_COMPLETE 0x4000
822 #define MBS_INVALID_COMMAND 0x4001
823 #define MBS_HOST_INTERFACE_ERROR 0x4002
824 #define MBS_TEST_FAILED 0x4003
825 #define MBS_COMMAND_ERROR 0x4005
826 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
827 #define MBS_PORT_ID_USED 0x4007
828 #define MBS_LOOP_ID_USED 0x4008
829 #define MBS_ALL_IDS_IN_USE 0x4009
830 #define MBS_NOT_LOGGED_IN 0x400A
831 #define MBS_LINK_DOWN_ERROR 0x400B
832 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
835 * ISP mailbox asynchronous event status codes
837 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
838 #define MBA_RESET 0x8001 /* Reset Detected. */
839 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
840 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
841 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
842 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
843 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
845 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
846 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
847 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
848 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
849 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
850 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
851 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
852 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
853 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
854 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
855 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
856 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
857 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
858 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
859 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
860 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
862 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
863 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
864 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
865 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
866 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
867 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
868 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
869 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
870 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
871 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
872 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
873 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
874 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
875 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
876 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
877 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
878 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
879 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
880 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
881 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
882 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
883 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
884 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
886 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
887 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
888 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
889 /* 83XX FCoE specific */
890 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
892 /* Interrupt type codes */
893 #define INTR_ROM_MB_SUCCESS 0x1
894 #define INTR_ROM_MB_FAILED 0x2
895 #define INTR_MB_SUCCESS 0x10
896 #define INTR_MB_FAILED 0x11
897 #define INTR_ASYNC_EVENT 0x12
898 #define INTR_RSP_QUE_UPDATE 0x13
899 #define INTR_RSP_QUE_UPDATE_83XX 0x14
900 #define INTR_ATIO_QUE_UPDATE 0x1C
901 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
903 /* ISP mailbox loopback echo diagnostic error code */
904 #define MBS_LB_RESET 0x17
906 * Firmware options 1, 2, 3.
908 #define FO1_AE_ON_LIPF8 BIT_0
909 #define FO1_AE_ALL_LIP_RESET BIT_1
910 #define FO1_CTIO_RETRY BIT_3
911 #define FO1_DISABLE_LIP_F7_SW BIT_4
912 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
913 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
914 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
915 #define FO1_SET_EMPHASIS_SWING BIT_8
916 #define FO1_AE_AUTO_BYPASS BIT_9
917 #define FO1_ENABLE_PURE_IOCB BIT_10
918 #define FO1_AE_PLOGI_RJT BIT_11
919 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
920 #define FO1_AE_QUEUE_FULL BIT_13
922 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
923 #define FO2_REV_LOOPBACK BIT_1
925 #define FO3_ENABLE_EMERG_IOCB BIT_0
926 #define FO3_AE_RND_ERROR BIT_1
928 /* 24XX additional firmware options */
929 #define ADD_FO_COUNT 3
930 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
931 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
933 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
935 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
938 * ISP mailbox commands
940 #define MBC_LOAD_RAM 1 /* Load RAM. */
941 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
942 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
943 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
944 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
945 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
946 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
947 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
948 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
949 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
950 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
951 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
952 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
953 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
954 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
955 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
956 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
957 #define MBC_RESET 0x18 /* Reset. */
958 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
959 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
960 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
961 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
962 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
963 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
964 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
965 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
966 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
967 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
968 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
969 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
970 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
971 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
972 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
973 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
974 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
975 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
976 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
977 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
978 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
979 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
980 #define MBC_DATA_RATE 0x5d /* Data Rate */
981 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
982 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
983 /* Initialization Procedure */
984 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
985 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
986 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
987 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
988 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
989 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
990 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
991 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
992 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
993 #define MBC_LIP_RESET 0x6c /* LIP reset. */
994 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
996 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
997 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
998 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
999 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1000 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1001 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1002 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1003 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1004 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1005 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1006 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
1009 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1010 * should be defined with MBC_MR_*
1012 #define MBC_MR_DRV_SHUTDOWN 0x6A
1015 * ISP24xx mailbox commands
1017 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1018 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1019 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1020 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1021 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1022 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1023 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1024 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1025 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1026 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1027 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1028 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1029 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1030 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1031 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1032 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1033 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1034 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1035 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1036 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1037 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1038 #define MBC_PORT_RESET 0x120 /* Port Reset */
1039 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1040 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1043 * ISP81xx mailbox commands
1045 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1048 * ISP8044 mailbox commands
1050 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1051 #define HCS_WRITE_SERDES 0x3
1052 #define HCS_READ_SERDES 0x4
1054 /* Firmware return data sizes */
1055 #define FCAL_MAP_SIZE 128
1057 /* Mailbox bit definitions for out_mb and in_mb */
1058 #define MBX_31 BIT_31
1059 #define MBX_30 BIT_30
1060 #define MBX_29 BIT_29
1061 #define MBX_28 BIT_28
1062 #define MBX_27 BIT_27
1063 #define MBX_26 BIT_26
1064 #define MBX_25 BIT_25
1065 #define MBX_24 BIT_24
1066 #define MBX_23 BIT_23
1067 #define MBX_22 BIT_22
1068 #define MBX_21 BIT_21
1069 #define MBX_20 BIT_20
1070 #define MBX_19 BIT_19
1071 #define MBX_18 BIT_18
1072 #define MBX_17 BIT_17
1073 #define MBX_16 BIT_16
1074 #define MBX_15 BIT_15
1075 #define MBX_14 BIT_14
1076 #define MBX_13 BIT_13
1077 #define MBX_12 BIT_12
1078 #define MBX_11 BIT_11
1079 #define MBX_10 BIT_10
1091 #define RNID_TYPE_SET_VERSION 0x9
1092 #define RNID_TYPE_ASIC_TEMP 0xC
1095 * Firmware state codes from get firmware state mailbox command
1097 #define FSTATE_CONFIG_WAIT 0
1098 #define FSTATE_WAIT_AL_PA 1
1099 #define FSTATE_WAIT_LOGIN 2
1100 #define FSTATE_READY 3
1101 #define FSTATE_LOSS_OF_SYNC 4
1102 #define FSTATE_ERROR 5
1103 #define FSTATE_REINIT 6
1104 #define FSTATE_NON_PART 7
1106 #define FSTATE_CONFIG_CORRECT 0
1107 #define FSTATE_P2P_RCV_LIP 1
1108 #define FSTATE_P2P_CHOOSE_LOOP 2
1109 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1110 #define FSTATE_FATAL_ERROR 4
1111 #define FSTATE_LOOP_BACK_CONN 5
1113 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1114 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1115 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1116 #define QLA27XX_PRIMARY_IMAGE 1
1117 #define QLA27XX_SECONDARY_IMAGE 2
1120 * Port Database structure definition
1121 * Little endian except where noted.
1123 #define PORT_DATABASE_SIZE 128 /* bytes */
1127 uint8_t master_state;
1128 uint8_t slave_state;
1129 uint8_t reserved[2];
1130 uint8_t hard_address;
1133 uint8_t node_name[WWN_SIZE];
1134 uint8_t port_name[WWN_SIZE];
1135 uint16_t execution_throttle;
1136 uint16_t execution_count;
1137 uint8_t reset_count;
1139 uint16_t resource_allocation;
1140 uint16_t current_allocation;
1141 uint16_t queue_head;
1142 uint16_t queue_tail;
1143 uint16_t transmit_execution_list_next;
1144 uint16_t transmit_execution_list_previous;
1145 uint16_t common_features;
1146 uint16_t total_concurrent_sequences;
1147 uint16_t RO_by_information_category;
1150 uint16_t receive_data_size;
1151 uint16_t concurrent_sequences;
1152 uint16_t open_sequences_per_exchange;
1153 uint16_t lun_abort_flags;
1154 uint16_t lun_stop_flags;
1155 uint16_t stop_queue_head;
1156 uint16_t stop_queue_tail;
1157 uint16_t port_retry_timer;
1158 uint16_t next_sequence_id;
1159 uint16_t frame_count;
1160 uint16_t PRLI_payload_length;
1161 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1162 /* Bits 15-0 of word 0 */
1163 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1164 /* Bits 15-0 of word 3 */
1166 uint16_t extended_lun_info_list_pointer;
1167 uint16_t extended_lun_stop_list_pointer;
1171 * Port database slave/master states
1173 #define PD_STATE_DISCOVERY 0
1174 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1175 #define PD_STATE_PORT_LOGIN 2
1176 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1177 #define PD_STATE_PROCESS_LOGIN 4
1178 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1179 #define PD_STATE_PORT_LOGGED_IN 6
1180 #define PD_STATE_PORT_UNAVAILABLE 7
1181 #define PD_STATE_PROCESS_LOGOUT 8
1182 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1183 #define PD_STATE_PORT_LOGOUT 10
1184 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1187 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1188 #define QLA_ZIO_DISABLED 0
1189 #define QLA_ZIO_DEFAULT_TIMER 2
1192 * ISP Initialization Control Block.
1193 * Little endian except where noted.
1195 #define ICB_VERSION 1
1201 * LSB BIT 0 = Enable Hard Loop Id
1202 * LSB BIT 1 = Enable Fairness
1203 * LSB BIT 2 = Enable Full-Duplex
1204 * LSB BIT 3 = Enable Fast Posting
1205 * LSB BIT 4 = Enable Target Mode
1206 * LSB BIT 5 = Disable Initiator Mode
1207 * LSB BIT 6 = Enable ADISC
1208 * LSB BIT 7 = Enable Target Inquiry Data
1210 * MSB BIT 0 = Enable PDBC Notify
1211 * MSB BIT 1 = Non Participating LIP
1212 * MSB BIT 2 = Descending Loop ID Search
1213 * MSB BIT 3 = Acquire Loop ID in LIPA
1214 * MSB BIT 4 = Stop PortQ on Full Status
1215 * MSB BIT 5 = Full Login after LIP
1216 * MSB BIT 6 = Node Name Option
1217 * MSB BIT 7 = Ext IFWCB enable bit
1219 uint8_t firmware_options[2];
1221 uint16_t frame_payload_size;
1222 uint16_t max_iocb_allocation;
1223 uint16_t execution_throttle;
1224 uint8_t retry_count;
1225 uint8_t retry_delay; /* unused */
1226 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1227 uint16_t hard_address;
1228 uint8_t inquiry_data;
1229 uint8_t login_timeout;
1230 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1232 uint16_t request_q_outpointer;
1233 uint16_t response_q_inpointer;
1234 uint16_t request_q_length;
1235 uint16_t response_q_length;
1236 uint32_t request_q_address[2];
1237 uint32_t response_q_address[2];
1239 uint16_t lun_enables;
1240 uint8_t command_resource_count;
1241 uint8_t immediate_notify_resource_count;
1243 uint8_t reserved_2[2];
1246 * LSB BIT 0 = Timer Operation mode bit 0
1247 * LSB BIT 1 = Timer Operation mode bit 1
1248 * LSB BIT 2 = Timer Operation mode bit 2
1249 * LSB BIT 3 = Timer Operation mode bit 3
1250 * LSB BIT 4 = Init Config Mode bit 0
1251 * LSB BIT 5 = Init Config Mode bit 1
1252 * LSB BIT 6 = Init Config Mode bit 2
1253 * LSB BIT 7 = Enable Non part on LIHA failure
1255 * MSB BIT 0 = Enable class 2
1256 * MSB BIT 1 = Enable ACK0
1259 * MSB BIT 4 = FC Tape Enable
1260 * MSB BIT 5 = Enable FC Confirm
1261 * MSB BIT 6 = Enable command queuing in target mode
1262 * MSB BIT 7 = No Logo On Link Down
1264 uint8_t add_firmware_options[2];
1266 uint8_t response_accumulation_timer;
1267 uint8_t interrupt_delay_timer;
1270 * LSB BIT 0 = Enable Read xfr_rdy
1271 * LSB BIT 1 = Soft ID only
1274 * LSB BIT 4 = FCP RSP Payload [0]
1275 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1276 * LSB BIT 6 = Enable Out-of-Order frame handling
1277 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1279 * MSB BIT 0 = Sbus enable - 2300
1283 * MSB BIT 4 = LED mode
1284 * MSB BIT 5 = enable 50 ohm termination
1285 * MSB BIT 6 = Data Rate (2300 only)
1286 * MSB BIT 7 = Data Rate (2300 only)
1288 uint8_t special_options[2];
1290 uint8_t reserved_3[26];
1294 * Get Link Status mailbox command return buffer.
1296 #define GLSO_SEND_RPS BIT_0
1297 #define GLSO_USE_DID BIT_3
1299 struct link_statistics {
1300 uint32_t link_fail_cnt;
1301 uint32_t loss_sync_cnt;
1302 uint32_t loss_sig_cnt;
1303 uint32_t prim_seq_err_cnt;
1304 uint32_t inval_xmit_word_cnt;
1305 uint32_t inval_crc_cnt;
1307 uint32_t link_up_cnt;
1308 uint32_t link_down_loop_init_tmo;
1309 uint32_t link_down_los;
1310 uint32_t link_down_loss_rcv_clk;
1311 uint32_t reserved0[5];
1312 uint32_t port_cfg_chg;
1313 uint32_t reserved1[11];
1314 uint32_t rsp_q_full;
1315 uint32_t atio_q_full;
1317 uint32_t els_proto_err;
1321 uint32_t discarded_frames;
1322 uint32_t dropped_frames;
1325 uint32_t reserved4[4];
1327 uint32_t rcv_exfail;
1329 uint32_t seq_frm_miss;
1332 uint32_t nport_full;
1335 uint32_t fpm_recv_word_cnt_lo;
1336 uint32_t fpm_recv_word_cnt_hi;
1337 uint32_t fpm_disc_word_cnt_lo;
1338 uint32_t fpm_disc_word_cnt_hi;
1339 uint32_t fpm_xmit_word_cnt_lo;
1340 uint32_t fpm_xmit_word_cnt_hi;
1341 uint32_t reserved6[70];
1345 * NVRAM Command values.
1347 #define NV_START_BIT BIT_2
1348 #define NV_WRITE_OP (BIT_26+BIT_24)
1349 #define NV_READ_OP (BIT_26+BIT_25)
1350 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1351 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1352 #define NV_DELAY_COUNT 10
1355 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1362 uint8_t nvram_version;
1366 * NVRAM RISC parameter block
1368 uint8_t parameter_block_version;
1372 * LSB BIT 0 = Enable Hard Loop Id
1373 * LSB BIT 1 = Enable Fairness
1374 * LSB BIT 2 = Enable Full-Duplex
1375 * LSB BIT 3 = Enable Fast Posting
1376 * LSB BIT 4 = Enable Target Mode
1377 * LSB BIT 5 = Disable Initiator Mode
1378 * LSB BIT 6 = Enable ADISC
1379 * LSB BIT 7 = Enable Target Inquiry Data
1381 * MSB BIT 0 = Enable PDBC Notify
1382 * MSB BIT 1 = Non Participating LIP
1383 * MSB BIT 2 = Descending Loop ID Search
1384 * MSB BIT 3 = Acquire Loop ID in LIPA
1385 * MSB BIT 4 = Stop PortQ on Full Status
1386 * MSB BIT 5 = Full Login after LIP
1387 * MSB BIT 6 = Node Name Option
1388 * MSB BIT 7 = Ext IFWCB enable bit
1390 uint8_t firmware_options[2];
1392 uint16_t frame_payload_size;
1393 uint16_t max_iocb_allocation;
1394 uint16_t execution_throttle;
1395 uint8_t retry_count;
1396 uint8_t retry_delay; /* unused */
1397 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1398 uint16_t hard_address;
1399 uint8_t inquiry_data;
1400 uint8_t login_timeout;
1401 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1404 * LSB BIT 0 = Timer Operation mode bit 0
1405 * LSB BIT 1 = Timer Operation mode bit 1
1406 * LSB BIT 2 = Timer Operation mode bit 2
1407 * LSB BIT 3 = Timer Operation mode bit 3
1408 * LSB BIT 4 = Init Config Mode bit 0
1409 * LSB BIT 5 = Init Config Mode bit 1
1410 * LSB BIT 6 = Init Config Mode bit 2
1411 * LSB BIT 7 = Enable Non part on LIHA failure
1413 * MSB BIT 0 = Enable class 2
1414 * MSB BIT 1 = Enable ACK0
1417 * MSB BIT 4 = FC Tape Enable
1418 * MSB BIT 5 = Enable FC Confirm
1419 * MSB BIT 6 = Enable command queuing in target mode
1420 * MSB BIT 7 = No Logo On Link Down
1422 uint8_t add_firmware_options[2];
1424 uint8_t response_accumulation_timer;
1425 uint8_t interrupt_delay_timer;
1428 * LSB BIT 0 = Enable Read xfr_rdy
1429 * LSB BIT 1 = Soft ID only
1432 * LSB BIT 4 = FCP RSP Payload [0]
1433 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1434 * LSB BIT 6 = Enable Out-of-Order frame handling
1435 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1437 * MSB BIT 0 = Sbus enable - 2300
1441 * MSB BIT 4 = LED mode
1442 * MSB BIT 5 = enable 50 ohm termination
1443 * MSB BIT 6 = Data Rate (2300 only)
1444 * MSB BIT 7 = Data Rate (2300 only)
1446 uint8_t special_options[2];
1448 /* Reserved for expanded RISC parameter block */
1449 uint8_t reserved_2[22];
1452 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1453 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1454 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1455 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1456 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1457 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1458 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1459 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1461 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1462 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1463 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1464 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1465 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1466 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1467 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1468 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1470 * LSB BIT 0 = Output Swing 1G bit 0
1471 * LSB BIT 1 = Output Swing 1G bit 1
1472 * LSB BIT 2 = Output Swing 1G bit 2
1473 * LSB BIT 3 = Output Emphasis 1G bit 0
1474 * LSB BIT 4 = Output Emphasis 1G bit 1
1475 * LSB BIT 5 = Output Swing 2G bit 0
1476 * LSB BIT 6 = Output Swing 2G bit 1
1477 * LSB BIT 7 = Output Swing 2G bit 2
1479 * MSB BIT 0 = Output Emphasis 2G bit 0
1480 * MSB BIT 1 = Output Emphasis 2G bit 1
1481 * MSB BIT 2 = Output Enable
1488 uint8_t seriallink_options[4];
1491 * NVRAM host parameter block
1493 * LSB BIT 0 = Enable spinup delay
1494 * LSB BIT 1 = Disable BIOS
1495 * LSB BIT 2 = Enable Memory Map BIOS
1496 * LSB BIT 3 = Enable Selectable Boot
1497 * LSB BIT 4 = Disable RISC code load
1498 * LSB BIT 5 = Set cache line size 1
1499 * LSB BIT 6 = PCI Parity Disable
1500 * LSB BIT 7 = Enable extended logging
1502 * MSB BIT 0 = Enable 64bit addressing
1503 * MSB BIT 1 = Enable lip reset
1504 * MSB BIT 2 = Enable lip full login
1505 * MSB BIT 3 = Enable target reset
1506 * MSB BIT 4 = Enable database storage
1507 * MSB BIT 5 = Enable cache flush read
1508 * MSB BIT 6 = Enable database load
1509 * MSB BIT 7 = Enable alternate WWN
1513 uint8_t boot_node_name[WWN_SIZE];
1514 uint8_t boot_lun_number;
1515 uint8_t reset_delay;
1516 uint8_t port_down_retry_count;
1517 uint8_t boot_id_number;
1518 uint16_t max_luns_per_target;
1519 uint8_t fcode_boot_port_name[WWN_SIZE];
1520 uint8_t alternate_port_name[WWN_SIZE];
1521 uint8_t alternate_node_name[WWN_SIZE];
1524 * BIT 0 = Selective Login
1525 * BIT 1 = Alt-Boot Enable
1527 * BIT 3 = Boot Order List
1529 * BIT 5 = Selective LUN
1533 uint8_t efi_parameters;
1535 uint8_t link_down_timeout;
1537 uint8_t adapter_id[16];
1539 uint8_t alt1_boot_node_name[WWN_SIZE];
1540 uint16_t alt1_boot_lun_number;
1541 uint8_t alt2_boot_node_name[WWN_SIZE];
1542 uint16_t alt2_boot_lun_number;
1543 uint8_t alt3_boot_node_name[WWN_SIZE];
1544 uint16_t alt3_boot_lun_number;
1545 uint8_t alt4_boot_node_name[WWN_SIZE];
1546 uint16_t alt4_boot_lun_number;
1547 uint8_t alt5_boot_node_name[WWN_SIZE];
1548 uint16_t alt5_boot_lun_number;
1549 uint8_t alt6_boot_node_name[WWN_SIZE];
1550 uint16_t alt6_boot_lun_number;
1551 uint8_t alt7_boot_node_name[WWN_SIZE];
1552 uint16_t alt7_boot_lun_number;
1554 uint8_t reserved_3[2];
1556 /* Offset 200-215 : Model Number */
1557 uint8_t model_number[16];
1559 /* OEM related items */
1560 uint8_t oem_specific[16];
1563 * NVRAM Adapter Features offset 232-239
1565 * LSB BIT 0 = External GBIC
1566 * LSB BIT 1 = Risc RAM parity
1567 * LSB BIT 2 = Buffer Plus Module
1568 * LSB BIT 3 = Multi Chip Adapter
1569 * LSB BIT 4 = Internal connector
1583 uint8_t adapter_features[2];
1585 uint8_t reserved_4[16];
1587 /* Subsystem vendor ID for ISP2200 */
1588 uint16_t subsystem_vendor_id_2200;
1590 /* Subsystem device ID for ISP2200 */
1591 uint16_t subsystem_device_id_2200;
1598 * ISP queue - response queue entry definition.
1601 uint8_t entry_type; /* Entry type. */
1602 uint8_t entry_count; /* Entry count. */
1603 uint8_t sys_define; /* System defined. */
1604 uint8_t entry_status; /* Entry Status. */
1605 uint32_t handle; /* System defined handle */
1608 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1612 * ISP queue - ATIO queue entry definition.
1615 uint8_t entry_type; /* Entry type. */
1616 uint8_t entry_count; /* Entry count. */
1617 __le16 attr_n_length;
1620 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1631 #define SET_TARGET_ID(ha, to, from) \
1633 if (HAS_EXTENDED_IDS(ha)) \
1634 to.extended = cpu_to_le16(from); \
1636 to.id.standard = (uint8_t)from; \
1640 * ISP queue - command entry structure definition.
1642 #define COMMAND_TYPE 0x11 /* Command entry */
1644 uint8_t entry_type; /* Entry type. */
1645 uint8_t entry_count; /* Entry count. */
1646 uint8_t sys_define; /* System defined. */
1647 uint8_t entry_status; /* Entry Status. */
1648 uint32_t handle; /* System handle. */
1649 target_id_t target; /* SCSI ID */
1650 uint16_t lun; /* SCSI LUN */
1651 uint16_t control_flags; /* Control flags. */
1652 #define CF_WRITE BIT_6
1653 #define CF_READ BIT_5
1654 #define CF_SIMPLE_TAG BIT_3
1655 #define CF_ORDERED_TAG BIT_2
1656 #define CF_HEAD_TAG BIT_1
1657 uint16_t reserved_1;
1658 uint16_t timeout; /* Command timeout. */
1659 uint16_t dseg_count; /* Data segment count. */
1660 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1661 uint32_t byte_count; /* Total byte count. */
1662 uint32_t dseg_0_address; /* Data segment 0 address. */
1663 uint32_t dseg_0_length; /* Data segment 0 length. */
1664 uint32_t dseg_1_address; /* Data segment 1 address. */
1665 uint32_t dseg_1_length; /* Data segment 1 length. */
1666 uint32_t dseg_2_address; /* Data segment 2 address. */
1667 uint32_t dseg_2_length; /* Data segment 2 length. */
1671 * ISP queue - 64-Bit addressing, command entry structure definition.
1673 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1675 uint8_t entry_type; /* Entry type. */
1676 uint8_t entry_count; /* Entry count. */
1677 uint8_t sys_define; /* System defined. */
1678 uint8_t entry_status; /* Entry Status. */
1679 uint32_t handle; /* System handle. */
1680 target_id_t target; /* SCSI ID */
1681 uint16_t lun; /* SCSI LUN */
1682 uint16_t control_flags; /* Control flags. */
1683 uint16_t reserved_1;
1684 uint16_t timeout; /* Command timeout. */
1685 uint16_t dseg_count; /* Data segment count. */
1686 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1687 uint32_t byte_count; /* Total byte count. */
1688 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1689 uint32_t dseg_0_length; /* Data segment 0 length. */
1690 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1691 uint32_t dseg_1_length; /* Data segment 1 length. */
1692 } cmd_a64_entry_t, request_t;
1695 * ISP queue - continuation entry structure definition.
1697 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1699 uint8_t entry_type; /* Entry type. */
1700 uint8_t entry_count; /* Entry count. */
1701 uint8_t sys_define; /* System defined. */
1702 uint8_t entry_status; /* Entry Status. */
1704 uint32_t dseg_0_address; /* Data segment 0 address. */
1705 uint32_t dseg_0_length; /* Data segment 0 length. */
1706 uint32_t dseg_1_address; /* Data segment 1 address. */
1707 uint32_t dseg_1_length; /* Data segment 1 length. */
1708 uint32_t dseg_2_address; /* Data segment 2 address. */
1709 uint32_t dseg_2_length; /* Data segment 2 length. */
1710 uint32_t dseg_3_address; /* Data segment 3 address. */
1711 uint32_t dseg_3_length; /* Data segment 3 length. */
1712 uint32_t dseg_4_address; /* Data segment 4 address. */
1713 uint32_t dseg_4_length; /* Data segment 4 length. */
1714 uint32_t dseg_5_address; /* Data segment 5 address. */
1715 uint32_t dseg_5_length; /* Data segment 5 length. */
1716 uint32_t dseg_6_address; /* Data segment 6 address. */
1717 uint32_t dseg_6_length; /* Data segment 6 length. */
1721 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1723 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1725 uint8_t entry_type; /* Entry type. */
1726 uint8_t entry_count; /* Entry count. */
1727 uint8_t sys_define; /* System defined. */
1728 uint8_t entry_status; /* Entry Status. */
1729 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1730 uint32_t dseg_0_length; /* Data segment 0 length. */
1731 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1732 uint32_t dseg_1_length; /* Data segment 1 length. */
1733 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1734 uint32_t dseg_2_length; /* Data segment 2 length. */
1735 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1736 uint32_t dseg_3_length; /* Data segment 3 length. */
1737 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1738 uint32_t dseg_4_length; /* Data segment 4 length. */
1741 #define PO_MODE_DIF_INSERT 0
1742 #define PO_MODE_DIF_REMOVE 1
1743 #define PO_MODE_DIF_PASS 2
1744 #define PO_MODE_DIF_REPLACE 3
1745 #define PO_MODE_DIF_TCP_CKSUM 6
1746 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1747 #define PO_DISABLE_GUARD_CHECK BIT_4
1748 #define PO_DISABLE_INCR_REF_TAG BIT_5
1749 #define PO_DIS_HEADER_MODE BIT_7
1750 #define PO_ENABLE_DIF_BUNDLING BIT_8
1751 #define PO_DIS_FRAME_MODE BIT_9
1752 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1753 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1755 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1756 #define PO_DIS_REF_TAG_REPL BIT_13
1757 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1758 #define PO_DIS_REF_TAG_VALD BIT_15
1761 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1763 struct crc_context {
1764 uint32_t handle; /* System handle. */
1767 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1768 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1769 __le16 guard_seed; /* Initial Guard Seed */
1770 __le16 prot_opts; /* Requested Data Protection Mode */
1771 __le16 blk_size; /* Data size in bytes */
1772 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1774 __le32 byte_count; /* Total byte count/ total data
1778 uint32_t reserved_1;
1779 uint16_t reserved_2;
1780 uint16_t reserved_3;
1781 uint32_t reserved_4;
1782 uint32_t data_address[2];
1783 uint32_t data_length;
1784 uint32_t reserved_5[2];
1785 uint32_t reserved_6;
1788 __le32 dif_byte_count; /* Total DIF byte
1790 uint16_t reserved_1;
1791 __le16 dseg_count; /* Data segment count */
1792 uint32_t reserved_2;
1793 uint32_t data_address[2];
1794 uint32_t data_length;
1795 uint32_t dif_address[2];
1796 uint32_t dif_length; /* Data segment 0
1801 struct fcp_cmnd fcp_cmnd;
1802 dma_addr_t crc_ctx_dma;
1803 /* List of DMA context transfers */
1804 struct list_head dsd_list;
1806 /* This structure should not exceed 512 bytes */
1809 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1810 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1813 * ISP queue - status entry structure definition.
1815 #define STATUS_TYPE 0x03 /* Status entry. */
1817 uint8_t entry_type; /* Entry type. */
1818 uint8_t entry_count; /* Entry count. */
1819 uint8_t sys_define; /* System defined. */
1820 uint8_t entry_status; /* Entry Status. */
1821 uint32_t handle; /* System handle. */
1822 uint16_t scsi_status; /* SCSI status. */
1823 uint16_t comp_status; /* Completion status. */
1824 uint16_t state_flags; /* State flags. */
1825 uint16_t status_flags; /* Status flags. */
1826 uint16_t rsp_info_len; /* Response Info Length. */
1827 uint16_t req_sense_length; /* Request sense data length. */
1828 uint32_t residual_length; /* Residual transfer length. */
1829 uint8_t rsp_info[8]; /* FCP response information. */
1830 uint8_t req_sense_data[32]; /* Request sense data. */
1834 * Status entry entry status
1836 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1837 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1838 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1839 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1840 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1841 #define RF_BUSY BIT_1 /* Busy */
1842 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1843 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1844 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1848 * Status entry SCSI status bit definitions.
1850 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1851 #define SS_RESIDUAL_UNDER BIT_11
1852 #define SS_RESIDUAL_OVER BIT_10
1853 #define SS_SENSE_LEN_VALID BIT_9
1854 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1855 #define SS_SCSI_STATUS_BYTE 0xff
1857 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1858 #define SS_BUSY_CONDITION BIT_3
1859 #define SS_CONDITION_MET BIT_2
1860 #define SS_CHECK_CONDITION BIT_1
1863 * Status entry completion status
1865 #define CS_COMPLETE 0x0 /* No errors */
1866 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1867 #define CS_DMA 0x2 /* A DMA direction error. */
1868 #define CS_TRANSPORT 0x3 /* Transport error. */
1869 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1870 #define CS_ABORTED 0x5 /* System aborted command. */
1871 #define CS_TIMEOUT 0x6 /* Timeout error. */
1872 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1873 #define CS_DIF_ERROR 0xC /* DIF error detected */
1875 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1876 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1877 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1878 /* (selection timeout) */
1879 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1880 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1881 #define CS_PORT_BUSY 0x2B /* Port Busy */
1882 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1883 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
1885 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1886 #define CS_UNKNOWN 0x81 /* Driver defined */
1887 #define CS_RETRY 0x82 /* Driver defined */
1888 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1890 #define CS_BIDIR_RD_OVERRUN 0x700
1891 #define CS_BIDIR_RD_WR_OVERRUN 0x707
1892 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1893 #define CS_BIDIR_RD_UNDERRUN 0x1500
1894 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1895 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1896 #define CS_BIDIR_DMA 0x200
1898 * Status entry status flags
1900 #define SF_ABTS_TERMINATED BIT_10
1901 #define SF_LOGOUT_SENT BIT_13
1904 * ISP queue - status continuation entry structure definition.
1906 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1908 uint8_t entry_type; /* Entry type. */
1909 uint8_t entry_count; /* Entry count. */
1910 uint8_t sys_define; /* System defined. */
1911 uint8_t entry_status; /* Entry Status. */
1912 uint8_t data[60]; /* data */
1916 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1917 * structure definition.
1919 #define STATUS_TYPE_21 0x21 /* Status entry. */
1921 uint8_t entry_type; /* Entry type. */
1922 uint8_t entry_count; /* Entry count. */
1923 uint8_t handle_count; /* Handle count. */
1924 uint8_t entry_status; /* Entry Status. */
1925 uint32_t handle[15]; /* System handles. */
1929 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1930 * structure definition.
1932 #define STATUS_TYPE_22 0x22 /* Status entry. */
1934 uint8_t entry_type; /* Entry type. */
1935 uint8_t entry_count; /* Entry count. */
1936 uint8_t handle_count; /* Handle count. */
1937 uint8_t entry_status; /* Entry Status. */
1938 uint16_t handle[30]; /* System handles. */
1942 * ISP queue - marker entry structure definition.
1944 #define MARKER_TYPE 0x04 /* Marker entry. */
1946 uint8_t entry_type; /* Entry type. */
1947 uint8_t entry_count; /* Entry count. */
1948 uint8_t handle_count; /* Handle count. */
1949 uint8_t entry_status; /* Entry Status. */
1950 uint32_t sys_define_2; /* System defined. */
1951 target_id_t target; /* SCSI ID */
1952 uint8_t modifier; /* Modifier (7-0). */
1953 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1954 #define MK_SYNC_ID 1 /* Synchronize ID */
1955 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1956 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1957 /* clear port changed, */
1958 /* use sequence number. */
1960 uint16_t sequence_number; /* Sequence number of event */
1961 uint16_t lun; /* SCSI LUN */
1962 uint8_t reserved_2[48];
1966 * ISP queue - Management Server entry structure definition.
1968 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1970 uint8_t entry_type; /* Entry type. */
1971 uint8_t entry_count; /* Entry count. */
1972 uint8_t handle_count; /* Handle count. */
1973 uint8_t entry_status; /* Entry Status. */
1974 uint32_t handle1; /* System handle. */
1975 target_id_t loop_id;
1977 uint16_t control_flags; /* Control flags. */
1980 uint16_t cmd_dsd_count;
1981 uint16_t total_dsd_count;
1987 uint32_t rsp_bytecount;
1988 uint32_t req_bytecount;
1989 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1990 uint32_t dseg_req_length; /* Data segment 0 length. */
1991 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1992 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1997 * ISP queue - Mailbox Command entry structure definition.
1999 #define MBX_IOCB_TYPE 0x39
2002 uint8_t entry_count;
2003 uint8_t sys_define1;
2004 /* Use sys_define1 for source type */
2005 #define SOURCE_SCSI 0x00
2006 #define SOURCE_IP 0x01
2007 #define SOURCE_VI 0x02
2008 #define SOURCE_SCTP 0x03
2009 #define SOURCE_MP 0x04
2010 #define SOURCE_MPIOCTL 0x05
2011 #define SOURCE_ASYNC_IOCB 0x07
2013 uint8_t entry_status;
2016 target_id_t loop_id;
2019 uint16_t state_flags;
2020 uint16_t status_flags;
2022 uint32_t sys_define2[2];
2032 uint32_t reserved_2[2];
2033 uint8_t node_name[WWN_SIZE];
2034 uint8_t port_name[WWN_SIZE];
2037 #ifndef IMMED_NOTIFY_TYPE
2038 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2040 * ISP queue - immediate notify entry structure definition.
2041 * This is sent by the ISP to the Target driver.
2042 * This IOCB would have report of events sent by the
2043 * initiator, that needs to be handled by the target
2044 * driver immediately.
2046 struct imm_ntfy_from_isp {
2047 uint8_t entry_type; /* Entry type. */
2048 uint8_t entry_count; /* Entry count. */
2049 uint8_t sys_define; /* System defined. */
2050 uint8_t entry_status; /* Entry Status. */
2053 uint32_t sys_define_2; /* System defined. */
2058 uint16_t status_modifier;
2060 uint16_t task_flags;
2063 uint32_t srr_rel_offs;
2065 #define SRR_IU_DATA_IN 0x1
2066 #define SRR_IU_DATA_OUT 0x5
2067 #define SRR_IU_STATUS 0x7
2069 uint8_t reserved_2[28];
2073 uint16_t nport_handle;
2074 uint16_t reserved_2;
2076 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2077 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2080 uint8_t status_subcode;
2082 uint32_t exchange_address;
2083 uint32_t srr_rel_offs;
2088 uint8_t node_name[8];
2089 } plogi; /* PLOGI/ADISC/PDISC */
2091 /* PRLI word 3 bit 0-15 */
2098 uint16_t nport_handle;
2102 uint8_t port_name[8];
2105 uint32_t reserved_5;
2110 uint16_t reserved_7;
2116 * ISP request and response queue entry sizes
2118 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2119 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2123 * 24 bit port ID type definition.
2133 #elif defined(__LITTLE_ENDIAN)
2138 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
2143 #define INVALID_PORT_ID 0xFFFFFF
2146 * Switch info gathering structure.
2150 uint8_t node_name[WWN_SIZE];
2151 uint8_t port_name[WWN_SIZE];
2152 uint8_t fabric_port_name[WWN_SIZE];
2158 #define FC4_TYPE_FCP_SCSI 0x08
2159 #define FC4_TYPE_OTHER 0x0
2160 #define FC4_TYPE_UNKNOWN 0xff
2162 /* mailbox command 4G & above */
2163 struct mbx_24xx_entry {
2165 uint8_t entry_count;
2166 uint8_t sys_define1;
2167 uint8_t entry_status;
2172 #define IOCB_SIZE 64
2175 * Fibre channel port type.
2186 enum qla_sess_deletion {
2187 QLA_SESS_DELETION_NONE = 0,
2188 QLA_SESS_DELETION_IN_PROGRESS,
2192 enum qlt_plogi_link_t {
2193 QLT_PLOGI_LINK_SAME_WWN,
2194 QLT_PLOGI_LINK_CONFLICT,
2198 struct qlt_plogi_ack_t {
2199 struct list_head list;
2200 struct imm_ntfy_from_isp iocb;
2206 struct ct_sns_desc {
2207 struct ct_sns_pkt *ct_sns;
2208 dma_addr_t ct_sns_dma;
2211 enum discovery_state {
2224 enum login_state { /* FW control Target side */
2225 DSC_LS_LLIOCB_SENT = 2,
2230 DSC_LS_PORT_UNAVAIL,
2231 DSC_LS_PRLO_PEND = 9,
2235 enum fcport_mgt_event {
2239 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */
2247 enum rscn_addr_format {
2255 * Fibre channel port structure.
2257 typedef struct fc_port {
2258 struct list_head list;
2259 struct scsi_qla_host *vha;
2261 uint8_t node_name[WWN_SIZE];
2262 uint8_t port_name[WWN_SIZE];
2265 uint16_t old_loop_id;
2267 unsigned int conf_compl_supported:1;
2268 unsigned int deleted:2;
2269 unsigned int local:1;
2270 unsigned int logout_on_delete:1;
2271 unsigned int logo_ack_needed:1;
2272 unsigned int keep_nport_handle:1;
2273 unsigned int send_els_logo:1;
2274 unsigned int login_pause:1;
2275 unsigned int login_succ:1;
2277 struct fc_port *conflict;
2278 unsigned char logout_completed;
2281 struct se_session *se_sess;
2282 struct kref sess_kref;
2283 struct qla_tgt *tgt;
2284 unsigned long expires;
2285 struct list_head del_list_entry;
2286 struct work_struct free_work;
2288 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2291 uint16_t old_tgt_id;
2295 uint8_t fabric_port_name[WWN_SIZE];
2298 fc_port_type_t port_type;
2305 struct fc_rport *rport, *drport;
2306 u32 supported_classes;
2311 unsigned long last_queue_full;
2312 unsigned long last_ramp_up;
2316 unsigned long retry_delay_timestamp;
2317 struct qla_tgt_sess *tgt_session;
2318 struct ct_sns_desc ct_desc;
2319 enum discovery_state disc_state;
2320 enum login_state fw_login_state;
2321 unsigned long plogi_nack_done_deadline;
2323 u32 login_gen, last_login_gen;
2324 u32 rscn_gen, last_rscn_gen;
2326 struct list_head gnl_entry;
2327 struct work_struct del_work;
2331 #define QLA_FCPORT_SCAN 1
2332 #define QLA_FCPORT_FOUND 2
2335 enum fcport_mgt_event event;
2340 u8 port_name[WWN_SIZE];
2347 * Fibre channel port/lun states.
2349 #define FCS_UNCONFIGURED 1
2350 #define FCS_DEVICE_DEAD 2
2351 #define FCS_DEVICE_LOST 3
2352 #define FCS_ONLINE 4
2354 static const char * const port_state_str[] = {
2365 #define FCF_FABRIC_DEVICE BIT_0
2366 #define FCF_LOGIN_NEEDED BIT_1
2367 #define FCF_FCP2_DEVICE BIT_2
2368 #define FCF_ASYNC_SENT BIT_3
2369 #define FCF_CONF_COMP_SUPPORTED BIT_4
2371 /* No loop ID flag. */
2372 #define FC_NO_LOOP_ID 0x1000
2377 * NOTE: All structures are big-endian in form.
2380 #define CT_REJECT_RESPONSE 0x8001
2381 #define CT_ACCEPT_RESPONSE 0x8002
2382 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2383 #define CT_REASON_CANNOT_PERFORM 0x09
2384 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2385 #define CT_EXPL_ALREADY_REGISTERED 0x10
2386 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2387 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2388 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2389 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2390 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2391 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2392 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2393 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2394 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2395 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2396 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2398 #define NS_N_PORT_TYPE 0x01
2399 #define NS_NL_PORT_TYPE 0x02
2400 #define NS_NX_PORT_TYPE 0x7F
2402 #define GA_NXT_CMD 0x100
2403 #define GA_NXT_REQ_SIZE (16 + 4)
2404 #define GA_NXT_RSP_SIZE (16 + 620)
2406 #define GID_PT_CMD 0x1A1
2407 #define GID_PT_REQ_SIZE (16 + 4)
2409 #define GPN_ID_CMD 0x112
2410 #define GPN_ID_REQ_SIZE (16 + 4)
2411 #define GPN_ID_RSP_SIZE (16 + 8)
2413 #define GNN_ID_CMD 0x113
2414 #define GNN_ID_REQ_SIZE (16 + 4)
2415 #define GNN_ID_RSP_SIZE (16 + 8)
2417 #define GFT_ID_CMD 0x117
2418 #define GFT_ID_REQ_SIZE (16 + 4)
2419 #define GFT_ID_RSP_SIZE (16 + 32)
2421 #define GID_PN_CMD 0x121
2422 #define GID_PN_REQ_SIZE (16 + 8)
2423 #define GID_PN_RSP_SIZE (16 + 4)
2425 #define RFT_ID_CMD 0x217
2426 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2427 #define RFT_ID_RSP_SIZE 16
2429 #define RFF_ID_CMD 0x21F
2430 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2431 #define RFF_ID_RSP_SIZE 16
2433 #define RNN_ID_CMD 0x213
2434 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2435 #define RNN_ID_RSP_SIZE 16
2437 #define RSNN_NN_CMD 0x239
2438 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2439 #define RSNN_NN_RSP_SIZE 16
2441 #define GFPN_ID_CMD 0x11C
2442 #define GFPN_ID_REQ_SIZE (16 + 4)
2443 #define GFPN_ID_RSP_SIZE (16 + 8)
2445 #define GPSC_CMD 0x127
2446 #define GPSC_REQ_SIZE (16 + 8)
2447 #define GPSC_RSP_SIZE (16 + 2 + 2)
2449 #define GFF_ID_CMD 0x011F
2450 #define GFF_ID_REQ_SIZE (16 + 4)
2451 #define GFF_ID_RSP_SIZE (16 + 128)
2454 * HBA attribute types.
2456 #define FDMI_HBA_ATTR_COUNT 9
2457 #define FDMIV2_HBA_ATTR_COUNT 17
2458 #define FDMI_HBA_NODE_NAME 0x1
2459 #define FDMI_HBA_MANUFACTURER 0x2
2460 #define FDMI_HBA_SERIAL_NUMBER 0x3
2461 #define FDMI_HBA_MODEL 0x4
2462 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2463 #define FDMI_HBA_HARDWARE_VERSION 0x6
2464 #define FDMI_HBA_DRIVER_VERSION 0x7
2465 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2466 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2467 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2468 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2469 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2470 #define FDMI_HBA_VENDOR_ID 0xd
2471 #define FDMI_HBA_NUM_PORTS 0xe
2472 #define FDMI_HBA_FABRIC_NAME 0xf
2473 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2474 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2476 struct ct_fdmi_hba_attr {
2480 uint8_t node_name[WWN_SIZE];
2481 uint8_t manufacturer[64];
2482 uint8_t serial_num[32];
2483 uint8_t model[16+1];
2484 uint8_t model_desc[80];
2485 uint8_t hw_version[32];
2486 uint8_t driver_version[32];
2487 uint8_t orom_version[16];
2488 uint8_t fw_version[32];
2489 uint8_t os_version[128];
2490 uint32_t max_ct_len;
2494 struct ct_fdmi_hba_attributes {
2496 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2499 struct ct_fdmiv2_hba_attr {
2503 uint8_t node_name[WWN_SIZE];
2504 uint8_t manufacturer[64];
2505 uint8_t serial_num[32];
2506 uint8_t model[16+1];
2507 uint8_t model_desc[80];
2508 uint8_t hw_version[16];
2509 uint8_t driver_version[32];
2510 uint8_t orom_version[16];
2511 uint8_t fw_version[32];
2512 uint8_t os_version[128];
2513 uint32_t max_ct_len;
2514 uint8_t sym_name[256];
2517 uint8_t fabric_name[WWN_SIZE];
2518 uint8_t bios_name[32];
2519 uint8_t vendor_identifier[8];
2523 struct ct_fdmiv2_hba_attributes {
2525 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2529 * Port attribute types.
2531 #define FDMI_PORT_ATTR_COUNT 6
2532 #define FDMIV2_PORT_ATTR_COUNT 16
2533 #define FDMI_PORT_FC4_TYPES 0x1
2534 #define FDMI_PORT_SUPPORT_SPEED 0x2
2535 #define FDMI_PORT_CURRENT_SPEED 0x3
2536 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2537 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2538 #define FDMI_PORT_HOST_NAME 0x6
2539 #define FDMI_PORT_NODE_NAME 0x7
2540 #define FDMI_PORT_NAME 0x8
2541 #define FDMI_PORT_SYM_NAME 0x9
2542 #define FDMI_PORT_TYPE 0xa
2543 #define FDMI_PORT_SUPP_COS 0xb
2544 #define FDMI_PORT_FABRIC_NAME 0xc
2545 #define FDMI_PORT_FC4_TYPE 0xd
2546 #define FDMI_PORT_STATE 0x101
2547 #define FDMI_PORT_COUNT 0x102
2548 #define FDMI_PORT_ID 0x103
2550 #define FDMI_PORT_SPEED_1GB 0x1
2551 #define FDMI_PORT_SPEED_2GB 0x2
2552 #define FDMI_PORT_SPEED_10GB 0x4
2553 #define FDMI_PORT_SPEED_4GB 0x8
2554 #define FDMI_PORT_SPEED_8GB 0x10
2555 #define FDMI_PORT_SPEED_16GB 0x20
2556 #define FDMI_PORT_SPEED_32GB 0x40
2557 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2559 #define FC_CLASS_2 0x04
2560 #define FC_CLASS_3 0x08
2561 #define FC_CLASS_2_3 0x0C
2563 struct ct_fdmiv2_port_attr {
2567 uint8_t fc4_types[32];
2570 uint32_t max_frame_size;
2571 uint8_t os_dev_name[32];
2572 uint8_t host_name[256];
2573 uint8_t node_name[WWN_SIZE];
2574 uint8_t port_name[WWN_SIZE];
2575 uint8_t port_sym_name[128];
2577 uint32_t port_supported_cos;
2578 uint8_t fabric_name[WWN_SIZE];
2579 uint8_t port_fc4_type[32];
2580 uint32_t port_state;
2587 * Port Attribute Block.
2589 struct ct_fdmiv2_port_attributes {
2591 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2594 struct ct_fdmi_port_attr {
2598 uint8_t fc4_types[32];
2601 uint32_t max_frame_size;
2602 uint8_t os_dev_name[32];
2603 uint8_t host_name[256];
2607 struct ct_fdmi_port_attributes {
2609 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2612 /* FDMI definitions. */
2613 #define GRHL_CMD 0x100
2614 #define GHAT_CMD 0x101
2615 #define GRPL_CMD 0x102
2616 #define GPAT_CMD 0x110
2618 #define RHBA_CMD 0x200
2619 #define RHBA_RSP_SIZE 16
2621 #define RHAT_CMD 0x201
2622 #define RPRT_CMD 0x210
2624 #define RPA_CMD 0x211
2625 #define RPA_RSP_SIZE 16
2627 #define DHBA_CMD 0x300
2628 #define DHBA_REQ_SIZE (16 + 8)
2629 #define DHBA_RSP_SIZE 16
2631 #define DHAT_CMD 0x301
2632 #define DPRT_CMD 0x310
2633 #define DPA_CMD 0x311
2635 /* CT command header -- request/response common fields */
2645 /* CT command request */
2647 struct ct_cmd_hdr header;
2649 uint16_t max_rsp_size;
2650 uint8_t fragment_id;
2651 uint8_t reserved[3];
2654 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2670 uint8_t fc4_types[32];
2677 uint8_t fc4_feature;
2684 uint8_t node_name[8];
2688 uint8_t node_name[8];
2690 uint8_t sym_node_name[255];
2694 uint8_t hba_identifier[8];
2698 uint8_t hba_identifier[8];
2699 uint32_t entry_count;
2700 uint8_t port_name[8];
2701 struct ct_fdmi_hba_attributes attrs;
2705 uint8_t hba_identifier[8];
2706 uint32_t entry_count;
2707 uint8_t port_name[8];
2708 struct ct_fdmiv2_hba_attributes attrs;
2712 uint8_t hba_identifier[8];
2713 struct ct_fdmi_hba_attributes attrs;
2717 uint8_t port_name[8];
2718 struct ct_fdmi_port_attributes attrs;
2722 uint8_t port_name[8];
2723 struct ct_fdmiv2_port_attributes attrs;
2727 uint8_t port_name[8];
2731 uint8_t port_name[8];
2735 uint8_t port_name[8];
2739 uint8_t port_name[8];
2743 uint8_t port_name[8];
2748 uint8_t port_name[3];
2752 uint8_t port_name[8];
2757 /* CT command response header */
2759 struct ct_cmd_hdr header;
2762 uint8_t fragment_id;
2763 uint8_t reason_code;
2764 uint8_t explanation_code;
2765 uint8_t vendor_unique;
2768 struct ct_sns_gid_pt_data {
2769 uint8_t control_byte;
2774 struct ct_rsp_hdr header;
2780 uint8_t port_name[8];
2781 uint8_t sym_port_name_len;
2782 uint8_t sym_port_name[255];
2783 uint8_t node_name[8];
2784 uint8_t sym_node_name_len;
2785 uint8_t sym_node_name[255];
2786 uint8_t init_proc_assoc[8];
2787 uint8_t node_ip_addr[16];
2788 uint8_t class_of_service[4];
2789 uint8_t fc4_types[32];
2790 uint8_t ip_address[16];
2791 uint8_t fabric_port_name[8];
2793 uint8_t hard_address[3];
2797 /* Assume the largest number of targets for the union */
2798 struct ct_sns_gid_pt_data
2799 entries[MAX_FIBRE_DEVICES_MAX];
2803 uint8_t port_name[8];
2807 uint8_t node_name[8];
2811 uint8_t fc4_types[32];
2815 uint32_t entry_count;
2816 uint8_t port_name[8];
2817 struct ct_fdmi_hba_attributes attrs;
2821 uint8_t port_name[8];
2829 #define GFF_FCP_SCSI_OFFSET 7
2831 uint8_t fc4_features[128];
2842 struct ct_sns_req req;
2843 struct ct_sns_rsp rsp;
2848 * SNS command structures -- for 2200 compatibility.
2850 #define RFT_ID_SNS_SCMD_LEN 22
2851 #define RFT_ID_SNS_CMD_SIZE 60
2852 #define RFT_ID_SNS_DATA_SIZE 16
2854 #define RNN_ID_SNS_SCMD_LEN 10
2855 #define RNN_ID_SNS_CMD_SIZE 36
2856 #define RNN_ID_SNS_DATA_SIZE 16
2858 #define GA_NXT_SNS_SCMD_LEN 6
2859 #define GA_NXT_SNS_CMD_SIZE 28
2860 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2862 #define GID_PT_SNS_SCMD_LEN 6
2863 #define GID_PT_SNS_CMD_SIZE 28
2865 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
2868 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
2870 #define GPN_ID_SNS_SCMD_LEN 6
2871 #define GPN_ID_SNS_CMD_SIZE 28
2872 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2874 #define GNN_ID_SNS_SCMD_LEN 6
2875 #define GNN_ID_SNS_CMD_SIZE 28
2876 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2878 struct sns_cmd_pkt {
2881 uint16_t buffer_length;
2882 uint16_t reserved_1;
2883 uint32_t buffer_address[2];
2884 uint16_t subcommand_length;
2885 uint16_t reserved_2;
2886 uint16_t subcommand;
2888 uint32_t reserved_3;
2892 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2893 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2894 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2895 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2896 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2897 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2904 const struct firmware *fw;
2907 /* Return data from MBC_GET_ID_LIST call. */
2908 struct gid_list_info {
2912 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2913 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2914 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2918 typedef struct vport_info {
2919 uint8_t port_name[WWN_SIZE];
2920 uint8_t node_name[WWN_SIZE];
2923 unsigned long host_no;
2928 typedef struct vport_params {
2929 uint8_t port_name[WWN_SIZE];
2930 uint8_t node_name[WWN_SIZE];
2932 #define VP_OPTS_RETRY_ENABLE BIT_0
2933 #define VP_OPTS_VP_DISABLE BIT_1
2936 /* NPIV - return codes of VP create and modify */
2937 #define VP_RET_CODE_OK 0
2938 #define VP_RET_CODE_FATAL 1
2939 #define VP_RET_CODE_WRONG_ID 2
2940 #define VP_RET_CODE_WWPN 3
2941 #define VP_RET_CODE_RESOURCES 4
2942 #define VP_RET_CODE_NO_MEM 5
2943 #define VP_RET_CODE_NOT_FOUND 6
2950 struct isp_operations {
2952 int (*pci_config) (struct scsi_qla_host *);
2953 void (*reset_chip) (struct scsi_qla_host *);
2954 int (*chip_diag) (struct scsi_qla_host *);
2955 void (*config_rings) (struct scsi_qla_host *);
2956 void (*reset_adapter) (struct scsi_qla_host *);
2957 int (*nvram_config) (struct scsi_qla_host *);
2958 void (*update_fw_options) (struct scsi_qla_host *);
2959 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2961 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2962 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
2964 irq_handler_t intr_handler;
2965 void (*enable_intrs) (struct qla_hw_data *);
2966 void (*disable_intrs) (struct qla_hw_data *);
2968 int (*abort_command) (srb_t *);
2969 int (*target_reset) (struct fc_port *, uint64_t, int);
2970 int (*lun_reset) (struct fc_port *, uint64_t, int);
2971 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2972 uint8_t, uint8_t, uint16_t *, uint8_t);
2973 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2976 uint16_t (*calc_req_entries) (uint16_t);
2977 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2978 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
2979 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2982 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *,
2983 uint32_t, uint32_t);
2984 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2987 void (*fw_dump) (struct scsi_qla_host *, int);
2989 int (*beacon_on) (struct scsi_qla_host *);
2990 int (*beacon_off) (struct scsi_qla_host *);
2991 void (*beacon_blink) (struct scsi_qla_host *);
2993 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2994 uint32_t, uint32_t);
2995 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2998 int (*get_flash_version) (struct scsi_qla_host *, void *);
2999 int (*start_scsi) (srb_t *);
3000 int (*start_scsi_mq) (srb_t *);
3001 int (*abort_isp) (struct scsi_qla_host *);
3002 int (*iospace_config)(struct qla_hw_data*);
3003 int (*initialize_adapter)(struct scsi_qla_host *);
3006 /* MSI-X Support *************************************************************/
3008 #define QLA_MSIX_CHIP_REV_24XX 3
3009 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3010 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3012 #define QLA_BASE_VECTORS 2 /* default + RSP */
3013 #define QLA_MSIX_RSP_Q 0x01
3014 #define QLA_ATIO_VECTOR 0x02
3015 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3017 #define QLA_MIDX_DEFAULT 0
3018 #define QLA_MIDX_RSP_Q 1
3019 #define QLA_PCI_MSIX_CONTROL 0xa2
3020 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3022 struct scsi_qla_host;
3025 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3027 struct qla_msix_entry {
3037 #define WATCH_INTERVAL 1 /* number of seconds */
3040 enum qla_work_type {
3043 QLA_EVT_ASYNC_LOGIN,
3044 QLA_EVT_ASYNC_LOGOUT,
3045 QLA_EVT_ASYNC_LOGOUT_DONE,
3046 QLA_EVT_ASYNC_ADISC,
3047 QLA_EVT_ASYNC_ADISC_DONE,
3062 struct qla_work_evt {
3063 struct list_head list;
3064 enum qla_work_type type;
3066 #define QLA_EVT_FLAG_FREE 0x1
3070 enum fc_host_event_code code;
3074 #define QLA_IDC_ACK_REGS 7
3075 uint16_t mb[QLA_IDC_ACK_REGS];
3078 struct fc_port *fcport;
3079 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3084 #define QLA_UEVENT_CODE_FW_DUMP 0
3102 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3114 struct qla_chip_state_84xx {
3115 struct list_head list;
3119 spinlock_t access_lock;
3120 struct mutex fw_update_mutex;
3122 uint32_t op_fw_version;
3123 uint32_t op_fw_size;
3124 uint32_t op_fw_seq_size;
3125 uint32_t diag_fw_version;
3126 uint32_t gold_fw_version;
3129 struct qla_dif_statistics {
3130 uint64_t dif_input_bytes;
3131 uint64_t dif_output_bytes;
3132 uint64_t dif_input_requests;
3133 uint64_t dif_output_requests;
3134 uint32_t dif_guard_err;
3135 uint32_t dif_ref_tag_err;
3136 uint32_t dif_app_tag_err;
3139 struct qla_statistics {
3140 uint32_t total_isp_aborts;
3141 uint64_t input_bytes;
3142 uint64_t output_bytes;
3143 uint64_t input_requests;
3144 uint64_t output_requests;
3145 uint32_t control_requests;
3147 uint64_t jiffies_at_last_reset;
3148 uint32_t stat_max_pend_cmds;
3149 uint32_t stat_max_qfull_cmds_alloc;
3150 uint32_t stat_max_qfull_cmds_dropped;
3152 struct qla_dif_statistics qla_dif_stats;
3155 struct bidi_statistics {
3156 unsigned long long io_count;
3157 unsigned long long transfer_bytes;
3160 struct qla_tc_param {
3161 struct scsi_qla_host *vha;
3164 struct scatterlist *sg;
3165 struct scatterlist *prot_sg;
3166 struct crc_context *ctx;
3167 uint8_t *ctx_dsd_alloced;
3170 /* Multi queue support */
3171 #define MBC_INITIALIZE_MULTIQ 0x1f
3172 #define QLA_QUE_PAGE 0X1000
3173 #define QLA_MQ_SIZE 32
3174 #define QLA_MAX_QUEUES 256
3175 #define ISP_QUE_REG(ha, id) \
3176 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \
3177 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3178 ((void __iomem *)ha->iobase))
3179 #define QLA_REQ_QUE_ID(tag) \
3180 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3181 #define QLA_DEFAULT_QUE_QOS 5
3182 #define QLA_PRECONFIG_VPORTS 32
3183 #define QLA_MAX_VPORTS_QLA24XX 128
3184 #define QLA_MAX_VPORTS_QLA25XX 256
3188 /* Response queue data structure */
3192 response_t *ring_ptr;
3193 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
3194 uint32_t __iomem *rsp_q_out;
3195 uint16_t ring_index;
3197 uint16_t *in_ptr; /* queue shadow in index */
3203 struct qla_hw_data *hw;
3204 struct qla_msix_entry *msix;
3205 struct req_que *req;
3206 srb_t *status_srb; /* status continuation entry */
3207 struct qla_qpair *qpair;
3209 dma_addr_t dma_fx00;
3210 response_t *ring_fx00;
3211 uint16_t length_fx00;
3212 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3215 /* Request queue data structure */
3219 request_t *ring_ptr;
3220 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
3221 uint32_t __iomem *req_q_out;
3222 uint16_t ring_index;
3224 uint16_t *out_ptr; /* queue shadow out index */
3232 struct rsp_que *rsp;
3233 srb_t **outstanding_cmds;
3234 uint32_t current_outstanding_cmd;
3235 uint16_t num_outstanding_cmds;
3238 dma_addr_t dma_fx00;
3239 request_t *ring_fx00;
3240 uint16_t length_fx00;
3241 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3244 /*Queue pair data structure */
3250 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3251 * legacy code. For other Qpair(s), it will point at qp_lock.
3253 spinlock_t *qp_lock_ptr;
3254 struct scsi_qla_host *vha;
3256 /* distill these fields down to 'online=0/1'
3257 * ha->flags.eeh_busy
3258 * ha->flags.pci_channel_io_perm_failure
3259 * base_vha->loop_state
3262 /* move vha->flags.difdix_supported here */
3263 uint32_t difdix_supported:1;
3264 uint32_t delete_in_progress:1;
3266 uint16_t id; /* qp number used with FW */
3267 uint16_t vp_idx; /* vport ID */
3268 mempool_t *srb_mempool;
3270 /* to do: New driver: move queues to here instead of pointers */
3271 struct req_que *req;
3272 struct rsp_que *rsp;
3273 struct atio_que *atio;
3274 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3275 struct qla_hw_data *hw;
3276 struct work_struct q_work;
3277 struct list_head qp_list_elem; /* vha->qp_list */
3278 struct list_head hints_list;
3282 /* Place holder for FW buffer parameters */
3289 struct scsi_qlt_host {
3290 void *target_lport_ptr;
3291 struct mutex tgt_mutex;
3292 struct mutex tgt_host_action_mutex;
3293 struct qla_tgt *qla_tgt;
3296 struct qlt_hw_data {
3297 /* Protected by hw lock */
3298 uint32_t enable_class_2:1;
3299 uint32_t enable_explicit_conf:1;
3300 uint32_t node_name_set:1;
3302 dma_addr_t atio_dma; /* Physical address. */
3303 struct atio *atio_ring; /* Base virtual address */
3304 struct atio *atio_ring_ptr; /* Current address. */
3305 uint16_t atio_ring_index; /* Current index. */
3306 uint16_t atio_q_length;
3307 uint32_t __iomem *atio_q_in;
3308 uint32_t __iomem *atio_q_out;
3310 struct qla_tgt_func_tmpl *tgt_ops;
3311 struct qla_tgt_vp_map *tgt_vp_map;
3314 uint16_t saved_exchange_count;
3315 uint32_t saved_firmware_options_1;
3316 uint32_t saved_firmware_options_2;
3317 uint32_t saved_firmware_options_3;
3318 uint8_t saved_firmware_options[2];
3319 uint8_t saved_add_firmware_options[2];
3321 uint8_t tgt_node_name[WWN_SIZE];
3323 struct dentry *dfs_tgt_sess;
3324 struct dentry *dfs_tgt_port_database;
3326 struct list_head q_full_list;
3327 uint32_t num_pend_cmds;
3328 uint32_t num_qfull_cmds_alloc;
3329 uint32_t num_qfull_cmds_dropped;
3330 spinlock_t q_full_lock;
3331 uint32_t leak_exchg_thresh_hold;
3332 spinlock_t sess_lock;
3333 int rspq_vector_cpuid;
3334 spinlock_t atio_lock ____cacheline_aligned;
3335 struct btree_head32 host_map;
3338 #define MAX_QFULL_CMDS_ALLOC 8192
3339 #define Q_FULL_THRESH_HOLD_PERCENT 90
3340 #define Q_FULL_THRESH_HOLD(ha) \
3341 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3343 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3345 #define QLA_EARLY_LINKUP(_ha) \
3346 ((_ha->flags.n2n_ae || _ha->flags.lip_ae) && \
3347 _ha->flags.fw_started && !_ha->flags.fw_init_done)
3350 * Qlogic host adapter specific data structure.
3352 struct qla_hw_data {
3353 struct pci_dev *pdev;
3355 #define SRB_MIN_REQ 128
3356 mempool_t *srb_mempool;
3359 uint32_t mbox_int :1;
3360 uint32_t mbox_busy :1;
3361 uint32_t disable_risc_code_load :1;
3362 uint32_t enable_64bit_addressing :1;
3363 uint32_t enable_lip_reset :1;
3364 uint32_t enable_target_reset :1;
3365 uint32_t enable_lip_full_login :1;
3366 uint32_t enable_led_scheme :1;
3368 uint32_t msi_enabled :1;
3369 uint32_t msix_enabled :1;
3370 uint32_t disable_serdes :1;
3371 uint32_t gpsc_supported :1;
3372 uint32_t npiv_supported :1;
3373 uint32_t pci_channel_io_perm_failure :1;
3374 uint32_t fce_enabled :1;
3375 uint32_t fac_supported :1;
3377 uint32_t chip_reset_done :1;
3378 uint32_t running_gold_fw :1;
3379 uint32_t eeh_busy :1;
3380 uint32_t disable_msix_handshake :1;
3381 uint32_t fcp_prio_enabled :1;
3382 uint32_t isp82xx_fw_hung:1;
3383 uint32_t nic_core_hung:1;
3385 uint32_t quiesce_owner:1;
3386 uint32_t nic_core_reset_hdlr_active:1;
3387 uint32_t nic_core_reset_owner:1;
3388 uint32_t isp82xx_no_md_cap:1;
3389 uint32_t host_shutting_down:1;
3390 uint32_t idc_compl_status:1;
3391 uint32_t mr_reset_hdlr_active:1;
3392 uint32_t mr_intr_valid:1;
3394 uint32_t dport_enabled:1;
3395 uint32_t fawwpn_enabled:1;
3396 uint32_t exlogins_enabled:1;
3397 uint32_t exchoffld_enabled:1;
3401 uint32_t fw_started:1;
3402 uint32_t fw_init_done:1;
3405 /* This spinlock is used to protect "io transactions", you must
3406 * acquire it before doing any IO to the card, eg with RD_REG*() and
3407 * WRT_REG*() for the duration of your entire commandtransaction.
3409 * This spinlock is of lower priority than the io request lock.
3412 spinlock_t hardware_lock ____cacheline_aligned;
3415 device_reg_t *iobase; /* Base I/O address */
3416 resource_size_t pio_address;
3418 #define MIN_IOBASE_LEN 0x100
3419 dma_addr_t bar0_hdl;
3421 void __iomem *cregbase;
3422 dma_addr_t bar2_hdl;
3423 #define BAR0_LEN_FX00 (1024 * 1024)
3424 #define BAR2_LEN_FX00 (128 * 1024)
3426 uint32_t rqstq_intr_code;
3427 uint32_t mbx_intr_code;
3428 uint32_t req_que_len;
3429 uint32_t rsp_que_len;
3430 uint32_t req_que_off;
3431 uint32_t rsp_que_off;
3433 /* Multi queue data structs */
3434 device_reg_t *mqiobase;
3435 device_reg_t *msixbase;
3436 uint16_t msix_count;
3438 struct req_que **req_q_map;
3439 struct rsp_que **rsp_q_map;
3440 struct qla_qpair **queue_pair_map;
3441 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3442 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3443 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3444 / sizeof(unsigned long)];
3445 uint8_t max_req_queues;
3446 uint8_t max_rsp_queues;
3449 struct qla_qpair *base_qpair;
3450 struct qla_npiv_entry *npiv_info;
3451 uint16_t nvram_npiv_size;
3453 uint16_t switch_cap;
3454 #define FLOGI_SEQ_DEL BIT_8
3455 #define FLOGI_MID_SUPPORT BIT_10
3456 #define FLOGI_VSAN_SUPPORT BIT_12
3457 #define FLOGI_SP_SUPPORT BIT_13
3459 uint8_t port_no; /* Physical port of adapter */
3460 uint8_t exch_starvation;
3462 /* Timeout timers. */
3463 uint8_t loop_down_abort_time; /* port down timer */
3464 atomic_t loop_down_timer; /* loop down timer */
3465 uint8_t link_down_timeout; /* link down timeout */
3466 uint16_t max_loop_id;
3467 uint16_t max_fibre_devices; /* Maximum number of targets */
3470 uint16_t min_external_loopid; /* First external loop Id */
3472 #define PORT_SPEED_UNKNOWN 0xFFFF
3473 #define PORT_SPEED_1GB 0x00
3474 #define PORT_SPEED_2GB 0x01
3475 #define PORT_SPEED_4GB 0x03
3476 #define PORT_SPEED_8GB 0x04
3477 #define PORT_SPEED_16GB 0x05
3478 #define PORT_SPEED_32GB 0x06
3479 #define PORT_SPEED_10GB 0x13
3480 uint16_t link_data_rate; /* F/W operating speed */
3482 uint8_t current_topology;
3483 uint8_t prev_topology;
3484 #define ISP_CFG_NL 1
3486 #define ISP_CFG_FL 4
3489 uint8_t operating_mode; /* F/W operating mode */
3494 uint8_t interrupts_on;
3495 uint32_t isp_abort_cnt;
3496 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3497 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3498 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3499 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3500 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3501 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3502 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3503 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3506 #define DT_ISP2100 BIT_0
3507 #define DT_ISP2200 BIT_1
3508 #define DT_ISP2300 BIT_2
3509 #define DT_ISP2312 BIT_3
3510 #define DT_ISP2322 BIT_4
3511 #define DT_ISP6312 BIT_5
3512 #define DT_ISP6322 BIT_6
3513 #define DT_ISP2422 BIT_7
3514 #define DT_ISP2432 BIT_8
3515 #define DT_ISP5422 BIT_9
3516 #define DT_ISP5432 BIT_10
3517 #define DT_ISP2532 BIT_11
3518 #define DT_ISP8432 BIT_12
3519 #define DT_ISP8001 BIT_13
3520 #define DT_ISP8021 BIT_14
3521 #define DT_ISP2031 BIT_15
3522 #define DT_ISP8031 BIT_16
3523 #define DT_ISPFX00 BIT_17
3524 #define DT_ISP8044 BIT_18
3525 #define DT_ISP2071 BIT_19
3526 #define DT_ISP2271 BIT_20
3527 #define DT_ISP2261 BIT_21
3528 #define DT_ISP_LAST (DT_ISP2261 << 1)
3530 uint32_t device_type;
3531 #define DT_T10_PI BIT_25
3532 #define DT_IIDMA BIT_26
3533 #define DT_FWI2 BIT_27
3534 #define DT_ZIO_SUPPORTED BIT_28
3535 #define DT_OEM_001 BIT_29
3536 #define DT_ISP2200A BIT_30
3537 #define DT_EXTENDED_IDS BIT_31
3539 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3540 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3541 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3542 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3543 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3544 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3545 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3546 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3547 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3548 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3549 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3550 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3551 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3552 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3553 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3554 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3555 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3556 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3557 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3558 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3559 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3560 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3561 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3562 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3564 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3565 IS_QLA6312(ha) || IS_QLA6322(ha))
3566 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3567 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3568 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3569 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3570 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
3571 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3572 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3574 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3575 IS_QLA8031(ha) || IS_QLA8044(ha))
3576 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3577 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3578 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3579 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3580 IS_QLA8044(ha) || IS_QLA27XX(ha))
3581 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3583 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3584 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3586 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3588 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3590 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3591 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3592 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3593 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3594 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3595 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3596 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3597 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3599 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
3600 /* Bit 21 of fw_attributes decides the MCTP capabilities */
3601 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3602 ((ha)->fw_attributes_ext[0] & BIT_0))
3603 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3604 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3605 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3606 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3607 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3608 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3609 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3610 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3611 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
3612 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3613 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3614 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
3615 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3616 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
3617 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3619 /* HBA serial number */
3624 /* NVRAM configuration data */
3625 #define MAX_NVRAM_SIZE 4096
3626 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
3627 uint16_t nvram_size;
3628 uint16_t nvram_base;
3634 uint16_t loop_reset_delay;
3635 uint8_t retry_count;
3636 uint8_t login_timeout;
3638 int port_down_retry_count;
3640 uint8_t aen_mbx_count;
3642 uint32_t login_retry_count;
3643 /* SNS command interfaces. */
3644 ms_iocb_entry_t *ms_iocb;
3645 dma_addr_t ms_iocb_dma;
3646 struct ct_sns_pkt *ct_sns;
3647 dma_addr_t ct_sns_dma;
3648 /* SNS command interfaces for 2200. */
3649 struct sns_cmd_pkt *sns_cmd;
3650 dma_addr_t sns_cmd_dma;
3652 #define SFP_DEV_SIZE 256
3653 #define SFP_BLOCK_SIZE 64
3655 dma_addr_t sfp_data_dma;
3657 #define XGMAC_DATA_SIZE 4096
3659 dma_addr_t xgmac_data_dma;
3661 #define DCBX_TLV_DATA_SIZE 4096
3663 dma_addr_t dcbx_tlv_dma;
3665 struct task_struct *dpc_thread;
3666 uint8_t dpc_active; /* DPC routine is active */
3668 dma_addr_t gid_list_dma;
3669 struct gid_list_info *gid_list;
3670 int gid_list_info_size;
3672 /* Small DMA pool allocations -- maximum 256 bytes in length. */
3673 #define DMA_POOL_SIZE 256
3674 struct dma_pool *s_dma_pool;
3676 dma_addr_t init_cb_dma;
3679 dma_addr_t ex_init_cb_dma;
3680 struct ex_init_cb_81xx *ex_init_cb;
3683 dma_addr_t async_pd_dma;
3685 #define ENABLE_EXTENDED_LOGIN BIT_7
3687 /* Extended Logins */
3689 dma_addr_t exlogin_buf_dma;
3692 #define ENABLE_EXCHANGE_OFFLD BIT_2
3694 /* Exchange Offload */
3695 void *exchoffld_buf;
3696 dma_addr_t exchoffld_buf_dma;
3698 int exchoffld_count;
3702 /* These are used by mailbox operations. */
3703 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3704 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3705 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3708 struct mbx_cmd_32 *mcp32;
3710 unsigned long mbx_cmd_flags;
3711 #define MBX_INTERRUPT 1
3712 #define MBX_INTR_WAIT 2
3713 #define MBX_UPDATE_FLASH_ACTIVE 3
3715 struct mutex vport_lock; /* Virtual port synchronization */
3716 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
3717 struct mutex mq_lock; /* multi-queue synchronization */
3718 struct completion mbx_cmd_comp; /* Serialize mbx access */
3719 struct completion mbx_intr_comp; /* Used for completion notification */
3720 struct completion dcbx_comp; /* For set port config notification */
3721 struct completion lb_portup_comp; /* Used to wait for link up during
3723 #define DCBX_COMP_TIMEOUT 20
3724 #define LB_PORTUP_COMP_TIMEOUT 10
3726 int notify_dcbx_comp;
3727 int notify_lb_portup_comp;
3728 struct mutex selflogin_lock;
3730 /* Basic firmware related information. */
3731 uint16_t fw_major_version;
3732 uint16_t fw_minor_version;
3733 uint16_t fw_subminor_version;
3734 uint16_t fw_attributes;
3735 uint16_t fw_attributes_h;
3736 uint16_t fw_attributes_ext[2];
3737 uint32_t fw_memory_size;
3738 uint32_t fw_transfer_size;
3739 uint32_t fw_srisc_address;
3740 #define RISC_START_ADDRESS_2100 0x1000
3741 #define RISC_START_ADDRESS_2300 0x800
3742 #define RISC_START_ADDRESS_2400 0x100000
3744 uint16_t orig_fw_tgt_xcb_count;
3745 uint16_t cur_fw_tgt_xcb_count;
3746 uint16_t orig_fw_xcb_count;
3747 uint16_t cur_fw_xcb_count;
3748 uint16_t orig_fw_iocb_count;
3749 uint16_t cur_fw_iocb_count;
3750 uint16_t fw_max_fcf_count;
3752 uint32_t fw_shared_ram_start;
3753 uint32_t fw_shared_ram_end;
3754 uint32_t fw_ddr_ram_start;
3755 uint32_t fw_ddr_ram_end;
3757 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
3758 uint8_t fw_seriallink_options[4];
3759 uint16_t fw_seriallink_options24[4];
3761 uint8_t mpi_version[3];
3762 uint32_t mpi_capabilities;
3763 uint8_t phy_version[3];
3764 uint8_t pep_version[3];
3766 /* Firmware dump template */
3767 void *fw_dump_template;
3768 uint32_t fw_dump_template_len;
3769 /* Firmware dump information. */
3770 struct qla2xxx_fw_dump *fw_dump;
3771 uint32_t fw_dump_len;
3773 unsigned long fw_dump_cap_flags;
3774 #define RISC_PAUSE_CMPL 0
3775 #define DMA_SHUTDOWN_CMPL 1
3776 #define ISP_RESET_CMPL 2
3777 #define RISC_RDY_AFT_RESET 3
3778 #define RISC_SRAM_DUMP_CMPL 4
3779 #define RISC_EXT_MEM_DUMP_CMPL 5
3780 #define ISP_MBX_RDY 6
3781 #define ISP_SOFT_RESET_CMPL 7
3782 int fw_dump_reading;
3783 int prev_minidump_failed;
3786 /* Current size of mctp dump is 0x086064 bytes */
3787 #define MCTP_DUMP_SIZE 0x086064
3788 dma_addr_t mctp_dump_dma;
3791 int mctp_dump_reading;
3792 uint32_t chain_offset;
3793 struct dentry *dfs_dir;
3794 struct dentry *dfs_fce;
3795 struct dentry *dfs_tgt_counters;
3796 struct dentry *dfs_fw_resource_cnt;
3802 uint64_t fce_wr, fce_rd;
3803 struct mutex fce_mutex;
3806 uint16_t chip_revision;
3808 uint16_t product_id[4];
3810 uint8_t model_number[16+1];
3811 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
3812 char model_desc[80];
3813 uint8_t adapter_id[16+1];
3815 /* Option ROM information. */
3816 char *optrom_buffer;
3817 uint32_t optrom_size;
3819 #define QLA_SWAITING 0
3820 #define QLA_SREADING 1
3821 #define QLA_SWRITING 2
3822 uint32_t optrom_region_start;
3823 uint32_t optrom_region_size;
3824 struct mutex optrom_mutex;
3826 /* PCI expansion ROM image information. */
3827 #define ROM_CODE_TYPE_BIOS 0
3828 #define ROM_CODE_TYPE_FCODE 1
3829 #define ROM_CODE_TYPE_EFI 3
3830 uint8_t bios_revision[2];
3831 uint8_t efi_revision[2];
3832 uint8_t fcode_revision[16];
3833 uint32_t fw_revision[4];
3835 uint32_t gold_fw_version[4];
3837 /* Offsets for flash/nvram access (set to ~0 if not used). */
3838 uint32_t flash_conf_off;
3839 uint32_t flash_data_off;
3840 uint32_t nvram_conf_off;
3841 uint32_t nvram_data_off;
3843 uint32_t fdt_wrt_disable;
3844 uint32_t fdt_wrt_enable;
3845 uint32_t fdt_erase_cmd;
3846 uint32_t fdt_block_size;
3847 uint32_t fdt_unprotect_sec_cmd;
3848 uint32_t fdt_protect_sec_cmd;
3849 uint32_t fdt_wrt_sts_reg_cmd;
3851 uint32_t flt_region_flt;
3852 uint32_t flt_region_fdt;
3853 uint32_t flt_region_boot;
3854 uint32_t flt_region_boot_sec;
3855 uint32_t flt_region_fw;
3856 uint32_t flt_region_fw_sec;
3857 uint32_t flt_region_vpd_nvram;
3858 uint32_t flt_region_vpd;
3859 uint32_t flt_region_vpd_sec;
3860 uint32_t flt_region_nvram;
3861 uint32_t flt_region_npiv_conf;
3862 uint32_t flt_region_gold_fw;
3863 uint32_t flt_region_fcp_prio;
3864 uint32_t flt_region_bootload;
3865 uint32_t flt_region_img_status_pri;
3866 uint32_t flt_region_img_status_sec;
3867 uint8_t active_image;
3869 /* Needed for BEACON */
3870 uint16_t beacon_blink_led;
3871 uint8_t beacon_color_state;
3872 #define QLA_LED_GRN_ON 0x01
3873 #define QLA_LED_YLW_ON 0x02
3874 #define QLA_LED_ABR_ON 0x04
3875 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
3876 /* ISP2322: red, green, amber. */
3880 struct qla_msix_entry *msix_entries;
3882 struct list_head vp_list; /* list of VP */
3883 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
3884 sizeof(unsigned long)];
3885 uint16_t num_vhosts; /* number of vports created */
3886 uint16_t num_vsans; /* number of vsan created */
3887 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
3888 int cur_vport_count;
3890 struct qla_chip_state_84xx *cs84xx;
3891 struct isp_operations *isp_ops;
3892 struct workqueue_struct *wq;
3893 struct qlfc_fw fw_buf;
3895 /* FCP_CMND priority support */
3896 struct qla_fcp_prio_cfg *fcp_prio_cfg;
3898 struct dma_pool *dl_dma_pool;
3899 #define DSD_LIST_DMA_POOL_SIZE 512
3901 struct dma_pool *fcp_cmnd_dma_pool;
3902 mempool_t *ctx_mempool;
3903 #define FCP_CMND_DMA_POOL_SIZE 512
3905 void __iomem *nx_pcibase; /* Base I/O address */
3906 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
3907 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
3910 uint32_t curr_window;
3911 uint32_t ddr_mn_window;
3912 unsigned long mn_win_crb;
3913 unsigned long ms_win_crb;
3915 uint32_t fcoe_dev_init_timeout;
3916 uint32_t fcoe_reset_timeout;
3918 uint16_t portnum; /* port number */
3920 struct fw_blob *hablob;
3921 struct qla82xx_legacy_intr_set nx_legacy_intr;
3923 uint16_t gbl_dsd_inuse;
3924 uint16_t gbl_dsd_avail;
3925 struct list_head gbl_dsd_list;
3926 #define NUM_DSD_CHAIN 4096
3929 __le32 file_prd_off; /* File firmware product offset */
3931 uint32_t md_template_size;
3933 dma_addr_t md_tmplt_hdr_dma;
3935 uint32_t md_dump_size;
3939 /* QLA83XX IDC specific fields */
3940 uint32_t idc_audit_ts;
3941 uint32_t idc_extend_tmo;
3943 /* DPC low-priority workqueue */
3944 struct workqueue_struct *dpc_lp_wq;
3945 struct work_struct idc_aen;
3946 /* DPC high-priority workqueue */
3947 struct workqueue_struct *dpc_hp_wq;
3948 struct work_struct nic_core_reset;
3949 struct work_struct idc_state_handler;
3950 struct work_struct nic_core_unrecoverable;
3951 struct work_struct board_disable;
3953 struct mr_data_fx00 mr;
3954 uint32_t chip_reset;
3956 struct qlt_hw_data tgt;
3957 int allow_cna_fw_dump;
3960 struct qla_tgt_counters {
3961 uint64_t qla_core_sbt_cmd;
3962 uint64_t core_qla_que_buf;
3963 uint64_t qla_core_ret_ctio;
3964 uint64_t core_qla_snd_status;
3965 uint64_t qla_core_ret_sta_ctio;
3966 uint64_t core_qla_free_cmd;
3967 uint64_t num_q_full_sent;
3968 uint64_t num_alloc_iocb_failed;
3969 uint64_t num_term_xchg_sent;
3973 * Qlogic scsi host structure
3975 typedef struct scsi_qla_host {
3976 struct list_head list;
3977 struct list_head vp_fcports; /* list of fcports */
3978 struct list_head work_list;
3979 spinlock_t work_lock;
3980 struct work_struct iocb_work;
3982 /* Commonly used flags and state information. */
3983 struct Scsi_Host *host;
3984 unsigned long host_no;
3985 uint8_t host_str[16];
3988 uint32_t init_done :1;
3990 uint32_t reset_active :1;
3992 uint32_t management_server_logged_in :1;
3993 uint32_t process_response_queue :1;
3994 uint32_t difdix_supported:1;
3995 uint32_t delete_progress:1;
3997 uint32_t fw_tgt_reported:1;
3998 uint32_t bbcr_enable:1;
3999 uint32_t qpairs_available:1;
4002 atomic_t loop_state;
4003 #define LOOP_TIMEOUT 1
4006 #define LOOP_UPDATE 4
4007 #define LOOP_READY 5
4010 unsigned long dpc_flags;
4011 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4012 #define RESET_ACTIVE 1
4013 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4014 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4015 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4016 #define LOOP_RESYNC_ACTIVE 5
4017 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4018 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
4019 #define RELOGIN_NEEDED 8
4020 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4021 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
4022 #define BEACON_BLINK_NEEDED 11
4023 #define REGISTER_FDMI_NEEDED 12
4024 #define FCPORT_UPDATE_NEEDED 13
4025 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4026 #define UNLOADING 15
4027 #define NPIV_CONFIG_NEEDED 16
4028 #define ISP_UNRECOVERABLE 17
4029 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4030 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4031 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4033 #define PORT_UPDATE_NEEDED 22
4034 #define FX00_RESET_RECOVERY 23
4035 #define FX00_TARGET_SCAN 24
4036 #define FX00_CRITEMP_RECOVERY 25
4037 #define FX00_HOST_INFO_RESEND 26
4038 #define QPAIR_ONLINE_CHECK_NEEDED 27
4040 unsigned long pci_flags;
4041 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4042 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4043 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4045 uint32_t device_flags;
4046 #define SWITCH_FOUND BIT_0
4047 #define DFLG_NO_CABLE BIT_1
4048 #define DFLG_DEV_FAILED BIT_5
4050 /* ISP configuration data. */
4051 uint16_t loop_id; /* Host adapter loop id */
4052 uint16_t self_login_loop_id; /* host adapter loop id
4053 * get it on self login
4055 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4056 * no need of allocating it for
4060 port_id_t d_id; /* Host adapter port id */
4061 uint8_t marker_needed;
4062 uint16_t mgmt_svr_loop_id;
4066 /* Timeout timers. */
4067 uint8_t loop_down_abort_time; /* port down timer */
4068 atomic_t loop_down_timer; /* loop down timer */
4069 uint8_t link_down_timeout; /* link down timeout */
4071 uint32_t timer_active;
4072 struct timer_list timer;
4074 uint8_t node_name[WWN_SIZE];
4075 uint8_t port_name[WWN_SIZE];
4076 uint8_t fabric_node_name[WWN_SIZE];
4078 uint16_t fcoe_vlan_id;
4079 uint16_t fcoe_fcf_idx;
4080 uint8_t fcoe_vn_port_mac[6];
4082 /* list of commands waiting on workqueue */
4083 struct list_head qla_cmd_list;
4084 struct list_head qla_sess_op_cmd_list;
4085 struct list_head unknown_atio_list;
4086 spinlock_t cmd_list_lock;
4087 struct delayed_work unknown_atio_work;
4089 /* Counter to detect races between ELS and RSCN events */
4090 atomic_t generation_tick;
4091 /* Time when global fcport update has been scheduled */
4092 int total_fcport_update_gen;
4093 /* List of pending LOGOs, protected by tgt_mutex */
4094 struct list_head logo_list;
4095 /* List of pending PLOGI acks, protected by hw lock */
4096 struct list_head plogi_ack_list;
4098 struct list_head qp_list;
4100 uint32_t vp_abort_cnt;
4102 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
4103 uint16_t vp_idx; /* vport ID */
4104 struct qla_qpair *qpair; /* base qpair */
4106 unsigned long vp_flags;
4107 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
4108 #define VP_CREATE_NEEDED 1
4109 #define VP_BIND_NEEDED 2
4110 #define VP_DELETE_NEEDED 3
4111 #define VP_SCR_NEEDED 4 /* State Change Request registration */
4112 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
4114 #define VP_OFFLINE 0
4117 // #define VP_DISABLE 3
4118 uint16_t vp_err_state;
4119 uint16_t vp_prev_err_state;
4120 #define VP_ERR_UNKWN 0
4121 #define VP_ERR_PORTDWN 1
4122 #define VP_ERR_FAB_UNSUPPORTED 2
4123 #define VP_ERR_FAB_NORESOURCES 3
4124 #define VP_ERR_FAB_LOGOUT 4
4125 #define VP_ERR_ADAP_NORESOURCES 5
4126 struct qla_hw_data *hw;
4127 struct scsi_qlt_host vha_tgt;
4128 struct req_que *req;
4129 int fw_heartbeat_counter;
4130 int seconds_since_last_heartbeat;
4131 struct fc_host_statistics fc_host_stat;
4132 struct qla_statistics qla_stats;
4133 struct bidi_statistics bidi_stats;
4135 atomic_t vref_count;
4136 struct qla8044_reset_template reset_tmplt;
4137 struct qla_tgt_counters tgt_counters;
4139 struct name_list_extended gnl;
4140 /* Count of active session/fcport */
4142 wait_queue_head_t fcport_waitQ;
4143 wait_queue_head_t vref_waitq;
4146 struct qla27xx_image_status {
4147 uint8_t image_status_mask;
4148 uint16_t generation_number;
4149 uint8_t reserved[3];
4156 #define SET_VP_IDX 1
4158 #define RESET_VP_IDX 3
4159 #define RESET_AL_PA 4
4160 struct qla_tgt_vp_map {
4162 scsi_qla_host_t *vha;
4166 dma_addr_t dma_addr; /* OUT */
4167 uint32_t dma_len; /* OUT */
4169 uint32_t tot_bytes; /* IN */
4170 struct scatterlist *cur_sg; /* IN */
4172 /* for book keeping, bzero on initial invocation */
4173 uint32_t bytes_consumed;
4175 uint32_t tot_partial;
4183 * Macros to help code, maintain, etc.
4185 #define LOOP_TRANSITION(ha) \
4186 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4187 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4188 atomic_read(&ha->loop_state) == LOOP_DOWN)
4190 #define STATE_TRANSITION(ha) \
4191 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4192 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4194 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4195 atomic_inc(&__vha->vref_count); \
4197 if (__vha->flags.delete_progress) { \
4198 atomic_dec(&__vha->vref_count); \
4199 wake_up(&__vha->vref_waitq); \
4206 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4207 atomic_dec(&__vha->vref_count); \
4208 wake_up(&__vha->vref_waitq); \
4211 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4212 atomic_inc(&__qpair->ref_count); \
4214 if (__qpair->delete_in_progress) { \
4215 atomic_dec(&__qpair->ref_count); \
4222 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4223 atomic_dec(&__qpair->ref_count); \
4226 * qla2x00 local function return status codes
4228 #define MBS_MASK 0x3fff
4230 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4231 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4232 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4233 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4234 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4235 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4236 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4237 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4238 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4239 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4241 #define QLA_FUNCTION_TIMEOUT 0x100
4242 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
4243 #define QLA_FUNCTION_FAILED 0x102
4244 #define QLA_MEMORY_ALLOC_FAILED 0x103
4245 #define QLA_LOCK_TIMEOUT 0x104
4246 #define QLA_ABORTED 0x105
4247 #define QLA_SUSPENDED 0x106
4248 #define QLA_BUSY 0x107
4249 #define QLA_ALREADY_REGISTERED 0x109
4251 #define NVRAM_DELAY() udelay(10)
4254 * Flash support definitions
4256 #define OPTROM_SIZE_2300 0x20000
4257 #define OPTROM_SIZE_2322 0x100000
4258 #define OPTROM_SIZE_24XX 0x100000
4259 #define OPTROM_SIZE_25XX 0x200000
4260 #define OPTROM_SIZE_81XX 0x400000
4261 #define OPTROM_SIZE_82XX 0x800000
4262 #define OPTROM_SIZE_83XX 0x1000000
4264 #define OPTROM_BURST_SIZE 0x1000
4265 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4267 #define QLA_DSDS_PER_IOCB 37
4269 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4271 #define QLA_SG_ALL 1024
4273 enum nexus_wait_type {
4279 #include "qla_target.h"
4280 #include "qla_gbl.h"
4281 #include "qla_dbg.h"
4282 #include "qla_inline.h"