2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
14 * | Module Init and Probe | 0x0126 | 0x4b,0xba,0xfa |
15 * | Mailbox commands | 0x115b | 0x111a-0x111b |
16 * | | | 0x112c-0x112e |
18 * | | | 0x1155-0x1158 |
19 * | Device Discovery | 0x2087 | 0x2020-0x2022, |
21 * | Queue Command and IO tracing | 0x3031 | 0x3006-0x300b |
22 * | | | 0x3027-0x3028 |
23 * | | | 0x302d-0x302e |
24 * | DPC Thread | 0x401d | 0x4002,0x4013 |
25 * | Async Events | 0x5071 | 0x502b-0x502f |
26 * | | | 0x5047,0x5052 |
27 * | Timer Routines | 0x6011 | |
28 * | User Space Interactions | 0x70c4 | 0x7018,0x702e, |
29 * | | | 0x7020,0x7024, |
30 * | | | 0x7039,0x7045, |
31 * | | | 0x7073-0x7075, |
33 * | | | 0x70a5,0x70a6, |
34 * | | | 0x70a8,0x70ab, |
35 * | | | 0x70ad-0x70ae |
36 * | Task Management | 0x803c | 0x8025-0x8026 |
37 * | | | 0x800b,0x8039 |
38 * | AER/EEH | 0x9011 | |
39 * | Virtual Port | 0xa007 | |
40 * | ISP82XX Specific | 0xb086 | 0xb002,0xb024 |
41 * | MultiQ | 0xc00c | |
43 * | Target Mode | 0xe070 | |
44 * | Target Mode Management | 0xf072 | |
45 * | Target Mode Task Management | 0x1000b | |
46 * ----------------------------------------------------------------------
51 #include <linux/delay.h>
53 static uint32_t ql_dbg_offset = 0x800;
56 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
58 fw_dump->fw_major_version = htonl(ha->fw_major_version);
59 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
60 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
61 fw_dump->fw_attributes = htonl(ha->fw_attributes);
63 fw_dump->vendor = htonl(ha->pdev->vendor);
64 fw_dump->device = htonl(ha->pdev->device);
65 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
66 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
70 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
72 struct req_que *req = ha->req_q_map[0];
73 struct rsp_que *rsp = ha->rsp_q_map[0];
75 memcpy(ptr, req->ring, req->length *
79 ptr += req->length * sizeof(request_t);
80 memcpy(ptr, rsp->ring, rsp->length *
83 return ptr + (rsp->length * sizeof(response_t));
87 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
88 uint32_t ram_dwords, void **nxt)
91 uint32_t cnt, stat, timer, dwords, idx;
93 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
94 dma_addr_t dump_dma = ha->gid_list_dma;
95 uint32_t *dump = (uint32_t *)ha->gid_list;
100 WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
101 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
103 dwords = qla2x00_gid_list_size(ha) / 4;
104 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
105 cnt += dwords, addr += dwords) {
106 if (cnt + dwords > ram_dwords)
107 dwords = ram_dwords - cnt;
109 WRT_REG_WORD(®->mailbox1, LSW(addr));
110 WRT_REG_WORD(®->mailbox8, MSW(addr));
112 WRT_REG_WORD(®->mailbox2, MSW(dump_dma));
113 WRT_REG_WORD(®->mailbox3, LSW(dump_dma));
114 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma)));
115 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma)));
117 WRT_REG_WORD(®->mailbox4, MSW(dwords));
118 WRT_REG_WORD(®->mailbox5, LSW(dwords));
119 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
121 for (timer = 6000000; timer; timer--) {
122 /* Check for pending interrupts. */
123 stat = RD_REG_DWORD(®->host_status);
124 if (stat & HSRX_RISC_INT) {
127 if (stat == 0x1 || stat == 0x2 ||
128 stat == 0x10 || stat == 0x11) {
129 set_bit(MBX_INTERRUPT,
132 mb0 = RD_REG_WORD(®->mailbox0);
134 WRT_REG_DWORD(®->hccr,
136 RD_REG_DWORD(®->hccr);
140 /* Clear this intr; it wasn't a mailbox intr */
141 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
142 RD_REG_DWORD(®->hccr);
147 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
148 rval = mb0 & MBS_MASK;
149 for (idx = 0; idx < dwords; idx++)
150 ram[cnt + idx] = swab32(dump[idx]);
152 rval = QLA_FUNCTION_FAILED;
156 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
161 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
162 uint32_t cram_size, void **nxt)
167 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
168 if (rval != QLA_SUCCESS)
171 /* External Memory. */
172 return qla24xx_dump_ram(ha, 0x100000, *nxt,
173 ha->fw_memory_size - 0x100000 + 1, nxt);
177 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
178 uint32_t count, uint32_t *buf)
180 uint32_t __iomem *dmp_reg;
182 WRT_REG_DWORD(®->iobase_addr, iobase);
183 dmp_reg = ®->iobase_window;
185 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
191 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
193 int rval = QLA_SUCCESS;
196 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
198 ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) &&
199 rval == QLA_SUCCESS; cnt--) {
203 rval = QLA_FUNCTION_TIMEOUT;
210 qla24xx_soft_reset(struct qla_hw_data *ha)
212 int rval = QLA_SUCCESS;
215 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
218 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
219 for (cnt = 0; cnt < 30000; cnt++) {
220 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
226 WRT_REG_DWORD(®->ctrl_status,
227 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
228 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
231 /* Wait for firmware to complete NVRAM accesses. */
232 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
233 for (cnt = 10000 ; cnt && mb0; cnt--) {
235 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
239 /* Wait for soft-reset to complete. */
240 for (cnt = 0; cnt < 30000; cnt++) {
241 if ((RD_REG_DWORD(®->ctrl_status) &
242 CSRX_ISP_SOFT_RESET) == 0)
247 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
248 RD_REG_DWORD(®->hccr); /* PCI Posting. */
250 for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 &&
251 rval == QLA_SUCCESS; cnt--) {
255 rval = QLA_FUNCTION_TIMEOUT;
262 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
263 uint32_t ram_words, void **nxt)
266 uint32_t cnt, stat, timer, words, idx;
268 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
269 dma_addr_t dump_dma = ha->gid_list_dma;
270 uint16_t *dump = (uint16_t *)ha->gid_list;
275 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
276 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
278 words = qla2x00_gid_list_size(ha) / 2;
279 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
280 cnt += words, addr += words) {
281 if (cnt + words > ram_words)
282 words = ram_words - cnt;
284 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
285 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
287 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
288 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
289 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
290 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
292 WRT_MAILBOX_REG(ha, reg, 4, words);
293 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
295 for (timer = 6000000; timer; timer--) {
296 /* Check for pending interrupts. */
297 stat = RD_REG_DWORD(®->u.isp2300.host_status);
298 if (stat & HSR_RISC_INT) {
301 if (stat == 0x1 || stat == 0x2) {
302 set_bit(MBX_INTERRUPT,
305 mb0 = RD_MAILBOX_REG(ha, reg, 0);
307 /* Release mailbox registers. */
308 WRT_REG_WORD(®->semaphore, 0);
309 WRT_REG_WORD(®->hccr,
311 RD_REG_WORD(®->hccr);
313 } else if (stat == 0x10 || stat == 0x11) {
314 set_bit(MBX_INTERRUPT,
317 mb0 = RD_MAILBOX_REG(ha, reg, 0);
319 WRT_REG_WORD(®->hccr,
321 RD_REG_WORD(®->hccr);
325 /* clear this intr; it wasn't a mailbox intr */
326 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
327 RD_REG_WORD(®->hccr);
332 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
333 rval = mb0 & MBS_MASK;
334 for (idx = 0; idx < words; idx++)
335 ram[cnt + idx] = swab16(dump[idx]);
337 rval = QLA_FUNCTION_FAILED;
341 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
346 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
349 uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd;
352 *buf++ = htons(RD_REG_WORD(dmp_reg++));
356 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
361 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
362 return ptr + ntohl(ha->fw_dump->eft_size);
366 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
370 struct qla2xxx_fce_chain *fcec = ptr;
375 *last_chain = &fcec->type;
376 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
377 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
378 fce_calc_size(ha->fce_bufs));
379 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
380 fcec->addr_l = htonl(LSD(ha->fce_dma));
381 fcec->addr_h = htonl(MSD(ha->fce_dma));
383 iter_reg = fcec->eregs;
384 for (cnt = 0; cnt < 8; cnt++)
385 *iter_reg++ = htonl(ha->fce_mb[cnt]);
387 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
389 return (char *)iter_reg + ntohl(fcec->size);
393 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
394 uint32_t **last_chain)
396 struct qla2xxx_mqueue_chain *q;
397 struct qla2xxx_mqueue_header *qh;
405 if (!ha->tgt.atio_ring)
410 aqp->length = ha->tgt.atio_q_length;
411 aqp->ring = ha->tgt.atio_ring;
413 for (que = 0; que < num_queues; que++) {
414 /* aqp = ha->atio_q_map[que]; */
416 *last_chain = &q->type;
417 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
418 q->chain_size = htonl(
419 sizeof(struct qla2xxx_mqueue_chain) +
420 sizeof(struct qla2xxx_mqueue_header) +
421 (aqp->length * sizeof(request_t)));
422 ptr += sizeof(struct qla2xxx_mqueue_chain);
426 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
427 qh->number = htonl(que);
428 qh->size = htonl(aqp->length * sizeof(request_t));
429 ptr += sizeof(struct qla2xxx_mqueue_header);
432 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
434 ptr += aqp->length * sizeof(request_t);
441 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
443 struct qla2xxx_mqueue_chain *q;
444 struct qla2xxx_mqueue_header *qh;
453 for (que = 1; que < ha->max_req_queues; que++) {
454 req = ha->req_q_map[que];
460 *last_chain = &q->type;
461 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
462 q->chain_size = htonl(
463 sizeof(struct qla2xxx_mqueue_chain) +
464 sizeof(struct qla2xxx_mqueue_header) +
465 (req->length * sizeof(request_t)));
466 ptr += sizeof(struct qla2xxx_mqueue_chain);
470 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
471 qh->number = htonl(que);
472 qh->size = htonl(req->length * sizeof(request_t));
473 ptr += sizeof(struct qla2xxx_mqueue_header);
476 memcpy(ptr, req->ring, req->length * sizeof(request_t));
477 ptr += req->length * sizeof(request_t);
480 /* Response queues */
481 for (que = 1; que < ha->max_rsp_queues; que++) {
482 rsp = ha->rsp_q_map[que];
488 *last_chain = &q->type;
489 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
490 q->chain_size = htonl(
491 sizeof(struct qla2xxx_mqueue_chain) +
492 sizeof(struct qla2xxx_mqueue_header) +
493 (rsp->length * sizeof(response_t)));
494 ptr += sizeof(struct qla2xxx_mqueue_chain);
498 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
499 qh->number = htonl(que);
500 qh->size = htonl(rsp->length * sizeof(response_t));
501 ptr += sizeof(struct qla2xxx_mqueue_header);
504 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
505 ptr += rsp->length * sizeof(response_t);
512 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
514 uint32_t cnt, que_idx;
516 struct qla2xxx_mq_chain *mq = ptr;
517 struct device_reg_25xxmq __iomem *reg;
519 if (!ha->mqenable || IS_QLA83XX(ha))
523 *last_chain = &mq->type;
524 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
525 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
527 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
528 ha->max_req_queues : ha->max_rsp_queues;
529 mq->count = htonl(que_cnt);
530 for (cnt = 0; cnt < que_cnt; cnt++) {
531 reg = (struct device_reg_25xxmq __iomem *)
532 (ha->mqiobase + cnt * QLA_QUE_PAGE);
534 mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in));
535 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(®->req_q_out));
536 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(®->rsp_q_in));
537 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(®->rsp_q_out));
540 return ptr + sizeof(struct qla2xxx_mq_chain);
544 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
546 struct qla_hw_data *ha = vha->hw;
548 if (rval != QLA_SUCCESS) {
549 ql_log(ql_log_warn, vha, 0xd000,
550 "Failed to dump firmware (%x).\n", rval);
553 ql_log(ql_log_info, vha, 0xd001,
554 "Firmware dump saved to temp buffer (%ld/%p).\n",
555 vha->host_no, ha->fw_dump);
557 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
562 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
564 * @hardware_locked: Called with the hardware_lock
567 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
571 struct qla_hw_data *ha = vha->hw;
572 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
573 uint16_t __iomem *dmp_reg;
575 struct qla2300_fw_dump *fw;
577 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
581 if (!hardware_locked)
582 spin_lock_irqsave(&ha->hardware_lock, flags);
585 ql_log(ql_log_warn, vha, 0xd002,
586 "No buffer available for dump.\n");
587 goto qla2300_fw_dump_failed;
591 ql_log(ql_log_warn, vha, 0xd003,
592 "Firmware has been previously dumped (%p) "
593 "-- ignoring request.\n",
595 goto qla2300_fw_dump_failed;
597 fw = &ha->fw_dump->isp.isp23;
598 qla2xxx_prep_dump(ha, ha->fw_dump);
601 fw->hccr = htons(RD_REG_WORD(®->hccr));
604 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
605 if (IS_QLA2300(ha)) {
607 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
608 rval == QLA_SUCCESS; cnt--) {
612 rval = QLA_FUNCTION_TIMEOUT;
615 RD_REG_WORD(®->hccr); /* PCI Posting. */
619 if (rval == QLA_SUCCESS) {
620 dmp_reg = ®->flash_address;
621 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
622 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
624 dmp_reg = ®->u.isp2300.req_q_in;
625 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
626 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
628 dmp_reg = ®->u.isp2300.mailbox0;
629 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
630 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
632 WRT_REG_WORD(®->ctrl_status, 0x40);
633 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
635 WRT_REG_WORD(®->ctrl_status, 0x50);
636 qla2xxx_read_window(reg, 48, fw->dma_reg);
638 WRT_REG_WORD(®->ctrl_status, 0x00);
639 dmp_reg = ®->risc_hw;
640 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
641 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
643 WRT_REG_WORD(®->pcr, 0x2000);
644 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
646 WRT_REG_WORD(®->pcr, 0x2200);
647 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
649 WRT_REG_WORD(®->pcr, 0x2400);
650 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
652 WRT_REG_WORD(®->pcr, 0x2600);
653 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
655 WRT_REG_WORD(®->pcr, 0x2800);
656 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
658 WRT_REG_WORD(®->pcr, 0x2A00);
659 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
661 WRT_REG_WORD(®->pcr, 0x2C00);
662 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
664 WRT_REG_WORD(®->pcr, 0x2E00);
665 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
667 WRT_REG_WORD(®->ctrl_status, 0x10);
668 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
670 WRT_REG_WORD(®->ctrl_status, 0x20);
671 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
673 WRT_REG_WORD(®->ctrl_status, 0x30);
674 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
677 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
678 for (cnt = 0; cnt < 30000; cnt++) {
679 if ((RD_REG_WORD(®->ctrl_status) &
680 CSR_ISP_SOFT_RESET) == 0)
687 if (!IS_QLA2300(ha)) {
688 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
689 rval == QLA_SUCCESS; cnt--) {
693 rval = QLA_FUNCTION_TIMEOUT;
698 if (rval == QLA_SUCCESS)
699 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
700 sizeof(fw->risc_ram) / 2, &nxt);
702 /* Get stack SRAM. */
703 if (rval == QLA_SUCCESS)
704 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
705 sizeof(fw->stack_ram) / 2, &nxt);
708 if (rval == QLA_SUCCESS)
709 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
710 ha->fw_memory_size - 0x11000 + 1, &nxt);
712 if (rval == QLA_SUCCESS)
713 qla2xxx_copy_queues(ha, nxt);
715 qla2xxx_dump_post_process(base_vha, rval);
717 qla2300_fw_dump_failed:
718 if (!hardware_locked)
719 spin_unlock_irqrestore(&ha->hardware_lock, flags);
723 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
725 * @hardware_locked: Called with the hardware_lock
728 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
732 uint16_t risc_address;
734 struct qla_hw_data *ha = vha->hw;
735 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
736 uint16_t __iomem *dmp_reg;
738 struct qla2100_fw_dump *fw;
739 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
745 if (!hardware_locked)
746 spin_lock_irqsave(&ha->hardware_lock, flags);
749 ql_log(ql_log_warn, vha, 0xd004,
750 "No buffer available for dump.\n");
751 goto qla2100_fw_dump_failed;
755 ql_log(ql_log_warn, vha, 0xd005,
756 "Firmware has been previously dumped (%p) "
757 "-- ignoring request.\n",
759 goto qla2100_fw_dump_failed;
761 fw = &ha->fw_dump->isp.isp21;
762 qla2xxx_prep_dump(ha, ha->fw_dump);
765 fw->hccr = htons(RD_REG_WORD(®->hccr));
768 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
769 for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
770 rval == QLA_SUCCESS; cnt--) {
774 rval = QLA_FUNCTION_TIMEOUT;
776 if (rval == QLA_SUCCESS) {
777 dmp_reg = ®->flash_address;
778 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
779 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
781 dmp_reg = ®->u.isp2100.mailbox0;
782 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
784 dmp_reg = ®->u_end.isp2200.mailbox8;
786 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
789 dmp_reg = ®->u.isp2100.unused_2[0];
790 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
791 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
793 WRT_REG_WORD(®->ctrl_status, 0x00);
794 dmp_reg = ®->risc_hw;
795 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
796 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
798 WRT_REG_WORD(®->pcr, 0x2000);
799 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
801 WRT_REG_WORD(®->pcr, 0x2100);
802 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
804 WRT_REG_WORD(®->pcr, 0x2200);
805 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
807 WRT_REG_WORD(®->pcr, 0x2300);
808 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
810 WRT_REG_WORD(®->pcr, 0x2400);
811 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
813 WRT_REG_WORD(®->pcr, 0x2500);
814 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
816 WRT_REG_WORD(®->pcr, 0x2600);
817 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
819 WRT_REG_WORD(®->pcr, 0x2700);
820 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
822 WRT_REG_WORD(®->ctrl_status, 0x10);
823 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
825 WRT_REG_WORD(®->ctrl_status, 0x20);
826 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
828 WRT_REG_WORD(®->ctrl_status, 0x30);
829 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
832 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
835 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
836 rval == QLA_SUCCESS; cnt--) {
840 rval = QLA_FUNCTION_TIMEOUT;
844 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
845 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) {
847 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
849 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
850 rval == QLA_SUCCESS; cnt--) {
854 rval = QLA_FUNCTION_TIMEOUT;
856 if (rval == QLA_SUCCESS) {
857 /* Set memory configuration and timing. */
859 WRT_REG_WORD(®->mctr, 0xf1);
861 WRT_REG_WORD(®->mctr, 0xf2);
862 RD_REG_WORD(®->mctr); /* PCI Posting. */
865 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
869 if (rval == QLA_SUCCESS) {
871 risc_address = 0x1000;
872 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
873 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
875 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
876 cnt++, risc_address++) {
877 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
878 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
880 for (timer = 6000000; timer != 0; timer--) {
881 /* Check for pending interrupts. */
882 if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) {
883 if (RD_REG_WORD(®->semaphore) & BIT_0) {
884 set_bit(MBX_INTERRUPT,
887 mb0 = RD_MAILBOX_REG(ha, reg, 0);
888 mb2 = RD_MAILBOX_REG(ha, reg, 2);
890 WRT_REG_WORD(®->semaphore, 0);
891 WRT_REG_WORD(®->hccr,
893 RD_REG_WORD(®->hccr);
896 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
897 RD_REG_WORD(®->hccr);
902 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
903 rval = mb0 & MBS_MASK;
904 fw->risc_ram[cnt] = htons(mb2);
906 rval = QLA_FUNCTION_FAILED;
910 if (rval == QLA_SUCCESS)
911 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
913 qla2xxx_dump_post_process(base_vha, rval);
915 qla2100_fw_dump_failed:
916 if (!hardware_locked)
917 spin_unlock_irqrestore(&ha->hardware_lock, flags);
921 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
925 uint32_t risc_address;
926 struct qla_hw_data *ha = vha->hw;
927 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
928 uint32_t __iomem *dmp_reg;
930 uint16_t __iomem *mbx_reg;
932 struct qla24xx_fw_dump *fw;
933 uint32_t ext_mem_cnt;
936 uint32_t *last_chain = NULL;
937 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
942 risc_address = ext_mem_cnt = 0;
945 if (!hardware_locked)
946 spin_lock_irqsave(&ha->hardware_lock, flags);
949 ql_log(ql_log_warn, vha, 0xd006,
950 "No buffer available for dump.\n");
951 goto qla24xx_fw_dump_failed;
955 ql_log(ql_log_warn, vha, 0xd007,
956 "Firmware has been previously dumped (%p) "
957 "-- ignoring request.\n",
959 goto qla24xx_fw_dump_failed;
961 fw = &ha->fw_dump->isp.isp24;
962 qla2xxx_prep_dump(ha, ha->fw_dump);
964 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
967 rval = qla24xx_pause_risc(reg);
968 if (rval != QLA_SUCCESS)
969 goto qla24xx_fw_dump_failed_0;
971 /* Host interface registers. */
972 dmp_reg = ®->flash_addr;
973 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
974 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
976 /* Disable interrupts. */
977 WRT_REG_DWORD(®->ictrl, 0);
978 RD_REG_DWORD(®->ictrl);
980 /* Shadow registers. */
981 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
982 RD_REG_DWORD(®->iobase_addr);
983 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
984 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
986 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
987 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
989 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
990 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
992 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
993 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
995 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
996 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
998 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
999 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1001 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1002 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1004 /* Mailbox registers. */
1005 mbx_reg = ®->mailbox0;
1006 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1007 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1009 /* Transfer sequence registers. */
1010 iter_reg = fw->xseq_gp_reg;
1011 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1012 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1013 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1014 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1015 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1016 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1017 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1018 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1020 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
1021 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1023 /* Receive sequence registers. */
1024 iter_reg = fw->rseq_gp_reg;
1025 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1026 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1027 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1028 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1029 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1030 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1031 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1032 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1034 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
1035 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1036 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1038 /* Command DMA registers. */
1039 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1042 iter_reg = fw->req0_dma_reg;
1043 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1044 dmp_reg = ®->iobase_q;
1045 for (cnt = 0; cnt < 7; cnt++)
1046 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1048 iter_reg = fw->resp0_dma_reg;
1049 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1050 dmp_reg = ®->iobase_q;
1051 for (cnt = 0; cnt < 7; cnt++)
1052 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1054 iter_reg = fw->req1_dma_reg;
1055 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1056 dmp_reg = ®->iobase_q;
1057 for (cnt = 0; cnt < 7; cnt++)
1058 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1060 /* Transmit DMA registers. */
1061 iter_reg = fw->xmt0_dma_reg;
1062 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1063 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1065 iter_reg = fw->xmt1_dma_reg;
1066 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1067 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1069 iter_reg = fw->xmt2_dma_reg;
1070 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1071 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1073 iter_reg = fw->xmt3_dma_reg;
1074 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1075 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1077 iter_reg = fw->xmt4_dma_reg;
1078 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1079 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1081 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1083 /* Receive DMA registers. */
1084 iter_reg = fw->rcvt0_data_dma_reg;
1085 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1086 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1088 iter_reg = fw->rcvt1_data_dma_reg;
1089 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1090 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1092 /* RISC registers. */
1093 iter_reg = fw->risc_gp_reg;
1094 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1095 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1096 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1097 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1098 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1099 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1100 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1101 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1103 /* Local memory controller registers. */
1104 iter_reg = fw->lmc_reg;
1105 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1106 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1107 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1108 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1109 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1110 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1111 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1113 /* Fibre Protocol Module registers. */
1114 iter_reg = fw->fpm_hdw_reg;
1115 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1116 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1117 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1118 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1119 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1120 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1121 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1122 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1123 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1124 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1125 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1126 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1128 /* Frame Buffer registers. */
1129 iter_reg = fw->fb_hdw_reg;
1130 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1131 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1132 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1133 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1134 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1135 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1136 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1137 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1138 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1139 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1140 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1142 rval = qla24xx_soft_reset(ha);
1143 if (rval != QLA_SUCCESS)
1144 goto qla24xx_fw_dump_failed_0;
1146 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1148 if (rval != QLA_SUCCESS)
1149 goto qla24xx_fw_dump_failed_0;
1151 nxt = qla2xxx_copy_queues(ha, nxt);
1153 qla24xx_copy_eft(ha, nxt);
1155 nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1156 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1158 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1159 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1162 /* Adjust valid length. */
1163 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1165 qla24xx_fw_dump_failed_0:
1166 qla2xxx_dump_post_process(base_vha, rval);
1168 qla24xx_fw_dump_failed:
1169 if (!hardware_locked)
1170 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1174 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1178 uint32_t risc_address;
1179 struct qla_hw_data *ha = vha->hw;
1180 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1181 uint32_t __iomem *dmp_reg;
1183 uint16_t __iomem *mbx_reg;
1184 unsigned long flags;
1185 struct qla25xx_fw_dump *fw;
1186 uint32_t ext_mem_cnt;
1187 void *nxt, *nxt_chain;
1188 uint32_t *last_chain = NULL;
1189 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1191 risc_address = ext_mem_cnt = 0;
1194 if (!hardware_locked)
1195 spin_lock_irqsave(&ha->hardware_lock, flags);
1198 ql_log(ql_log_warn, vha, 0xd008,
1199 "No buffer available for dump.\n");
1200 goto qla25xx_fw_dump_failed;
1203 if (ha->fw_dumped) {
1204 ql_log(ql_log_warn, vha, 0xd009,
1205 "Firmware has been previously dumped (%p) "
1206 "-- ignoring request.\n",
1208 goto qla25xx_fw_dump_failed;
1210 fw = &ha->fw_dump->isp.isp25;
1211 qla2xxx_prep_dump(ha, ha->fw_dump);
1212 ha->fw_dump->version = __constant_htonl(2);
1214 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
1217 rval = qla24xx_pause_risc(reg);
1218 if (rval != QLA_SUCCESS)
1219 goto qla25xx_fw_dump_failed_0;
1221 /* Host/Risc registers. */
1222 iter_reg = fw->host_risc_reg;
1223 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1224 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1226 /* PCIe registers. */
1227 WRT_REG_DWORD(®->iobase_addr, 0x7C00);
1228 RD_REG_DWORD(®->iobase_addr);
1229 WRT_REG_DWORD(®->iobase_window, 0x01);
1230 dmp_reg = ®->iobase_c4;
1231 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1232 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1233 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1234 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
1236 WRT_REG_DWORD(®->iobase_window, 0x00);
1237 RD_REG_DWORD(®->iobase_window);
1239 /* Host interface registers. */
1240 dmp_reg = ®->flash_addr;
1241 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1242 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1244 /* Disable interrupts. */
1245 WRT_REG_DWORD(®->ictrl, 0);
1246 RD_REG_DWORD(®->ictrl);
1248 /* Shadow registers. */
1249 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1250 RD_REG_DWORD(®->iobase_addr);
1251 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
1252 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
1254 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
1255 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
1257 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
1258 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
1260 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
1261 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
1263 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
1264 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
1266 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
1267 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1269 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1270 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1272 WRT_REG_DWORD(®->iobase_select, 0xB0700000);
1273 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
1275 WRT_REG_DWORD(®->iobase_select, 0xB0800000);
1276 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
1278 WRT_REG_DWORD(®->iobase_select, 0xB0900000);
1279 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
1281 WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
1282 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
1284 /* RISC I/O register. */
1285 WRT_REG_DWORD(®->iobase_addr, 0x0010);
1286 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
1288 /* Mailbox registers. */
1289 mbx_reg = ®->mailbox0;
1290 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1291 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1293 /* Transfer sequence registers. */
1294 iter_reg = fw->xseq_gp_reg;
1295 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1296 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1297 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1298 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1299 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1300 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1301 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1302 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1304 iter_reg = fw->xseq_0_reg;
1305 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1306 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1307 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1309 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1311 /* Receive sequence registers. */
1312 iter_reg = fw->rseq_gp_reg;
1313 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1314 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1315 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1316 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1317 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1318 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1319 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1320 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1322 iter_reg = fw->rseq_0_reg;
1323 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1324 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1326 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1327 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1329 /* Auxiliary sequence registers. */
1330 iter_reg = fw->aseq_gp_reg;
1331 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1332 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1333 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1334 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1335 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1336 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1337 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1338 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1340 iter_reg = fw->aseq_0_reg;
1341 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1342 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1344 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1345 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1347 /* Command DMA registers. */
1348 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1351 iter_reg = fw->req0_dma_reg;
1352 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1353 dmp_reg = ®->iobase_q;
1354 for (cnt = 0; cnt < 7; cnt++)
1355 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1357 iter_reg = fw->resp0_dma_reg;
1358 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1359 dmp_reg = ®->iobase_q;
1360 for (cnt = 0; cnt < 7; cnt++)
1361 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1363 iter_reg = fw->req1_dma_reg;
1364 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1365 dmp_reg = ®->iobase_q;
1366 for (cnt = 0; cnt < 7; cnt++)
1367 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1369 /* Transmit DMA registers. */
1370 iter_reg = fw->xmt0_dma_reg;
1371 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1372 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1374 iter_reg = fw->xmt1_dma_reg;
1375 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1376 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1378 iter_reg = fw->xmt2_dma_reg;
1379 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1380 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1382 iter_reg = fw->xmt3_dma_reg;
1383 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1384 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1386 iter_reg = fw->xmt4_dma_reg;
1387 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1388 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1390 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1392 /* Receive DMA registers. */
1393 iter_reg = fw->rcvt0_data_dma_reg;
1394 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1395 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1397 iter_reg = fw->rcvt1_data_dma_reg;
1398 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1399 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1401 /* RISC registers. */
1402 iter_reg = fw->risc_gp_reg;
1403 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1404 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1405 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1406 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1407 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1408 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1409 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1410 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1412 /* Local memory controller registers. */
1413 iter_reg = fw->lmc_reg;
1414 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1415 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1416 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1417 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1418 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1419 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1420 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1421 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1423 /* Fibre Protocol Module registers. */
1424 iter_reg = fw->fpm_hdw_reg;
1425 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1426 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1427 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1428 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1429 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1430 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1431 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1432 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1433 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1434 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1435 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1436 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1438 /* Frame Buffer registers. */
1439 iter_reg = fw->fb_hdw_reg;
1440 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1441 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1442 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1443 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1444 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1445 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1446 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1447 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1448 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1449 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1450 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1451 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1453 /* Multi queue registers */
1454 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1457 rval = qla24xx_soft_reset(ha);
1458 if (rval != QLA_SUCCESS)
1459 goto qla25xx_fw_dump_failed_0;
1461 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1463 if (rval != QLA_SUCCESS)
1464 goto qla25xx_fw_dump_failed_0;
1466 nxt = qla2xxx_copy_queues(ha, nxt);
1468 nxt = qla24xx_copy_eft(ha, nxt);
1470 /* Chain entries -- started with MQ. */
1471 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1472 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1473 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1475 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1476 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1479 /* Adjust valid length. */
1480 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1482 qla25xx_fw_dump_failed_0:
1483 qla2xxx_dump_post_process(base_vha, rval);
1485 qla25xx_fw_dump_failed:
1486 if (!hardware_locked)
1487 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1491 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1495 uint32_t risc_address;
1496 struct qla_hw_data *ha = vha->hw;
1497 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1498 uint32_t __iomem *dmp_reg;
1500 uint16_t __iomem *mbx_reg;
1501 unsigned long flags;
1502 struct qla81xx_fw_dump *fw;
1503 uint32_t ext_mem_cnt;
1504 void *nxt, *nxt_chain;
1505 uint32_t *last_chain = NULL;
1506 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1508 risc_address = ext_mem_cnt = 0;
1511 if (!hardware_locked)
1512 spin_lock_irqsave(&ha->hardware_lock, flags);
1515 ql_log(ql_log_warn, vha, 0xd00a,
1516 "No buffer available for dump.\n");
1517 goto qla81xx_fw_dump_failed;
1520 if (ha->fw_dumped) {
1521 ql_log(ql_log_warn, vha, 0xd00b,
1522 "Firmware has been previously dumped (%p) "
1523 "-- ignoring request.\n",
1525 goto qla81xx_fw_dump_failed;
1527 fw = &ha->fw_dump->isp.isp81;
1528 qla2xxx_prep_dump(ha, ha->fw_dump);
1530 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
1533 rval = qla24xx_pause_risc(reg);
1534 if (rval != QLA_SUCCESS)
1535 goto qla81xx_fw_dump_failed_0;
1537 /* Host/Risc registers. */
1538 iter_reg = fw->host_risc_reg;
1539 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1540 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1542 /* PCIe registers. */
1543 WRT_REG_DWORD(®->iobase_addr, 0x7C00);
1544 RD_REG_DWORD(®->iobase_addr);
1545 WRT_REG_DWORD(®->iobase_window, 0x01);
1546 dmp_reg = ®->iobase_c4;
1547 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1548 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1549 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1550 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
1552 WRT_REG_DWORD(®->iobase_window, 0x00);
1553 RD_REG_DWORD(®->iobase_window);
1555 /* Host interface registers. */
1556 dmp_reg = ®->flash_addr;
1557 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1558 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1560 /* Disable interrupts. */
1561 WRT_REG_DWORD(®->ictrl, 0);
1562 RD_REG_DWORD(®->ictrl);
1564 /* Shadow registers. */
1565 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1566 RD_REG_DWORD(®->iobase_addr);
1567 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
1568 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
1570 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
1571 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
1573 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
1574 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
1576 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
1577 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
1579 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
1580 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
1582 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
1583 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1585 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1586 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1588 WRT_REG_DWORD(®->iobase_select, 0xB0700000);
1589 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
1591 WRT_REG_DWORD(®->iobase_select, 0xB0800000);
1592 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
1594 WRT_REG_DWORD(®->iobase_select, 0xB0900000);
1595 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
1597 WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
1598 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
1600 /* RISC I/O register. */
1601 WRT_REG_DWORD(®->iobase_addr, 0x0010);
1602 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
1604 /* Mailbox registers. */
1605 mbx_reg = ®->mailbox0;
1606 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1607 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1609 /* Transfer sequence registers. */
1610 iter_reg = fw->xseq_gp_reg;
1611 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1612 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1613 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1614 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1615 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1616 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1617 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1618 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1620 iter_reg = fw->xseq_0_reg;
1621 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1622 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1623 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1625 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1627 /* Receive sequence registers. */
1628 iter_reg = fw->rseq_gp_reg;
1629 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1630 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1631 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1632 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1633 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1634 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1635 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1636 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1638 iter_reg = fw->rseq_0_reg;
1639 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1640 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1642 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1643 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1645 /* Auxiliary sequence registers. */
1646 iter_reg = fw->aseq_gp_reg;
1647 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1648 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1649 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1650 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1651 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1652 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1653 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1654 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1656 iter_reg = fw->aseq_0_reg;
1657 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1658 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1660 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1661 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1663 /* Command DMA registers. */
1664 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1667 iter_reg = fw->req0_dma_reg;
1668 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1669 dmp_reg = ®->iobase_q;
1670 for (cnt = 0; cnt < 7; cnt++)
1671 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1673 iter_reg = fw->resp0_dma_reg;
1674 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1675 dmp_reg = ®->iobase_q;
1676 for (cnt = 0; cnt < 7; cnt++)
1677 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1679 iter_reg = fw->req1_dma_reg;
1680 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1681 dmp_reg = ®->iobase_q;
1682 for (cnt = 0; cnt < 7; cnt++)
1683 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1685 /* Transmit DMA registers. */
1686 iter_reg = fw->xmt0_dma_reg;
1687 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1688 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1690 iter_reg = fw->xmt1_dma_reg;
1691 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1692 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1694 iter_reg = fw->xmt2_dma_reg;
1695 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1696 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1698 iter_reg = fw->xmt3_dma_reg;
1699 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1700 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1702 iter_reg = fw->xmt4_dma_reg;
1703 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1704 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1706 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1708 /* Receive DMA registers. */
1709 iter_reg = fw->rcvt0_data_dma_reg;
1710 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1711 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1713 iter_reg = fw->rcvt1_data_dma_reg;
1714 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1715 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1717 /* RISC registers. */
1718 iter_reg = fw->risc_gp_reg;
1719 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1720 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1721 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1722 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1723 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1724 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1725 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1726 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1728 /* Local memory controller registers. */
1729 iter_reg = fw->lmc_reg;
1730 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1731 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1732 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1733 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1734 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1735 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1736 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1737 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1739 /* Fibre Protocol Module registers. */
1740 iter_reg = fw->fpm_hdw_reg;
1741 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1742 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1743 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1744 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1745 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1746 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1747 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1748 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1749 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1750 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1751 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1752 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1753 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1754 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1756 /* Frame Buffer registers. */
1757 iter_reg = fw->fb_hdw_reg;
1758 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1759 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1760 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1761 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1762 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1763 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1764 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1765 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1766 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1767 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1768 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1769 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1770 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1772 /* Multi queue registers */
1773 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1776 rval = qla24xx_soft_reset(ha);
1777 if (rval != QLA_SUCCESS)
1778 goto qla81xx_fw_dump_failed_0;
1780 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1782 if (rval != QLA_SUCCESS)
1783 goto qla81xx_fw_dump_failed_0;
1785 nxt = qla2xxx_copy_queues(ha, nxt);
1787 nxt = qla24xx_copy_eft(ha, nxt);
1789 /* Chain entries -- started with MQ. */
1790 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1791 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1792 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1794 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1795 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1798 /* Adjust valid length. */
1799 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1801 qla81xx_fw_dump_failed_0:
1802 qla2xxx_dump_post_process(base_vha, rval);
1804 qla81xx_fw_dump_failed:
1805 if (!hardware_locked)
1806 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1810 qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1813 uint32_t cnt, reg_data;
1814 uint32_t risc_address;
1815 struct qla_hw_data *ha = vha->hw;
1816 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1817 uint32_t __iomem *dmp_reg;
1819 uint16_t __iomem *mbx_reg;
1820 unsigned long flags;
1821 struct qla83xx_fw_dump *fw;
1822 uint32_t ext_mem_cnt;
1823 void *nxt, *nxt_chain;
1824 uint32_t *last_chain = NULL;
1825 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1827 risc_address = ext_mem_cnt = 0;
1830 if (!hardware_locked)
1831 spin_lock_irqsave(&ha->hardware_lock, flags);
1834 ql_log(ql_log_warn, vha, 0xd00c,
1835 "No buffer available for dump!!!\n");
1836 goto qla83xx_fw_dump_failed;
1839 if (ha->fw_dumped) {
1840 ql_log(ql_log_warn, vha, 0xd00d,
1841 "Firmware has been previously dumped (%p) -- ignoring "
1842 "request...\n", ha->fw_dump);
1843 goto qla83xx_fw_dump_failed;
1845 fw = &ha->fw_dump->isp.isp83;
1846 qla2xxx_prep_dump(ha, ha->fw_dump);
1848 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
1851 rval = qla24xx_pause_risc(reg);
1852 if (rval != QLA_SUCCESS)
1853 goto qla83xx_fw_dump_failed_0;
1855 WRT_REG_DWORD(®->iobase_addr, 0x6000);
1856 dmp_reg = ®->iobase_window;
1857 reg_data = RD_REG_DWORD(dmp_reg);
1858 WRT_REG_DWORD(dmp_reg, 0);
1860 dmp_reg = ®->unused_4_1[0];
1861 reg_data = RD_REG_DWORD(dmp_reg);
1862 WRT_REG_DWORD(dmp_reg, 0);
1864 WRT_REG_DWORD(®->iobase_addr, 0x6010);
1865 dmp_reg = ®->unused_4_1[2];
1866 reg_data = RD_REG_DWORD(dmp_reg);
1867 WRT_REG_DWORD(dmp_reg, 0);
1869 /* select PCR and disable ecc checking and correction */
1870 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1871 RD_REG_DWORD(®->iobase_addr);
1872 WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */
1874 /* Host/Risc registers. */
1875 iter_reg = fw->host_risc_reg;
1876 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1877 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1878 qla24xx_read_window(reg, 0x7040, 16, iter_reg);
1880 /* PCIe registers. */
1881 WRT_REG_DWORD(®->iobase_addr, 0x7C00);
1882 RD_REG_DWORD(®->iobase_addr);
1883 WRT_REG_DWORD(®->iobase_window, 0x01);
1884 dmp_reg = ®->iobase_c4;
1885 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1886 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1887 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1888 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
1890 WRT_REG_DWORD(®->iobase_window, 0x00);
1891 RD_REG_DWORD(®->iobase_window);
1893 /* Host interface registers. */
1894 dmp_reg = ®->flash_addr;
1895 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1896 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1898 /* Disable interrupts. */
1899 WRT_REG_DWORD(®->ictrl, 0);
1900 RD_REG_DWORD(®->ictrl);
1902 /* Shadow registers. */
1903 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1904 RD_REG_DWORD(®->iobase_addr);
1905 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
1906 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
1908 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
1909 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
1911 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
1912 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
1914 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
1915 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
1917 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
1918 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
1920 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
1921 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1923 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1924 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1926 WRT_REG_DWORD(®->iobase_select, 0xB0700000);
1927 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
1929 WRT_REG_DWORD(®->iobase_select, 0xB0800000);
1930 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
1932 WRT_REG_DWORD(®->iobase_select, 0xB0900000);
1933 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
1935 WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
1936 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
1938 /* RISC I/O register. */
1939 WRT_REG_DWORD(®->iobase_addr, 0x0010);
1940 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
1942 /* Mailbox registers. */
1943 mbx_reg = ®->mailbox0;
1944 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1945 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1947 /* Transfer sequence registers. */
1948 iter_reg = fw->xseq_gp_reg;
1949 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
1950 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
1951 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
1952 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
1953 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
1954 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
1955 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
1956 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
1957 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1958 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1959 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1960 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1961 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1962 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1963 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1964 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1966 iter_reg = fw->xseq_0_reg;
1967 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1968 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1969 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1971 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1973 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
1975 /* Receive sequence registers. */
1976 iter_reg = fw->rseq_gp_reg;
1977 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
1978 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
1979 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
1980 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
1981 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
1982 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
1983 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
1984 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
1985 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1986 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1987 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1988 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1989 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1990 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1991 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1992 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1994 iter_reg = fw->rseq_0_reg;
1995 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1996 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1998 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1999 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
2000 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
2002 /* Auxiliary sequence registers. */
2003 iter_reg = fw->aseq_gp_reg;
2004 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
2005 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
2006 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
2007 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
2008 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
2009 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
2010 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
2011 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
2012 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
2013 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
2014 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
2015 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
2016 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
2017 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
2018 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
2019 qla24xx_read_window(reg, 0xB170, 16, iter_reg);
2021 iter_reg = fw->aseq_0_reg;
2022 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
2023 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
2025 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
2026 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
2027 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
2029 /* Command DMA registers. */
2030 iter_reg = fw->cmd_dma_reg;
2031 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
2032 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
2033 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
2034 qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
2037 iter_reg = fw->req0_dma_reg;
2038 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2039 dmp_reg = ®->iobase_q;
2040 for (cnt = 0; cnt < 7; cnt++)
2041 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2043 iter_reg = fw->resp0_dma_reg;
2044 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2045 dmp_reg = ®->iobase_q;
2046 for (cnt = 0; cnt < 7; cnt++)
2047 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2049 iter_reg = fw->req1_dma_reg;
2050 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2051 dmp_reg = ®->iobase_q;
2052 for (cnt = 0; cnt < 7; cnt++)
2053 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2055 /* Transmit DMA registers. */
2056 iter_reg = fw->xmt0_dma_reg;
2057 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
2058 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
2060 iter_reg = fw->xmt1_dma_reg;
2061 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
2062 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
2064 iter_reg = fw->xmt2_dma_reg;
2065 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
2066 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
2068 iter_reg = fw->xmt3_dma_reg;
2069 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
2070 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
2072 iter_reg = fw->xmt4_dma_reg;
2073 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
2074 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
2076 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2078 /* Receive DMA registers. */
2079 iter_reg = fw->rcvt0_data_dma_reg;
2080 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2081 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2083 iter_reg = fw->rcvt1_data_dma_reg;
2084 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2085 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2087 /* RISC registers. */
2088 iter_reg = fw->risc_gp_reg;
2089 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2090 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2091 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2092 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2093 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2094 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2095 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2096 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2098 /* Local memory controller registers. */
2099 iter_reg = fw->lmc_reg;
2100 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2101 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2102 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2103 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2104 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2105 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2106 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2107 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2109 /* Fibre Protocol Module registers. */
2110 iter_reg = fw->fpm_hdw_reg;
2111 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2112 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2113 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2114 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2115 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2116 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2117 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2118 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2119 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2120 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2121 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2122 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2123 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2124 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2125 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2126 qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2128 /* RQ0 Array registers. */
2129 iter_reg = fw->rq0_array_reg;
2130 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2131 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2132 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2133 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2134 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2135 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2136 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2137 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2138 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2139 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2140 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2141 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2142 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2143 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2144 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2145 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2147 /* RQ1 Array registers. */
2148 iter_reg = fw->rq1_array_reg;
2149 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2150 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2151 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2152 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2153 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2154 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2155 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2156 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2157 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2158 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2159 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2160 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2161 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2162 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2163 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2164 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2166 /* RP0 Array registers. */
2167 iter_reg = fw->rp0_array_reg;
2168 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2169 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2170 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2171 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2172 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2173 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2174 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2175 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2176 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2177 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2178 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2179 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2180 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2181 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2182 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2183 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2185 /* RP1 Array registers. */
2186 iter_reg = fw->rp1_array_reg;
2187 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2188 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2189 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2190 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2191 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2192 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2193 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2194 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2195 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2196 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2197 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2198 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2199 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2200 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2201 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2202 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2204 iter_reg = fw->at0_array_reg;
2205 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2206 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2207 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2208 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2209 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2210 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2211 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2212 qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2214 /* I/O Queue Control registers. */
2215 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2217 /* Frame Buffer registers. */
2218 iter_reg = fw->fb_hdw_reg;
2219 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2220 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2221 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2222 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2223 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2224 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2225 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2226 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2227 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2228 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2229 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2230 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2231 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2232 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2233 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2234 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2235 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2236 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2237 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2238 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2239 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2240 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2241 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2242 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2243 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2244 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2245 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2247 /* Multi queue registers */
2248 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2251 rval = qla24xx_soft_reset(ha);
2252 if (rval != QLA_SUCCESS) {
2253 ql_log(ql_log_warn, vha, 0xd00e,
2254 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2257 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2259 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET);
2260 RD_REG_DWORD(®->hccr);
2262 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
2263 RD_REG_DWORD(®->hccr);
2265 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
2266 RD_REG_DWORD(®->hccr);
2268 for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--)
2273 nxt += sizeof(fw->code_ram);
2274 nxt += (ha->fw_memory_size - 0x100000 + 1);
2277 ql_log(ql_log_warn, vha, 0xd010,
2278 "bigger hammer success?\n");
2281 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2283 if (rval != QLA_SUCCESS)
2284 goto qla83xx_fw_dump_failed_0;
2287 nxt = qla2xxx_copy_queues(ha, nxt);
2289 nxt = qla24xx_copy_eft(ha, nxt);
2291 /* Chain entries -- started with MQ. */
2292 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2293 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2294 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
2296 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2297 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2300 /* Adjust valid length. */
2301 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2303 qla83xx_fw_dump_failed_0:
2304 qla2xxx_dump_post_process(base_vha, rval);
2306 qla83xx_fw_dump_failed:
2307 if (!hardware_locked)
2308 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2311 /****************************************************************************/
2312 /* Driver Debug Functions. */
2313 /****************************************************************************/
2316 ql_mask_match(uint32_t level)
2318 if (ql2xextended_error_logging == 1)
2319 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2320 return (level & ql2xextended_error_logging) == level;
2324 * This function is for formatting and logging debug information.
2325 * It is to be used when vha is available. It formats the message
2326 * and logs it to the messages file.
2328 * level: The level of the debug messages to be printed.
2329 * If ql2xextended_error_logging value is correctly set,
2330 * this message will appear in the messages file.
2331 * vha: Pointer to the scsi_qla_host_t.
2332 * id: This is a unique identifier for the level. It identifies the
2333 * part of the code from where the message originated.
2334 * msg: The message to be displayed.
2337 ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2340 struct va_format vaf;
2342 if (!ql_mask_match(level))
2351 const struct pci_dev *pdev = vha->hw->pdev;
2352 /* <module-name> <pci-name> <msg-id>:<host> Message */
2353 pr_warn("%s [%s]-%04x:%ld: %pV",
2354 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2355 vha->host_no, &vaf);
2357 pr_warn("%s [%s]-%04x: : %pV",
2358 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
2366 * This function is for formatting and logging debug information.
2367 * It is to be used when vha is not available and pci is available,
2368 * i.e., before host allocation. It formats the message and logs it
2369 * to the messages file.
2371 * level: The level of the debug messages to be printed.
2372 * If ql2xextended_error_logging value is correctly set,
2373 * this message will appear in the messages file.
2374 * pdev: Pointer to the struct pci_dev.
2375 * id: This is a unique id for the level. It identifies the part
2376 * of the code from where the message originated.
2377 * msg: The message to be displayed.
2380 ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2381 const char *fmt, ...)
2384 struct va_format vaf;
2388 if (!ql_mask_match(level))
2396 /* <module-name> <dev-name>:<msg-id> Message */
2397 pr_warn("%s [%s]-%04x: : %pV",
2398 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
2404 * This function is for formatting and logging log messages.
2405 * It is to be used when vha is available. It formats the message
2406 * and logs it to the messages file. All the messages will be logged
2407 * irrespective of value of ql2xextended_error_logging.
2409 * level: The level of the log messages to be printed in the
2411 * vha: Pointer to the scsi_qla_host_t
2412 * id: This is a unique id for the level. It identifies the
2413 * part of the code from where the message originated.
2414 * msg: The message to be displayed.
2417 ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2420 struct va_format vaf;
2423 if (level > ql_errlev)
2427 const struct pci_dev *pdev = vha->hw->pdev;
2428 /* <module-name> <msg-id>:<host> Message */
2429 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2430 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2432 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2433 QL_MSGHDR, "0000:00:00.0", id);
2435 pbuf[sizeof(pbuf) - 1] = 0;
2443 case ql_log_fatal: /* FATAL LOG */
2444 pr_crit("%s%pV", pbuf, &vaf);
2447 pr_err("%s%pV", pbuf, &vaf);
2450 pr_warn("%s%pV", pbuf, &vaf);
2453 pr_info("%s%pV", pbuf, &vaf);
2461 * This function is for formatting and logging log messages.
2462 * It is to be used when vha is not available and pci is available,
2463 * i.e., before host allocation. It formats the message and logs
2464 * it to the messages file. All the messages are logged irrespective
2465 * of the value of ql2xextended_error_logging.
2467 * level: The level of the log messages to be printed in the
2469 * pdev: Pointer to the struct pci_dev.
2470 * id: This is a unique id for the level. It identifies the
2471 * part of the code from where the message originated.
2472 * msg: The message to be displayed.
2475 ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2476 const char *fmt, ...)
2479 struct va_format vaf;
2484 if (level > ql_errlev)
2487 /* <module-name> <dev-name>:<msg-id> Message */
2488 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2489 QL_MSGHDR, dev_name(&(pdev->dev)), id);
2490 pbuf[sizeof(pbuf) - 1] = 0;
2498 case ql_log_fatal: /* FATAL LOG */
2499 pr_crit("%s%pV", pbuf, &vaf);
2502 pr_err("%s%pV", pbuf, &vaf);
2505 pr_warn("%s%pV", pbuf, &vaf);
2508 pr_info("%s%pV", pbuf, &vaf);
2516 ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
2519 struct qla_hw_data *ha = vha->hw;
2520 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2521 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2522 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2523 uint16_t __iomem *mbx_reg;
2525 if (!ql_mask_match(level))
2529 mbx_reg = ®82->mailbox_in[0];
2530 else if (IS_FWI2_CAPABLE(ha))
2531 mbx_reg = ®24->mailbox0;
2533 mbx_reg = MAILBOX_REG(ha, reg, 0);
2535 ql_dbg(level, vha, id, "Mailbox registers:\n");
2536 for (i = 0; i < 6; i++)
2537 ql_dbg(level, vha, id,
2538 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
2543 ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2544 uint8_t *b, uint32_t size)
2549 if (!ql_mask_match(level))
2552 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
2553 "9 Ah Bh Ch Dh Eh Fh\n");
2554 ql_dbg(level, vha, id, "----------------------------------"
2555 "----------------------------\n");
2557 ql_dbg(level, vha, id, " ");
2558 for (cnt = 0; cnt < size;) {
2560 printk("%02x", (uint32_t) c);
2568 ql_dbg(level, vha, id, "\n");