1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Marvell 88SE64xx/88SE94xx main function head file
5 * Copyright 2007 Red Hat, Inc.
6 * Copyright 2008 Marvell. <kewei@marvell.com>
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/delay.h>
17 #include <linux/types.h>
18 #include <linux/ctype.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/pci.h>
21 #include <linux/platform_device.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/slab.h>
25 #include <linux/vmalloc.h>
26 #include <asm/unaligned.h>
27 #include <scsi/libsas.h>
28 #include <scsi/scsi.h>
29 #include <scsi/scsi_tcq.h>
30 #include <scsi/sas_ata.h>
33 #define DRV_NAME "mvsas"
34 #define DRV_VERSION "0.8.16"
35 #define MVS_ID_NOT_MAPPED 0x7f
36 #define WIDE_PORT_MAX_PHY 4
37 #define mv_printk(fmt, arg ...) \
38 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
40 #define mv_dprintk(format, arg...) \
41 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
43 #define mv_dprintk(format, arg...)
45 #define MV_MAX_U32 0xffffffff
47 extern int interrupt_coalescing;
48 extern struct mvs_tgt_initiator mvs_tgt;
49 extern struct mvs_info *tgt_mvi;
50 extern const struct mvs_dispatch mvs_64xx_dispatch;
51 extern const struct mvs_dispatch mvs_94xx_dispatch;
53 #define DEV_IS_EXPANDER(type) \
54 ((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))
56 #define bit(n) ((u64)1 << n)
58 #define for_each_phy(__lseq_mask, __mc, __lseq) \
59 for ((__mc) = (__lseq_mask), (__lseq) = 0; \
61 (++__lseq), (__mc) >>= 1)
63 #define MVS_PHY_ID (1U << sas_phy->id)
64 #define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
65 #define UNASSOC_D2H_FIS(id) \
66 ((void *) mvi->rx_fis + 0x100 * id)
67 #define SATA_RECEIVED_FIS_LIST(reg_set) \
68 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
69 #define SATA_RECEIVED_SDB_FIS(reg_set) \
70 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
71 #define SATA_RECEIVED_D2H_FIS(reg_set) \
72 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
73 #define SATA_RECEIVED_PIO_FIS(reg_set) \
74 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
75 #define SATA_RECEIVED_DMA_FIS(reg_set) \
76 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
94 int (*chip_init)(struct mvs_info *mvi);
95 int (*spi_init)(struct mvs_info *mvi);
96 int (*chip_ioremap)(struct mvs_info *mvi);
97 void (*chip_iounmap)(struct mvs_info *mvi);
98 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
99 u32 (*isr_status)(struct mvs_info *mvi, int irq);
100 void (*interrupt_enable)(struct mvs_info *mvi);
101 void (*interrupt_disable)(struct mvs_info *mvi);
103 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
104 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
106 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
107 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
108 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
110 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
111 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
112 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
114 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
115 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
117 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
118 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
120 void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
121 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
122 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
124 void (*start_delivery)(struct mvs_info *mvi, u32 tx);
125 u32 (*rx_update)(struct mvs_info *mvi);
126 void (*int_full)(struct mvs_info *mvi);
127 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
128 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
129 u32 (*prd_size)(void);
130 u32 (*prd_count)(void);
131 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
132 void (*detect_porttype)(struct mvs_info *mvi, int i);
133 int (*oob_done)(struct mvs_info *mvi, int i);
134 void (*fix_phy_info)(struct mvs_info *mvi, int i,
135 struct sas_identify_frame *id);
136 void (*phy_work_around)(struct mvs_info *mvi, int i);
137 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
138 struct sas_phy_linkrates *rates);
139 u32 (*phy_max_link_rate)(void);
140 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
141 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
142 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
143 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
144 void (*clear_active_cmds)(struct mvs_info *mvi);
145 u32 (*spi_read_data)(struct mvs_info *mvi);
146 void (*spi_write_data)(struct mvs_info *mvi, u32 data);
147 int (*spi_buildcmd)(struct mvs_info *mvi,
154 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
155 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
156 void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
157 int buf_len, int from, void *prd);
158 void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
159 void (*non_spec_ncq_error)(struct mvs_info *mvi);
160 int (*gpio_write)(struct mvs_prv_info *mvs_prv, u8 reg_type,
161 u8 reg_index, u8 reg_count, u8 *write_data);
165 struct mvs_chip_info {
173 const struct mvs_dispatch *dispatch;
175 #define MVS_MAX_SG (1U << mvi->chip->sg_width)
176 #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
177 #define MVS_RX_FISL_SZ \
178 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
179 #define MVS_CHIP_DISP (mvi->chip->dispatch)
181 struct mvs_err_info {
187 __le32 flags; /* PRD tbl len; SAS, SATA ctl */
188 __le32 lens; /* cmd, max resp frame len */
189 __le32 tags; /* targ port xfer tag; tag */
190 __le32 data_len; /* data xfer len */
191 __le64 cmd_tbl; /* command table address */
192 __le64 open_frame; /* open addr frame address */
193 __le64 status_buf; /* status buffer address */
194 __le64 prd_tbl; /* PRD tbl address */
199 struct asd_sas_port sas_port;
202 struct list_head list;
206 struct mvs_info *mvi;
207 struct mvs_port *port;
208 struct asd_sas_phy sas_phy;
209 struct sas_identify identify;
210 struct scsi_device *sdev;
211 struct timer_list timer;
213 u64 att_dev_sas_addr;
225 enum sas_linkrate minimum_linkrate;
226 enum sas_linkrate maximum_linkrate;
230 struct list_head dev_entry;
231 enum sas_device_type dev_type;
232 struct mvs_info *mvi_info;
233 struct domain_device *sas_device;
242 /* Generate PHY tunning parameters */
244 /* 1 bit, transmitter emphasis enable */
246 /* 4 bits, transmitter emphasis amplitude */
248 /* 3 bits, reserved space */
249 u8 Reserved_2bit_1:3;
250 /* 5 bits, transmitter amplitude */
252 /* 2 bits, transmitter amplitude adjust */
254 /* 1 bit, reserved space */
256 /* 2 bytes, reserved space */
261 /* 4 bits, FFE Capacitor Select (value range 0~F) */
263 /* 3 bits, FFE Resistor Select (value range 0~7) */
270 * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
271 * The data area is valid only Signature="MRVL".
272 * If any member fills with 0xFF, the member is invalid.
274 struct hba_info_page {
276 /* 4 bytes, structure signature,should be "MRVL" at first initial */
283 /* 64 bytes, SAS address for each port */
287 /* 8 bytes for vanir 8 port PHY FFE seeting
288 * BIT 0~3 : FFE Capacitor select(value range 0~F)
289 * BIT 4~6 : FFE Resistor select(value range 0~7)
293 struct ffe_control ffe_ctl[8];
298 /* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */
302 /* 32 bytes, PHY tuning parameters for each PHY*/
303 struct phy_tuning phy_tuning[8];
307 }; /* total 256 bytes */
309 struct mvs_slot_info {
310 struct list_head entry;
312 struct sas_task *task;
319 /* DMA buffer for storing cmd tbl, open addr frame, status buffer,
325 struct mvs_port *port;
326 struct mvs_device *device;
337 struct pci_dev *pdev;
340 /* enhanced mode registers */
343 /* peripheral or soc registers */
344 void __iomem *regs_ex;
345 u8 sas_addr[SAS_ADDR_SIZE];
348 struct sas_ha_struct *sas;
349 struct Scsi_Host *shost;
351 /* TX (delivery) DMA ring */
355 /* cached next-producer idx */
358 /* RX (completion) DMA ring */
362 /* RX consumer idx */
367 dma_addr_t rx_fis_dma;
369 /* DMA command header slots */
370 struct mvs_cmd_hdr *slot;
374 const struct mvs_chip_info *chip;
378 /* further per-slot information */
379 struct mvs_phy phy[MVS_MAX_PHYS];
380 struct mvs_port port[MVS_MAX_PHYS];
383 struct list_head *hba_list;
384 struct list_head soc_entry;
385 struct list_head wq_list;
386 unsigned long instance;
392 struct hba_info_page hba_info_param;
393 struct mvs_device devices[MVS_MAX_DEVICES];
395 dma_addr_t bulk_buffer_dma;
397 dma_addr_t bulk_buffer_dma1;
398 #define TRASH_BUCKET_SIZE 0x20000
400 struct mvs_slot_info slot_info[0];
408 struct mvs_info *mvi[2];
409 struct tasklet_struct mv_tasklet;
413 struct delayed_work work_q;
414 struct mvs_info *mvi;
417 struct list_head entry;
420 struct mvs_task_exec_info {
421 struct sas_task *task;
422 struct mvs_cmd_hdr *hdr;
423 struct mvs_port *port;
428 /******************** function prototype *********************/
429 void mvs_get_sas_addr(void *buf, u32 buflen);
430 void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
431 void mvs_tag_free(struct mvs_info *mvi, u32 tag);
432 void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
433 int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
434 void mvs_tag_init(struct mvs_info *mvi);
435 void mvs_iounmap(void __iomem *regs);
436 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
437 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
438 int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
440 void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
441 u32 off_hi, u64 sas_addr);
442 void mvs_scan_start(struct Scsi_Host *shost);
443 int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
444 int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags);
445 int mvs_abort_task(struct sas_task *task);
446 int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
447 int mvs_clear_aca(struct domain_device *dev, u8 *lun);
448 int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
449 void mvs_port_formed(struct asd_sas_phy *sas_phy);
450 void mvs_port_deformed(struct asd_sas_phy *sas_phy);
451 int mvs_dev_found(struct domain_device *dev);
452 void mvs_dev_gone(struct domain_device *dev);
453 int mvs_lu_reset(struct domain_device *dev, u8 *lun);
454 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
455 int mvs_I_T_nexus_reset(struct domain_device *dev);
456 int mvs_query_task(struct sas_task *task);
457 void mvs_release_task(struct mvs_info *mvi,
458 struct domain_device *dev);
459 void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
460 struct domain_device *dev);
461 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
462 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
463 int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
464 struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
465 int mvs_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
466 u8 reg_count, u8 *write_data);